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| Data Sheet August 18, 2004 MARS(R)2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Features One of the next-generation, system-on-a-chip devices of Agere Systems' multiservice access & rate solutions MARSTM family of framers. Transmission convergence and SONET/SDH terminal functionality for linear networks. Versatile IC supports 155/622/2488 Mbits/s SONET/SDH interface solutions for packet over SONET (POS), packet over fiber (POF), or asynchronous transfer mode (ATM) applications. Low-power 1.6 V/3.3 V operation. -- IETF RFC 2615: PPP over SONET/SDH. -- IETF RFC 1661: The Point-to-Point Protocol (PPP). -- IETF RFC 1662: PPP in HDLC-like Framing. Data Processing SONET/SDH Interface Termination of quad STS-3/STM-1, quad STS-12/STM-4, or single STS-48/STM-16. Supports overhead processing for transport and path overhead bytes. Optional insertion and extraction of overhead bytes via serial overhead interface. STS pointer processing to align the receive frame to the system frame. Support for 1 + 1 and 1:1 linear networks. Full path termination and SPE extraction/insertion. SONET/SDH compliant condition and alarm reporting. Handles all concatenation levels of STS-3c to STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.). Built-in diagnostic loopback modes. Compliant with the following Telcordia Technologies(R), ANSI(R), and ITU standards: -- GR-253 CORE: SONET Transport Systems: Common Generic Criteria. -- ITU-T G.707: Network Node Interface for the Synchronous Digital Hierarchy. -- ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy. -- T1.105: SONET-Basic Description including Multiplex Structure, Rates, and Formats. -- T1.105.02 SONET-Payload Mappings. -- T1.105.03 SONET-Jitter at Network Interfaces. -- T1.105.06 SONET Physical Layer Specifications. -- T1.105.07 SONET-Sub-STS-1 Interface Rates and Formats Specification. -- ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification. Provisionable data engine supports payload insertion/extraction for PPP, ATM, or HDLC streams. Extraction and insertion of DS3 frames containing HDLC or ATM data streams for up to 16 channels. Integrated UTOPIA Level 2 and Level 3 compatible physical layer interface for packets or ATM cells. Provides/supports internal E3 mapping. Supports DS3/PLCP and clear channel DS3 mapping. Insertion and extraction of up to 16 separate data channels. Direct cell/packet over fiber interface device. Compliant with ATM forum, ITU standards, and IETF standards. Supports generic framing procedure (GFP) protocol. Interfaces Enhanced UTOPIA interface for cell and packet transfer. IEEE(R) 1149.1 port with BIST, scan, and boundry scan. Microprocessor Interface Up to 66 MHz synchronous. 16-bit address and 16-bit data interface. Synchronous or asynchronous modes available. Configurable to operate with most commercial microprocessors. MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Table of Contents Contents Page Features ................................................................................................................................................................... 1 SONET/SDH Interface ....................................................................................................................................... 1 Data Processing................................................................................................................................................. 1 Interfaces ........................................................................................................................................................... 1 Microprocessor Interface ................................................................................................................................... 1 Description.............................................................................................................................................................. 27 Generic Framing Procedure (GFP) .................................................................................................................. 28 Target Applications Supported ............................................................................................................................... 29 MARS2G5 P-Pro (600-Pin LBGA and 792-Pin PBGA) .................................................................................... 29 MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 30 MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 31 Overview................................................................................................................................................................. 32 Clocking ........................................................................................................................................................... 34 MARS2G5 P-Pro (792-Pin PBGA) Low-Speed Devices Available......................................................................... 36 MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 36 MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 36 MARS2G5 P-Pro Device Product Line Table Summaries...................................................................................... 37 Pin Information ....................................................................................................................................................... 38 792-Pin PBGA Pin Assignments ...................................................................................................................... 38 600-Pin LBGA Pin Assignments ...................................................................................................................... 87 Pin Descriptions...................................................................................................................................................... 97 Microprocessor (MPU) Interface........................................................................................................................... 123 Device Address Space Assignments ............................................................................................................. 123 Microprocessor Interface Modes.................................................................................................................... 124 Microprocessor Interface Timing.................................................................................................................... 125 Necessary Register Provisioning Sequence and Clocks ............................................................................... 133 Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers....................................................... 134 Performance Monitor (PM) Reset .................................................................................................................. 158 General-Purpose Input/Output Interface ........................................................................................................ 160 Interrupts ........................................................................................................................................................ 162 Loopback Operation....................................................................................................................................... 163 MPU Register Descriptions ............................................................................................................................ 164 MPU Register Map......................................................................................................................................... 173 Functional Description .......................................................................................................................................... 175 Line Interface........................................................................................................................................................ 176 LVPECL I/O Termination and Load Specifications ........................................................................................ 178 Line Interface I/O Timing................................................................................................................................ 180 Transport Overhead Processor (TOHP-48) Block................................................................................................ 184 Introduction .................................................................................................................................................... 184 TOHP-48 Functional Block Diagram .............................................................................................................. 184 Enhancements ............................................................................................................................................... 186 APSMON and K2MON Processing (Including K1K2 Validation and Pass Through) ..................................... 186 TOHP-48 Receive Direction........................................................................................................................... 187 Transmit Direction (to SONET/SDH line) ....................................................................................................... 197 Receive/Transmit TOHP-48 Interface ............................................................................................................ 204 TOHP-48 Register Descriptions..................................................................................................................... 208 TOHP-48 Register Map ................................................................................................................................. 237 Pointer Processor (PP)......................................................................................................................................... 247 Introduction .................................................................................................................................................... 247 Detailed Description ....................................................................................................................................... 250 PP Register Map Overview ............................................................................................................................ 257 PP Register Descriptions ............................................................................................................................... 258 2 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Table of Contents (continued) Contents Page PP Register Map ............................................................................................................................................ 317 Path Terminator (PT)............................................................................................................................................ 345 Introduction .................................................................................................................................................... 345 SPE Mapper................................................................................................................................................... 346 Supported SPE Formats ................................................................................................................................ 349 SPE Mapper Architecture............................................................................................................................... 352 Transpose Block ............................................................................................................................................ 356 PT Register Descriptions ............................................................................................................................... 357 PT Register Map (Entire PT Except RXT Block)............................................................................................ 385 STS Receive Terminator (RXT) Block.................................................................................................................. 391 Introduction .................................................................................................................................................... 391 Receive Timing Functions.............................................................................................................................. 393 Pointer Interpreter Functions.......................................................................................................................... 394 Concatenation ................................................................................................................................................ 398 RXT Register Descriptions............................................................................................................................. 414 RXT Register Map.......................................................................................................................................... 460 DS3/E3 Block ....................................................................................................................................................... 486 DS3 Functional Description............................................................................................................................ 486 DS3 Transmit Direction .................................................................................................................................. 494 FIFO Block ..................................................................................................................................................... 494 DS3 PLCP Frame/Data Insert........................................................................................................................ 495 DS3 Frame Generate/OH Bit Inserter ............................................................................................................ 497 Transparent Payload Mode (Used in Conjunction with DS3 Mapping) .......................................................... 498 E3 Functional Description .............................................................................................................................. 499 DS3 Register Descriptions ............................................................................................................................. 518 E3 Register Descriptions................................................................................................................................ 550 DS3 Register Map.......................................................................................................................................... 582 E3 Register Map ............................................................................................................................................ 595 Appendix: DS3 to STS-1 Mapping ................................................................................................................. 609 Receive Sequencer (RXS) Block.......................................................................................................................... 611 Introduction .................................................................................................................................................... 611 RXS PRBS Monitor ........................................................................................................................................ 612 RXS Register Descriptions............................................................................................................................. 613 RXS Register Maps........................................................................................................................................ 618 Data Engine Block ................................................................................................................................................ 623 Data Engine Block--Subblocks ..................................................................................................................... 623 Data Engine Block--ATM Framer/Frame Inserter Subblock................................................................................ 624 Overview ........................................................................................................................................................ 624 Capabilities..................................................................................................................................................... 624 Architecture .................................................................................................................................................... 626 Data Engine Block--HDLC Framer and Escaper Subblock ................................................................................. 627 Introduction .................................................................................................................................................... 627 Features ......................................................................................................................................................... 627 Byte-Synchronous Mode................................................................................................................................ 628 Examples of Byte-Synchronous Mode Escaper Operation ............................................................................ 629 Examples of Byte-Synchronous Mode Framer Operation.............................................................................. 631 Bit-Synchronous Mode................................................................................................................................... 632 Examples of Bit-Synchronous Mode Framer Operation................................................................................. 634 Examples of Bit-Synchronous Mode Escaper Operation ............................................................................... 635 Data Engine Block--CRC Generator/Checker Subblock ..................................................................................... 636 Overview ........................................................................................................................................................ 636 Agere Systems Inc. 3 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Table of Contents (continued) Contents Page Receive .......................................................................................................................................................... 636 Transmit ......................................................................................................................................................... 639 Examples of CRC Insertion/Testing ............................................................................................................... 641 Data Engine Block--PPP Detach Subblock ......................................................................................................... 645 PPP Header Detach....................................................................................................................................... 645 Data Engine Block--Data Engine Counter Subblock ........................................................................................... 648 Introduction .................................................................................................................................................... 648 Overview ........................................................................................................................................................ 648 Implementation .............................................................................................................................................. 648 Data Engine Block--Channel Distribution and Allocation Subblock..................................................................... 651 Channel Distribution and Allocation Subblock Description ............................................................................ 651 Operation and Programming of the CDA Maps ............................................................................................. 652 Data Engine Block--GFP General Framing Procedure Subblock........................................................................ 668 Introduction .................................................................................................................................................... 668 Overview ........................................................................................................................................................ 668 GFP Control Messages.................................................................................................................................. 670 GFP Frame Delineation/Frame Insertion ....................................................................................................... 671 GFP Scrambling/Descrambling...................................................................................................................... 673 Packet-Over-Wavelength Mode ..................................................................................................................... 676 Data Engine Block Registers................................................................................................................................ 677 DE Register Descriptions ............................................................................................................................... 677 DE Register Map............................................................................................................................................ 703 UTOPIA (UT) Block .............................................................................................................................................. 716 UTOPIA Interface Features ........................................................................................................................... 716 UTOPIA Modes .............................................................................................................................................. 718 32-Bit Mode Configuration (Necessary Configuration for Proper Operation)................................................. 718 UT Receive Path (Ingress)............................................................................................................................. 721 UT Transmit Path (Egress) ............................................................................................................................ 724 Address Modes and Pin Assignments of MPHY Interfaces ........................................................................... 726 UTOPIA Loopbacks ....................................................................................................................................... 729 Basic Modes of Operations ............................................................................................................................ 730 Mixed Modes of Operations ........................................................................................................................... 739 Reference Configurations .............................................................................................................................. 741 UTOPIA Interface Pin Description ................................................................................................................. 742 FIFO Ganging ................................................................................................................................................ 744 Packet Packing .............................................................................................................................................. 744 Default Channel Configuration ....................................................................................................................... 744 UTOPIA Interface Timing ............................................................................................................................... 745 UT Global Registers....................................................................................................................................... 748 UT Per-Interface Registers ............................................................................................................................ 750 UT Register Map ............................................................................................................................................ 764 System Interface................................................................................................................................................... 772 ATM Interfaces............................................................................................................................................... 772 POS Interfaces............................................................................................................................................... 775 Test....................................................................................................................................................................... 778 Scan ............................................................................................................................................................... 778 Boundary Scan .............................................................................................................................................. 778 RAM BIST ...................................................................................................................................................... 778 GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only) ................................................................. 786 Introduction .................................................................................................................................................... 793 4 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Figures Figure Page Figure 1. MARS2G5 P-Pro Block Diagram ............................................................................................................ 27 Figure 2. GFP Relationship to Transport Payloads ............................................................................................... 28 Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 29 Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 30 Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram ....................................................................... 31 Figure 6. MARS2G5 P-Pro External Interfaces ..................................................................................................... 33 Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode ................................................................ 34 Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode .......................................................................... 35 Figure 9. PLL Outputs Lock-In Process ............................................................................................................... 122 Figure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1) ......................... 125 Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1) ........................ 127 Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0) .... 129 Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ................................. 131 Figure 14. PM Reset Signal Generation .............................................................................................................. 159 Figure 15. General Input/Output (GPIO) ............................................................................................................. 161 Figure 16. Interrupt Functionality ......................................................................................................................... 162 Figure 17. Loopback Operation ........................................................................................................................... 163 Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block .............................................. 175 Figure 19. Line Interface ...................................................................................................................................... 177 Figure 20. LVPECL Load Connections ................................................................................................................ 179 Figure 21. Receive Line-Side Timing Waveform ................................................................................................. 180 Figure 22. Transmit Line-Side Timing Waveform--OC-48 Contraclocking ......................................................... 181 Figure 23. Transmit Line-Side Timing Waveform--OC-48 Forward Clocking ..................................................... 181 Figure 24. Transmit Line-Side Timing Waveform--Frame Sync ......................................................................... 181 Figure 25. High-Level Block Interconnect ............................................................................................................ 184 Figure 26. TOHP-48 Block Diagram (One Channel) ........................................................................................... 185 Figure 27. Time-Slot Assignments ...................................................................................................................... 194 Figure 28. REI-L (MS-REI) Location .................................................................................................................... 202 Figure 29. RTOH Interface .................................................................................................................................. 205 Figure 30. TTOH Interface ................................................................................................................................... 205 Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing ..................... 206 Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing .............................................. 206 Figure 33. STS-3/STM-1 Receive TOAC Interface Timing .................................................................................. 207 Figure 34. Signal Degrade and Failure Parameters for BER .............................................................................. 228 Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor ........................ 250 Figure 36. Top Level Block Diagram of the Pointer Processor Block .................................................................. 251 Figure 37. Overview of Pointer Processor Register Map .................................................................................... 257 Figure 38. Path Terminator Block Diagram ......................................................................................................... 345 Figure 39. Block Diagram of SPE Mapper Block ................................................................................................. 346 Figure 40. Direct Mapping into STS SPE ............................................................................................................ 349 Figure 41. STS-Nc SPE ....................................................................................................................................... 349 Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE ................................................................................ 350 Figure 43. Asynchronous Mapping of E3 into STS-1 SPE .................................................................................. 351 Figure 44. STS-48 Frame Structure .................................................................................................................... 352 Figure 45. STS-12 Frame Structure .................................................................................................................... 353 Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator ............. 391 Figure 47. STS Receive Terminator (RXT) Functional Block Diagram ............................................................... 392 Figure 48. Interpreter State Machine ................................................................................................................... 394 Figure 49. STS-12 RXT Concatenated Offset Passing ....................................................................................... 398 Figure 50. STS-6 RXT Concatenated Offset Passing ......................................................................................... 398 Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing ....................................................................... 399 Agere Systems Inc. 5 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Figures (continued) Figure Page Figure 52. STS-6c Offset Passing in an STS-12 RXT ......................................................................................... 399 Figure 53. Concatenated Offset Passing ............................................................................................................. 400 Figure 54. Overview of RXT Register Map .......................................................................................................... 414 Figure 55. DS3 Block Interface Diagram ............................................................................................................. 486 Figure 56. DS3 Receive Subblock ....................................................................................................................... 487 Figure 57. DS3/E3 Mappings .............................................................................................................................. 499 Figure 58. VC-3 Into an AU-3 .............................................................................................................................. 500 Figure 59. Asynchronous Mapping of 34,368 kbits/s Tributary Into VC-3 ........................................................... 501 Figure 60. G.832 E3 Frame Structure at 34,368 kbits/s ...................................................................................... 502 Figure 61. DS3 Multiframe Format ...................................................................................................................... 609 Figure 62. PLCP Mapping of ATM Cells .............................................................................................................. 610 Figure 63. MARS2G5 P-Pro PRBS Monitor/Generator Locations ....................................................................... 612 Figure 64. ATM Cell Format ................................................................................................................................ 624 Figure 65. Alpha-Delta Framer State Machine .................................................................................................... 626 Figure 66. Legend for Escaper Examples ........................................................................................................... 629 Figure 67. Escaping and EOP ............................................................................................................................. 629 Figure 68. Escaping Dry and Abort ..................................................................................................................... 630 Figure 69. Aborting a Dry .................................................................................................................................... 630 Figure 70. Framing and EOP ............................................................................................................................... 631 Figure 71. Framing Dry and Abort ....................................................................................................................... 631 Figure 72. Aborting a Dry .................................................................................................................................... 631 Figure 73. Bit-Synchronous HDLC Framer Operation ......................................................................................... 634 Figure 74. Bit-Synchronous HDLC Abort ............................................................................................................. 634 Figure 75. Bit-Synchronous HDLC Escaper Operation ....................................................................................... 635 Figure 76. Bit-Synchronous HDLC Escaper Abort .............................................................................................. 635 Figure 77. CRC-16 Checker Data Arriving Across Two Words ........................................................................... 636 Figure 78. CRC-32 Check Arriving Across Two Words ....................................................................................... 637 Figure 79. A CRC-16/32 Checker Circuit ............................................................................................................ 638 Figure 80. Normal CRC-16 and CRC-32 Cases .................................................................................................. 639 Figure 81. CRC Generator Block Diagram .......................................................................................................... 640 Figure 82. Assorted CRC Generator Cases ........................................................................................................ 641 Figure 83. Assorted CRC Generator Cases ........................................................................................................ 642 Figure 84. Assorted CRC Checker Cases ........................................................................................................... 643 Figure 85. Assorted CRC Checker Cases ........................................................................................................... 644 Figure 86. DE Counter Block ............................................................................................................................... 649 Figure 87. GFP Encapsulations of Packet Data .................................................................................................. 669 Figure 88. Special-Purpose GFP Header Definitions .......................................................................................... 669 Figure 89. Special-Purpose GFP Header Definitions .......................................................................................... 672 Figure 90. X43 Self-Synchronous Scrambler/Descrambler ................................................................................. 674 Figure 91. X48 Set-Reset Scrambler ................................................................................................................... 675 Figure 92. X48 Scrambler Synchronization State Machine ................................................................................. 676 Figure 93. UT48: Generic Structure of UTOPIA Block ........................................................................................ 717 Figure 94. Receive-Side Interface Handshaking in Point-to-Point Mode (RXPPA as Single Cycle) ................... 723 Figure 95. Transmit-Side Interface Handshaking in Point-to-Point Mode (TXPPA as Single Cycle) .................. 725 Figure 96. Near-End Loopback for Slice D .......................................................................................................... 729 Figure 97. Overall Structure for Receive Direction .............................................................................................. 731 Figure 98. Overall Structure for Transmit Direction ............................................................................................. 732 Figure 99. Four Groups of Multi-PHY Devices of Four Channels for Receive Direction ..................................... 733 Figure 100. Four Groups of Multi-PHY Devices of Four Channels for Transmit Direction .................................. 734 Figure 101. Two Groups of Multi-PHY Devices of Eight Channels for Receive Direction ................................... 735 Figure 102. Two Groups of Multi-PHY Devices of Eight Channels for Transmit Direction .................................. 736 6 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Figures (continued) Figure Page Figure 103. A Multi-PHY Device of 16 Channels for Receive 16-Bit or 8-Bit Modes ........................................... 737 Figure 104. A Multi-PHY Device of 16 Channels of Receive 32-Bit Mode .......................................................... 738 Figure 105. Mixed Modes of Operations for Receive Direction ........................................................................... 739 Figure 106. Mixed Modes of Operation of the Receive Side and the Transmit Side ........................................... 740 Figure 107. Reference Configurations ................................................................................................................. 741 Figure 108. Transmit UTOPIA Interface Timing .................................................................................................. 745 Figure 109. Receive UTOPIA Interface Timing ................................................................................................... 746 Figure 110. Quad 16-Bit ATM Level 2 ................................................................................................................. 772 Figure 111. Quad 8-Bit ATM Level 3 ................................................................................................................... 773 Figure 112. Single 32-Bit ATM Level 3 ................................................................................................................ 774 Figure 113. Quad 16-Bit POS Level 2 ................................................................................................................. 775 Figure 114. Quad 8-Bit POS Level 3 ................................................................................................................... 776 Figure 115. Single 32-Bit POS Level 3 ................................................................................................................ 777 Agere Systems Inc. 7 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables Table Page Table 1. List of the Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode.................................................. 34 Table 2. MARS2G5 P-Pro Device Product Line--Data Port Summary.................................................................. 37 Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order ....................................... 38 Table 4. Pin Assignments for 792-Pin PBGA by Signal Name............................................................................... 62 Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order....................................................................... 87 Table 6. Pin Assignments for 600-Pin LBGA by Signal Name ............................................................................... 92 Table 7. Pin Descriptions--Line Interface Signals ................................................................................................. 97 Table 8. Pin Descriptions--TOH Interface Signals............................................................................................... 102 Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals........................................................................ 104 Table 10. Pin Descriptions--Microprocessor Interface Signals............................................................................ 117 Table 11. Pin Descriptions--General-Purpose I/O Signals: Interface Signals ..................................................... 118 Table 12. Pin Descriptions--JTAG Interface Signals ........................................................................................... 119 Table 13. Pin Descriptions--Power Signals ......................................................................................................... 120 Table 14. PLL Test Outputs.................................................................................................................................. 122 Table 15. Pin Descriptions--No-Connect Pins..................................................................................................... 122 Table 16. Leakage Test Pin.................................................................................................................................. 122 Table 17. Device Address Space Assignment ..................................................................................................... 123 Table 18. MPU Modes.......................................................................................................................................... 124 Table 19. Microprocessor Interface Synchronous Write Cycle Specifications ..................................................... 126 Table 20. Microprocessor Interface Synchronous Read Cycle Specifications ..................................................... 128 Table 21. Microprocessor Interface Asynchronous Write Cycle Specifications.................................................... 130 Table 22. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................... 132 Table 23. PM Reset Signal Provisioning .............................................................................................................. 158 Table 24. MPU_VERR[0--5], Version Control Registers (RO) ............................................................................ 164 Table 25. MPU_ISR, Interrupt Status Register (RO or COR/W) .......................................................................... 165 Table 26. MPU_CNDR, Condition Register (RO)................................................................................................. 166 Table 27. MPU_IMR, Interrupt Mask Register (R/W) ........................................................................................... 166 Table 28. MPU_ICLRR, Interrupt Clear Register (R/W) ....................................................................................... 167 Table 29. MPU_SWRSR, Software Reset Register (R/W)................................................................................... 167 Table 30. MPU_GPIO_CTLR, GPIO Output Value (R/W).................................................................................... 168 Table 31. MPU_PROVISION0, Provisioning Register 0 (R/W) ............................................................................ 168 Table 32. MPU_PROVISION1, Provisioning Register 1 (R/W) ............................................................................ 168 Table 33. MPU_LPBKCTLR, Loopback Control Register (R/W) .......................................................................... 169 Table 34. MPU_GPIOCFG, GPIO Configuration Register (R/W)......................................................................... 169 Table 35. MPU_GPIO_OER[1--2], GPIO Output Enable (R/W).......................................................................... 170 Table 36. MPU_PDN1, Powerdown Register 1 (R/W) ......................................................................................... 171 Table 37. MPU_PDN2, Powerdown Register 2 (R/W) ......................................................................................... 171 Table 38. MPU_PDN3, Powerdown Register 3 (R/W) ......................................................................................... 171 Table 39. MPU_SCRATCHR, Scratch Register (R/W)......................................................................................... 171 Table 40. MPU_TDAT16_MODER, MARS2G5 P-Pro Mode Selection Register (R/W)....................................... 171 Table 41. MPU_LI_MODER, Register (R/W) ....................................................................................................... 172 Table 42. MPU_HSI_TST_CTL, High-Speed Interface Control ........................................................................... 172 Table 43. MPU_HSI_LPBKR, High-Speed Interface Loopback Register............................................................. 172 Table 44. MPU Register Map ............................................................................................................................... 173 Table 45. Line Interface Modes ............................................................................................................................ 177 Table 46. Nominal dc Power for Suggested Terminations ................................................................................... 179 Table 47. Receive Line-Side Timing Specifications ............................................................................................. 182 Table 48. Transmit Line-Side Timing Specifications ............................................................................................ 183 Table 49. Framing Bytes Observed for Framing Integrity..................................................................................... 188 Table 50. TOAC Channel Output Versus Time-Slot Assignment ......................................................................... 195 Table 51. Transport Overhead Bytes Received Via RxTOAC Interface............................................................... 196 8 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 52. TOAC Channel Input Versus Time-Slot Assignments .......................................................................... 198 Table 53. TTOAC OC-3 Signal Definition............................................................................................................. 198 Table 54. TTOAC OC-12 Signal Definition........................................................................................................... 199 Table 55. TTOAC OC-48 Signal Definition........................................................................................................... 200 Table 56. TTOAC Control Bits.............................................................................................................................. 201 Table 57. Rx/Tx TOHP-48 Interface Rates........................................................................................................... 204 Table 58. Transmit TOAC Interface Timing Specifications................................................................................... 206 Table 59. Receive TOAC Interface Timing Specifications.................................................................................... 207 Table 60. TOHP_MODE_VERR, Mode (R/W) and Block Version (RO)............................................................... 208 Table 61. TOHP_CH_INT, Channel Interrupt (R/W, RO) ..................................................................................... 208 Table 62. TOHP_DLT_EVT[A--D][1--2], 0x0802--0x0809, Delta/Event Registers (COR/COW-RO) ................ 209 Table 63. TOHP_RX_TX_STATE[A--D], 0x080A--0x080D, Receive/Transmit State Registers (RO) ............... 211 Table 64. TOHP_MSK[A--D][1--2], 0x080E--0x0815, Mask Bit Registers (R/W).............................................. 212 Table 65. TOHP_TRG[A--D], 0x0816--0x0819, Trigger Register 0 AE 1 (R/W) ................................................. 213 Table 66. TOHP_CNTD[A--D][1--2], 0x081A--0x0821, Continuous N-Times Detect (CNTD) Values (R/W) .... 214 Table 67. TOHP_RCTL[A--D][1--2], 0x0822--0x0829, Receive Control [1--2] (R/W) ...................................... 215 Table 68. TOHP_RCTL[A--D][3], 0x082A--0x082D, Receive Control 3 (R/W) .................................................. 218 Table 69. TOHP_TCTL[A--D][1--2], 0x082E--0x0835, Transmit Control [1--2] (R/W) ..................................... 219 Table 70. TOHP_TCTL[A--D][3], 0x0836--0x0839, Transmit Control 3 (R/W) ................................................... 223 Table 71. TOHP_SD_SETR[A--D][1--2], 0x083A--0x0841, Signal Degrade BER Algorithm Set Control Registers [1--2] (R/W)....................................................................................................................................... 224 Table 72. TOHP_SD_SETR[A--D][3], 0x0842--0x0845, Signal Degrade BER Algorithm Set Control Register [3] (R/W) .............................................................................................................................................. 224 Table 73. TOHP_SD_CLEARR[A--D][1--2], 0x0846--0x084D, Signal Degrade BER Algorithm Clear Control Registers [1--2] (R/W) .......................................................................................................................... 225 Table 74. TOHP_SD_CLEARR[A--D][3], 0x084E--0x0851, Signal Degrade BER Algorithm Clear Control Register [3] (R/W) .............................................................................................................................................. 225 Table 75. TOHP_SF_SETR[A--D][1--2], 0x0852--0x0859, Signal Fail Set BER Algorithm Control Registers [1--2] (R/W)....................................................................................................................................... 226 Table 76. TOHP_SF_SETR[A--D][3], 0x085A--0x085D, Signal Fail BER Algorithm Set Control Register [3] (R/W) .............................................................................................................................................. 226 Table 77. TOHP_SF_CLEARR[A--D][1--2], 0x085E--0x0865, Signal Fail BER Algorithm Clear Control Registers [1--2] (R/W) .......................................................................................................................... 227 Table 78. TOHP_SF_CLEARR[A--D][3], 0x0866--0x0869, Signal Fail BER Algorithm Clear Control Register [3] (R/W).................................................................................................................................. 227 Table 79. Ns, L, M, and B Values to Set the BER Indicator ................................................................................. 229 Table 80. Ns, L, M, and B Values to Clear the BER Indicator .............................................................................. 230 Table 81. TOHP_B1ECNTR[A--D], 0x086A--0x086D, B1 Error Count (RO) ..................................................... 231 Table 82. TOHP_B2ECNTR[A--D][1--2], 0x086E--0x0875, B2 Error Count (RO) ............................................ 231 Table 83. TOHP_M1ECNTR[A--D][1--2], 0x0876--0x087D, M1 Error Count (RO) ........................................... 231 Table 84. TOHP_TOH_INSR[A--D][1--2], 0x087E--0x0885, Transmit OH Insert Value (R/W)......................... 232 Table 85. TOHP_RMONR[A--D][1--3], 0x0886--0x0891, Receive Monitor Value (RO).................................... 232 Table 86. TOHP_RJ0DMONR[A--D][1--32], 0x0892--0x0911, Receive J0/Z0 Monitor Value Registers (RO) . 233 Table 87. TOHP_TJ0DINSR[A--D][1--32], 0x0912--0x09A9, Transmit J0/Z0 Insert Value Registers (R/W) .... 234 Table 88. TOHP_TZ0DINSR[A--D][1--6], 0x09AA--0x09C1, Transmit Z0 Insert Value Registers (R/W) ......... 235 Table 89. Z0 Byte Ordering STS-48 Mode for Z0-1--Z0-47 ................................................................................ 236 Table 90. Z0 Byte Ordering STS-12 Mode for Z0-1--Z0-11 ................................................................................ 236 Table 91. Z0 Byte Ordering STS-3 Mode for Z0-1--Z0-2 .................................................................................... 236 Table 92. TOHP_SCRATCHR, 0x09C2, TOHP-48 Scratch Register (R/W) ........................................................ 236 Table 93. TOHP-48 Register Map ........................................................................................................................ 237 Table 94. E1/F1 Path Status Definition ................................................................................................................ 249 Agere Systems Inc. 9 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 95. RDI-P Codes and Interpretation ........................................................................................................... 256 Table 96. PP_IDR, PP Identification Register (RO, Fixed Value) ........................................................................ 258 Table 97. PP_CORWR, PP Clear on Read/Write Register (R/W, Control) .......................................................... 258 Table 98. PP_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) ................................ 259 Table 99. PP_ES_ALMBNBSR, Elastic Store Overrun/Underrun Alarm Status Binning Bytestream A--D (RO) 263 Table 100. PP_TSES_ALMBSR[A--D], Time Slots 1--12 Elastic Store Overrun/Underrun Alarm Bytestream A--D (RO, COR/COW)................................................................................................................... 263 Table 101. PP_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A--D (RO) ............................... 263 Table 102. PP_TSSF_ALMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Bytestream A--D (RO, COR/COW)...................................................................................................................................... 263 Table 103. PP_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A--D (RO)........ 264 Table 104. PP_TSRDI_ALMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Bytestream A--D (RO, COR/COW)................................................................................................................... 264 Table 105. PP_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A--D (RO) ...... 264 Table 106. PP_TSPLM_ALMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Bytestream A--D (RO, COR/COW)................................................................................................................... 264 Table 107. PP_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A--D (RO) .... 265 Table 108. PP_TSUNEQR_ALMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Bytestream A--D (RO, COR/COW)................................................................................................................... 265 Table 109. PP_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A--D (RO) .......... 265 Table 110. PP_TSAIS_ALMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Bytestream A--D (RO, COR/COW)...................................................................................................................................... 265 Table 111. PP_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A--D (RO)...................... 266 Table 112. PP_TSLOP_ALMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Bytestream A--D (RO, COR/COW) ............................................................................................................................................... 266 Table 113. PP_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW)................................................................................................................... 267 Table 114. PP_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning Bytestream A--D (RO, COR/COW)................................................................................................................... 267 Table 115. PP_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning Bytestream A--D (RO, COR/COW)...................................................................................................................................... 267 Table 116. PP_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW)...................................................................................................................................... 267 Table 117. PP_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A--D (RO)........ 268 Table 118. PP_TSPDI_ALMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Bytestream A--D (RO, COR/COW)...................................................................................................................................... 268 Table 119. PP_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 268 Table 120. PP_TSRDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) ......................................................................................................... 268 Table 121. PP_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 269 Table 122. PP_TSPLM_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Bytestream A--D (RO, COR/COW) .............................................................................. 269 Table 123. PP_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 269 Table 124. PP_TSUNEQR_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Bytestream A--D (RO, COR/COW)............................................................................................... 269 Table 125. PP_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 270 10 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 126. PP_TSAIS_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Bytestream A--D (RO, COR/COW) ......................................................................................................... 270 Table 127. PP_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 270 Table 128. PP_TSLOP_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Bytestream A--D (RO, COR/COW)................................................................................................................... 270 Table 129. PP_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW) ................................. 271 Table 130. PP_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 271 Table 131. PP_TSPDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) ................................................................................ 271 Table 132. STS-1 #12 Channel Path Alarm Binning Status Registers (RO) ........................................................ 272 Table 133. STS-1 Channel Path SS New Validated Bits Alarm Status Binning Bytestream A--D (RO) ............. 273 Table 134. STS-1 Channel Path Time Slots 1--12 SS New Validated Bits Alarm Status Bytestream A--D (RO, COR/COW)...................................................................................................................................... 273 Table 135. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Bytestream A--D (RO) ..................... 273 Table 136. STS-1 Channel Path Time Slots 1--12 SS Bits Mismatch Alarm Status Bytestream A--D (RO, COR/COW) ............................................................................................................................................... 273 Table 137. PP_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) ............................. 274 Table 138. PP_ES_ALMBNMBSR, Elastic Store Overrun/Underrun Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 277 Table 139. PP_TSES_ALMMBSR[A--D], Time Slots 1--12 Elastic Store Overrun/Underrun Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 277 Table 140. PP_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A--D (R/W) ............... 277 Table 141. PP_TSSF_ALMMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Masks Bytestream A--D (R/W) . 277 Table 142. PP_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W) ........................................................................................................................................................ 278 Table 143. PP_TSRDI_ALMMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 278 Table 144. PP_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks Bytestream A--D (R/W) ........................................................................................................................................................ 278 Table 145. PP_TSPLM_ALMMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Masks Bytestream A--D (R/W) ........................................................................................................................................................ 278 Table 146. PP_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 279 Table 147. PP_TSUNEQR_ALMMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Masks Bytestream A--D (R/W) ........................................................................................................................................................ 279 Table 148. PP_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 279 Table 149. PP_TSAIS_ALMMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 279 Table 150. PP_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A--D (R/W)...... 280 Table 151. PP_TSLOP_ALMMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Masks Bytestream A--D (R/W) ........................................................................................................................................................ 280 Table 152. PP_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A--D (R/W)..................................................................................................................................... 281 Table 153. PP_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 281 Table 154. PP_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks Bytestream A--D(R/W)...................................................................................................................................... 281 Agere Systems Inc. 11 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 155. PP_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks Bytestream A--D (R/W)..................................................................................................................................... 281 Table 156. PP_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 282 Table 157. PP_TSPDI_ALMMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 282 Table 158. PP_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 283 Table 159. PP_TSRDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 283 Table 160. PP_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 283 Table 161. PP_TSPLM_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 283 Table 162. PP_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 284 Table 163. PP_TSUNEQR_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 284 Table 164. PP_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 285 Table 165. PP_TSAIS_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Masks Bytestream A--D (R/W) ................................................................................................................ 285 Table 166. PP_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 285 Table 167. PP_TSLOP_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Masks Bytestream A--D (R/W) ......................................................................................................................... 285 Table 168. PP_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W) .......................................... 286 Table 169. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Masks Bytestream A--D (R/W) ........ 286 Table 170. STS-1 Channel Path Time Slots 1--12 SS Bits Mismatch Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 286 Table 171. PP_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 287 Table 172. PP_TSPDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 287 Table 173. STS-1 #12 Channel Path Alarm Binning Mask Status Registers (R/W)............................................. 288 Table 174. STS-1 Channel Path SS New Validated Bits Alarm Binning Masks Bytestream A--D (R/W)............ 289 Table 175. STS-1 Channel Path Time Slots 1--12 SS New Validated Bits Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 289 Table 176. PP_PTRBFR[1--32], Path Trace Buffer Registers 1--32 (R/W) ....................................................... 290 Table 177. PP_PTRACCTLR1, Path Trace Access Control Register 1 (R/W)..................................................... 290 Table 178. PP_PTRACCTLR2, Path Trace Access Control Register 2 (R/W)..................................................... 290 Table 179. PP_PTRACCTLR3, Path Trace Access Control Register 3 (R/W)..................................................... 290 Table 180. PP_PTRACBGR, Path Trace Access Begin (WO)............................................................................. 290 Table 181. PP_STS12PTRCTLR[1--6], STS-12 Channel Path Trace Control Registers 1--6 (R/W)................. 291 Table 182. STS-12 F2, H4, Z3, Z4, and Z5 Status (RO) ...................................................................................... 292 Table 183. Path F2, H4, Z3, Z4, and Z5 Provisioning Bytestream A--D (R/W, Control) ..................................... 293 Table 184. STS-12 SS Bits Status (RO)............................................................................................................... 294 Table 185. PP_TSRDI_ALMPSBSR[A--D], Time Slots 1--12 RDI Alarm Persistency Bytestream A--D (RO) . 296 Table 186. PP_TSPLM_ALMPSBSR[A--D], Time Slots 1--12 PLM Alarm Persistency Bytestream A--D (RO) 296 Table 187. PP_TSPUNEQ_ALMPSBSR[A--D], Time Slots 1--12 Path Unequipped Alarm Persistency Bytestream A--D (RO) ...................................................................................................................................... 296 12 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 188. PP_TSAIS_ALMPSBSR[A--D], Time Slots 1--12 AIS Alarm Persistency Bytestream A--D (RO) .. 297 Table 189. PP_TSLOP_ALMPSBSR[A--D], Time Slots 1--12 LOP Alarm Persistency Bytestream A--D (RO) 297 Table 190. PP_TSPDI_ALMPSBSR[A--D], Time Slots 1--12 PDI Alarm Persistency Bytestream A--D (RO) .. 297 Table 191. PP_TSRDI_STBSR[A--D], Time Slots 1--12 RDI State Bytestream A--D (RO).............................. 298 Table 192. PP_TSPLM_STBSR[A--D], Time Slots 1--12 PLM State Bytestream A--D (RO) ........................... 298 Table 193. PP_TSPUNEQ_STBSR[A--D], Time Slots 1--12 Path Unequipped State Bytestream A--D (RO) . 298 Table 194. PP_TSAIS_STBSR[A--D], Time Slots 1--12 AIS State Bytestream A--D (RO) .............................. 299 Table 195. PP_TSLOP_STBSR[A--D], Time Slots 1--12 LOP State Bytestream A--D (RO)............................ 299 Table 196. PP_TSPDI_STBSR[A--D], Time Slots 1--12 PDI State Bytestream A--D (RO) .............................. 299 Table 197. PP_SFWSZ_SELR[1--2], Signal Fail Window Size Select Registers 1--2 (R/W, Control) ............... 300 Table 198. PP_SFDR[0--7], Signal Fail Detect Threshold Registers 0--7 (R/W, Control) ................................. 301 Table 199. PP_SFCLRR[0--7], Signal Fail Clear Threshold Registers 0--7 (R/W, Control)............................... 302 Table 200. PP_SFWSZR[0--3], Signal Fail Window Size 0/1/2/3 Registers (R/W, Control) ............................... 302 Table 201. PP_ECNCTM_TSBSR[A--D], Expected Concatenation Map Time Slots 1--12 in Bytestream A--D (R/W)..................................................................................................................................... 303 Table 202. PP_CNCTCPREN_TSBSR[A--D], Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D (R/W)..................................................................................................................................... 303 Table 203. PP_RCNCTM_TSBSR[A--D], Received Concatenation Map Time Slots 1--12 in Bytestream A--D (RO) ...................................................................................................................................... 303 Table 204. PP_SWAIS_ISRTR, Software AIS Insert (R/W) ................................................................................. 304 Table 205. PP_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W) ............................................ 304 Table 206. PP_TSSS_ISRTBSR[A--D], Time Slot 1--Time Slot 12 SS Bits Insert Bytestream A--D (R/W) ..... 304 Table 207. PP_TSE1F1_ISRTBSR[A--D], Time Slot 1--Time Slot 12 E1/F1 Insert Bytestream A--D (R/W).... 304 Table 208. PP_E2_ISRTCTLR[A--D], E2 Insert Control Bytestream A--D (R/W) .............................................. 305 Table 209. PP_TS_INCDECBNR[A--D], Time Slots 1--12 Increment/Decrement Binning Select Bytestream A--D (R/W)..................................................................................................................................... 305 Table 210. PP_AISONTIM_ISRTR[A--D], STS-12 Pointer Processor Control (R/W) ......................................... 305 Table 211. PP_TSPDIVLD_CTLBSR[A--D], Time Slot 1--Time Slot 12 PDI Validate Control Bytestream A--D (R/W) ........................................................................................................................................................ 306 Table 212. PP_EXPC2_PVSNR[1--24], Expected C2 Byte Provisioning (R/W) ................................................. 306 Table 213. PP_TSCBB_ERRBSR[A--D], Time Slot 1--Time Slot 12 Count Block/Bit Errors Bytestream A--D 306 Table 214. PP_TS1_6_SSBSRA, PP_TS7_12_SSBSRA, Time Slots 1--12 SS Bits Insertion Value Bytestream A (R/W) ........................................................................................................................................... 307 Table 215. PP_TS1_6_SSBSRB, PP_TS7_12_SSBSRB, Time Slots 1--12 SS Bits Insertion Value Bytestream B (R/W) ........................................................................................................................................... 307 Table 216. PP_TS1_6_SSBSRC, PP_TS7_12_SSBSRC, Time Slots 1--12 SS Bits Insertion Value Bytestream C (R/W)........................................................................................................................................... 308 Table 217. PP_TS1_6_SSBSRD, PP_TS7_12_SSBSRD, Time Slots 1--12 SS Bits Insertion Value Bytestream D (R/W)........................................................................................................................................... 308 Table 218. SS Bits Provisioning (R/W)................................................................................................................. 309 Table 219. SS Bits Validation/Compare Period (R/W) ......................................................................................... 309 Table 220. Elastic Store Decrement and Increment (R/W) .................................................................................. 309 Table 221. Elastic Store Overflow Region (R/W) ................................................................................................. 309 Table 222. PP_TS_E1F1ISRTR[1--24], Time Slots 1--48 E1/F1 Insert ............................................................. 309 Table 223. PP_E2_ISRTBSR[A--D], E2 Byte Insert Bytestream A--D............................................................... 309 Table 224. PP_TSMNTR[1--48], Time Slots 1--48 Maintenance (R/W)............................................................. 310 Table 225. PP_PI_LSECINCR[A--D], Pointer Interpreter Last Second Increments Bytestream A--D (RO) ...... 310 Table 226. PP_PI_LSECDECR[A--D], Pointer Interpreter Last Second Decrements Bytestream A--D (RO) ... 310 Table 227. PP_PG_LSECINCR[A--D], Pointer Generator Last Second Increments Bytestream A--D (RO) ..... 310 Table 228. PP_PG_LSECDECR[A--D], Pointer Generator Last Second Decrements Bytestream A--D (RO) .. 310 Table 229. PP_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO) ....................................... 311 Agere Systems Inc. 13 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 230. PP_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A--D (RO)................... 312 Table 231. PP_TS1BRDI_DPMBSR[A--D], Path Overhead Time Slots 1--12 One-Bit RDI Defect PM Bytestream A--D (RO).......................................................................................................................................................... 312 Table 232. PP_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A--D (RO) ............... 312 Table 233. PP_TSERDI_PDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Payload Defect PM Bytestream A--D (RO).......................................................................................................................................................... 312 Table 234. PP_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A--D (RO) ........ 313 Table 235. PP_TSERDI_CDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Connectivity Defect PM Bytestream A--D (RO) ...................................................................................................................................... 313 Table 236. PP_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A--D (RO).................. 313 Table 237. PP_TSERDI_SDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Server Defect PM Bytestream A--D (RO).......................................................................................................................................................... 313 Table 238. PP_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A--D (RO) .............. 314 Table 239. PP_TSUNEQR_PMBSR[A--D], Path Overhead Time Slots 1--12 Unequipped Received PM Bytestream A--D (RO) ...................................................................................................................................... 314 Table 240. PP_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A--D (RO)...................... 314 Table 241. PP_TSAIS_PMBSR[A--D], Path Overhead Time Slots 1--12 Alarm Indicator Signal PM Bytestream A--D (RO) ...................................................................................................................................... 314 Table 242. PP_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A--D (RO)................................ 315 Table 243. PP_TSLOP_PMBSR[A--D], Path Overhead Time Slots 1--12 Loss of Pointer PM Bytestream A--D (RO) ...................................................................................................................................... 315 Table 244. PP_LSECCVP_CPMR[1--48], Last Second CV-P Count Time Slot 1--Time Slot 48 PM (RO) ....... 315 Table 245. PP_LSECREIP_CPMR[1--48], Last Second REI-P Count Time Slot 1--Time Slot 48 PM (RO) ..... 315 Table 246. PP_TSRDIPR[1--48], Time Slots 1--48 Path RDI Status (RO) ........................................................ 316 Table 247. PP_TSC2R[1--24], Time Slots 1--48 Path C2 Status (RO).............................................................. 316 Table 248. PP_TSPDIR[1--24], Time Slots 1--48 Path PDI Status (RO) ........................................................... 316 Table 249. Pointer Processor Register Map......................................................................................................... 317 Table 250. STS-48 Time-Slot Assignments ......................................................................................................... 346 Table 251. STS-12 Time-Slot Assignments ................................................................................................. 347 Table 252. STS-3 Time-Slot Assignments ........................................................................................................... 347 Table 253. Sequence Register Map TS[0--23]_PM_[A--D]................................................................................ 348 Table 254. Logical 16-Channel Configuration Concatenation Register Map CH[0--15]_NC............................... 348 Table 255. C2 Path Signal Label.......................................................................................................................... 354 Table 256. G1 RDI-P Codes................................................................................................................................. 355 Table 257. STS-48 Time-Slot Internal Ordering ................................................................................................... 356 Table 258. (PT_TX_VERSION), Version Control (RO) ........................................................................................ 357 Table 259. (PT_TX_CH_INT), Tx Channel Composite Interrupt (RO) ................................................................. 357 Table 260. (PT_TX_TS_[A--D]_INT), Tx Time-Slot Composite Interrupt (RO) ................................................... 357 Table 261. (PT_TX_CH_INTMASK), Tx Channel Composite Interrupt Mask (R/W)............................................ 357 Table 262. (PT_TX_TS[A--D]_INTMASK), Tx Time-Slot Composite Interrupt Mask (R/W)................................ 357 Table 263. (PT_TX_MODE), Mode (R/W)............................................................................................................ 358 Table 264. (PT_TX_BANKAorB), Tx_BANKAorB (R/W) ...................................................................................... 359 Table 265. (PT_TX_SCRATCH), SCRATCH (R/W)............................................................................................. 359 Table 266. (PT_TX_SOFTRST), Tx Channel FIFO Reset (R/W)......................................................................... 359 Table 267. (PT_TX_CH_DELTA [0--15]), Tx Channel Delta/Event (COR/W)..................................................... 360 Table 268. (PT_Tx_TS_[A--D]_Delta), Tx Delta/Event Register (COR/W) ......................................................... 360 Table 269. (PT_Tx_CH_Status_[0--15]), Transmit Status Register (RO) ........................................................... 360 Table 270. (PT_TX_TS_[A--D]0_Status), Transmit Status Register (RO) .......................................................... 361 Table 271. (PT_TX_TS_[A--D]1_Status), Transmit Status Register (RO) .......................................................... 361 Table 272. (PT_TX_TS_[A--D]2_Status), Transmit Status Register (RO) .......................................................... 361 Table 273. (PT_Tx_CH_Mask_[0--15]), Tx Channel Mask Register (R/W) ........................................................ 362 14 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 274. (PT_Tx_TS_[A--D]_Mask), Tx Mask Register (COR/W) ................................................................... 362 Table 275. (PT_Tx_Mask_A_[1--6]), Transmit Provisioning Register (R/W)....................................................... 363 Table 276. (PT_Tx_Mask_B_[1--6]), Transmit Provisioning Register (R/W)....................................................... 364 Table 277. (PT_Tx_Mask_C_[1--6]), Transmit Provisioning Register (R/W) ...................................................... 365 Table 278. (PT_Tx_Mask_D_[1--6]), Transmit Provisioning Register (R/W) ...................................................... 366 Table 279. (PT_Tx_RW4_[0--15]), Transmit Provisioning Register 4 (R/W)....................................................... 367 Table 280. (PT_Tx_RW1_[0--47]), Transmit Provisioning Register, Per Time Slot (R/W) .................................. 367 Table 281. (PT_Tx_RW2_[0--15]), Transmit Provisioning Register, Per Channel (R/W).................................... 367 Table 282. (PT_Tx_RW3_[0--15]), Transmit Provisioning Register 3 (R/W)....................................................... 367 Table 283. (PT_Tx_alarm_[A--D]_[1]]), TX Alarm Mapper Register 1 (R/W) ...................................................... 368 Table 284. (PT_Tx_alarm_[A--D]_[2]]), TX Alarm Mapper Register 2 (R/W) ...................................................... 368 Table 285. (PT_Tx_alarm_[A--D]_[3]]), TX Alarm Mapper Register 3 (R/W) ...................................................... 369 Table 286. (PT_Tx_alarm_[A--D]_[4]]), TX Alarm Mapper Register 4 (R/W) ...................................................... 369 Table 287. (PT_Tx_alarm_[A--D]_[5]]), TX Alarm Mapper Register 5 (R/W) ...................................................... 370 Table 288. (PT_Tx_alarm_[A--D]_[6]]), TX Alarm Mapper Register 6 (R/W) ...................................................... 370 Table 289. (PT_Tx_RW5_[0--15]), Transmit Provisioning Register 5 (R/W)....................................................... 371 Table 290. (PT_Tx_TIMP_[A--D]), TX TIMP Alarm Register, Per Time Slot (R/W) ............................................ 371 Table 291. (PT_Tx_DS3E3_[A--B]), Transmit Provisioning Register (R/W) ....................................................... 372 Table 292. (PT_Tx_STS1_[A--D]), Transmit Provisioning Register (R/W).......................................................... 372 Table 293. (PT_Tx_Cnfg_Alow), Transmit STS Configuration, Time Slots 0--5 (R/W) ....................................... 373 Table 294. (PT_Tx_Cnfg_Ahigh), Transmit STS Configuration, Time Slots 6--11 (R/W) ................................... 373 Table 295. (PT_Tx_Cnfg_Blow), Transmit STS Configuration, Time Slots 0--5 (R/W) ....................................... 374 Table 296. (PT_Tx_Cnfg_Bhigh), Transmit STS Configuration, Time Slots 6--11 (R/W) ................................... 374 Table 297. (PT_Tx_Cnfg_Clow), Transmit STS Configuration, Time Slots 0--5 (R/W)....................................... 375 Table 298. (PT_Tx_Cnfg_Chigh), Transmit STS Configuration, Time Slots 6--11 (R/W) ................................... 375 Table 299. (PT_Tx_Cnfg_Dlow), Transmit STS Configuration, Time Slots 0--5 (R/W)....................................... 376 Table 300. (PT_Tx_Cnfg_Dhigh), Transmit STS Configuration, Time Slots 6--11 (R/W) ................................... 376 Table 301. (PT_Tx_Stuffbyte_cnfg]), Tx Stuff Byte Configuration Register (R/W)............................................... 377 Table 302. (PT_TX_SEQMAP_A_AB[0--11]), Sequence Map, Bank A, Slices A and B, Per Time Slot (R/W) .. 378 Table 303. (PT_TX_SEQMAP_B_AB[0--11]), Sequence Map, Bank B, Slices A and B, Per Time Slot (R/W) .. 379 Table 304. (PT_TX_SEQMAP_A_CD[0--11]), Sequence Map, Bank A, Slices C and D, Per Time Slot (R/W).. 380 Table 305. (PT_TX_SEQMAP_B_CD[0--11]), Sequence Map, Bank B, Slices C and D, Per Time Slot (R/W).. 381 Table 306. (PT_Tx_J1Byte_start_0_[0--31]), Transmit J1 Byte Message Channel 0 (R/W)............................... 382 Table 307. (PT_Tx_J1Byte_start_1_[0--31]), Transmit J1 Byte Message Channel 1 (R/W)............................... 382 Table 308. (PT_Tx_J1Byte_start_2_[0--31]), Transmit J1 Byte Message Channel 2 (R/W)............................... 382 Table 309. (PT_Tx_J1Byte_start_3_[0--31]), Transmit J1 Byte Message Channel 3 (R/W)............................... 382 Table 310. (PT_Tx_J1Byte_start_4_[0--31]), Transmit J1 Byte Message Channel 4 (R/W)............................... 382 Table 311. (PT_Tx_J1Byte_start_5_[0--31]), Transmit J1 Byte Message Channel 5 (R/W)............................... 383 Table 312. (PT_Tx_J1Byte_start_6_[0--31]), Transmit J1 Byte Message Channel 6 (R/W)............................... 383 Table 313. (PT_Tx_J1Byte_start_7_[0--31]), Transmit J1 Byte Message Channel 7 (R/W)............................... 383 Table 314. (PT_Tx_J1Byte_start_8_[0--31]), Transmit J1 Byte Message Channel 8 (R/W)............................... 383 Table 315. (PT_Tx_J1Byte_start_9_[0--31]), Transmit J1 Byte Message Channel 9 (R/W)............................... 383 Table 316. (PT_Tx_J1Byte_start_10_[0--31]), Transmit J1 Byte Message Channel 10 (R/W)........................... 383 Table 317. (PT_Tx_J1Byte_start_11_[0--31]), Transmit J1 Byte Message Channel 11 (R/W)........................... 384 Table 318. (PT_Tx_J1Byte_start_12_[0--31]), Transmit J1 Byte Message Channel 12 (R/W)........................... 384 Table 319. (PT_Tx_J1Byte_start_13_[0--31]), Transmit J1 Byte Message Channel 13 (R/W)........................... 384 Table 320. (PT_Tx_J1Byte_start_14_[0--31]), Transmit J1 Byte Message Channel 14 (R/W)........................... 384 Table 321. (PT_Tx_J1Byte_start_15_[0--31]), Transmit J1 Byte Message Channel 15 (R/W)........................... 384 Table 322. PT Register Map................................................................................................................................. 385 Table 323. Path Overhead Extraction Compare Values....................................................................................... 393 Table 324. Set/Clear Threshold and Window Settings......................................................................................... 403 Agere Systems Inc. 15 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 325. Default Signal Fail Window Size Settings........................................................................................... 408 Table 326. STS Path Signal Label Assignments.................................................................................................. 410 Table 327. Payload Label Conditions................................................................................................................... 411 Table 328. RDI-P Codes and Interpretation ......................................................................................................... 412 Table 329. RXT_IDR, RXT Identification Register (RO, Fixed Value).................................................................. 415 Table 330. PP_CORWR, PP Clear on Read/Write Register (R/W, Control) ........................................................ 415 Table 331. RXT_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) ............................ 416 Table 332. RXT_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A--D (RO) ............................. 419 Table 333. RXT_TSSF_ALMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Bytestream A--D (RO, COR/COW) ............................................................................................................................................... 419 Table 334. RXT_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A--D (RO) ..... 419 Table 335. RXT_TSRDI_ALMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Bytestream A--D (RO, COR/COW)................................................................................................................... 419 Table 336. RXT_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A--D (RO).... 420 Table 337. RXT_TSPLM_ALMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Bytestream A--D (RO, COR/COW)................................................................................................................... 420 Table 338. RXT_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A--D (RO) .. 420 Table 339. RXT_TSUNEQR_ALMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Bytestream A--D (RO, COR/COW) ............................................................................................................................................... 420 Table 340. RXT_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A--D (RO)........ 421 Table 341. PP_TSAIS_ALMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Bytestream A--D (RO, COR/COW)...................................................................................................................................... 421 Table 342. RXT_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A--D (RO) ................... 421 Table 343. RXT_TSLOP_ALMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Bytestream A--D (RO, COR/COW) ............................................................................................................................................... 421 Table 344. RXT_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW)................................................................................................................... 422 Table 345. RXT_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning Bytestream A--D (RO, COR/COW)................................................................................................................... 422 Table 346. RXT_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning Bytestream A--D (RO, COR/COW)................................................................................................................... 422 Table 347. RXT_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW)................................................................................................................... 422 Table 348. RXT_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A--D (RO) ..... 423 Table 349. RXT_TSPDI_ALMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Bytestream A--D (RO, COR/COW)...................................................................................................................................... 423 Table 350. RXT_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 423 Table 351. RXT_TSRDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) ................................................................................ 423 Table 352. RXT_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 424 Table 353. RXT_TSPLM_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Bytestream A--D (RO, COR/COW)............................................................................................... 424 Table 354. RXT_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 424 Table 355. RXT_TSUNEQR_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Bytestream A--D (RO, COR/COW)............................................................................................... 424 Table 356. RXT_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 425 16 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 357. RXT_TSAIS_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Bytestream A--D (RO, COR/COW) ......................................................................................................... 425 Table 358. RXT_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 425 Table 359. RXT_TSLOP_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Bytestream A--D (RO, COR/COW)................................................................................................................... 425 Table 360. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW) ............................... 426 Table 361. RXT_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) ...................................................................................................................................... 426 Table 362. RXT_TSPDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) ................................................................................ 426 Table 363. RXT_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) .......................... 427 Table 364. RXT_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A--D (R/W) ............. 429 Table 365. RXT_TSSF_ALMMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Masks Bytestream A--D (R/W)429 Table 366. RXT_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 430 Table 367. RXT_TSRDI_ALMMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Masks Bytestream A--D (R/W) ........................................................................................................................................................ 430 Table 368. RXT_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 430 Table 369. RXT_TSPLM_ALMMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Masks Bytestream A--D (R/W) ........................................................................................................................................................ 430 Table 370. RXT_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 431 Table 371. RXT_TSUNEQR_ALMMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 431 Table 372. RXT_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 431 Table 373. RXT_TSAIS_ALMMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 431 Table 374. RXT_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A--D (R/W) ... 432 Table 375. RXT_TSLOP_ALMMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 432 Table 376. RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A--D (R/W)..................................................................................................................................... 432 Table 377. RXT_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 432 Table 378. RXT_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 433 Table 379. RXT_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks Bytestream A--D (R/W)..................................................................................................................................... 433 Table 380. RXT_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W)..................................................................................................................................... 433 Table 381. RXT_TSPDI_ALMMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Masks Bytestream A--D (R/W)..................................................................................................................................... 433 Table 382. RXT_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) ............................................................................................................ 434 Table 383. RXT_TSRDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 434 Table 384. RXT_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Masks Bytestream A--D (R/W) ................................................................................................. 434 Agere Systems Inc. 17 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 385. RXT_TSPLM_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 434 Table 386. RXT_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Masks Bytestream A--D (R/W) ............................................................................................................ 435 Table 387. RXT_TSUNEQR_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 435 Table 388. RXT_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 435 Table 389. RXT_TSAIS_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Masks Bytestream A--D (R/W)........................................................................................... 435 Table 390. RXT_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 436 Table 391. RXT_TSLOP_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 436 Table 392. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W)........................................ 436 Table 393. RXT_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) ......................................................................................................................... 437 Table 394. RXT_TSPDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Masks Bytestream A--D (R/W)...................................................................................................... 437 Table 395. RXT_PTRBFR[1--32], Path Trace Buffer Registers 1--32 (R/W) ..................................................... 438 Table 396. RXT_PTRACCTLR1, Path Trace Access Control Register 1 (R/W) .................................................. 438 Table 397. RXT_PTRACCTLR2, Path Trace Access Control Register 2 (R/W) .................................................. 438 Table 398. RXT_PTRACCTLR3, Path Trace Access Control Register 3 (R/W) .................................................. 438 Table 399. RXT_PTRACBGR, Path Trace Access Begin (WO) .......................................................................... 438 Table 400. RXT_STS12PTRCTLR[1--6], STS-12 Channel Path Trace Control Registers 1--6 (R/W) .............. 439 Table 401. RXT_TSRDI_ALMPSBSR[A--D], Time Slots 1--12 RDI Alarm Persistency Bytestream A--D (RO)440 Table 402. RXT_TSPLM_ALMPSBSR[A--D], Time Slots 1--12 PLM Alarm Persistency Bytestream A--D (RO).......................................................................................................................................................... 440 Table 403. RXT_TSPUNEQ_ALMPSBSR[A--D], Time Slots 1--12 Path Unequipped Alarm Persistency Bytestream A--D (RO) ...................................................................................................................................... 440 Table 404. RXT_TSAIS_ALMPSBSR[A--D], Time Slots 1--12 AIS Alarm Persistency Bytestream A--D (RO) 441 Table 405. RXT_TSLOP_ALMPSBSR[A--D], Time Slots 1--12 LOP Alarm Persistency Bytestream A--D (RO).......................................................................................................................................................... 441 Table 406. RXT_TSPDI_ALMPSBSR[A--D], Time Slots 1--12 PDI Alarm Persistency Bytestream A--D (RO) 441 Table 407. RXT_TSRDI_STBSR[A--D], Time Slots 1--12 RDI State Bytestream A--D (RO) ........................... 442 Table 408. RXT_TSPLM_STBSR[A--D], Time Slots 1--12 PLM State Bytestream A--D (RO)......................... 442 Table 409. RXT_TSPUNEQ_STBSR[A--D], Time Slots 1--12 Path Unequipped State Bytestream A--D (RO) 442 Table 410. RXT_TSAIS_STBSR[A--D], Time Slots 1--12 AIS State Bytestream A--D (RO) ............................ 443 Table 411. RXT_TSLOP_STBSR[A--D], Time Slots 1--12 LOP State Bytestream A--D (RO) ......................... 443 Table 412. RXT_TSPDI_STBSR[A--D], Time Slots 1--12 PDI State Bytestream A--D (RO)............................ 443 Table 413. RXT_SFWSZ_SELR[1--2], Signal Fail Window Size Select Registers 1--2 (R/W, Control) ............ 444 Table 414. RXT_SFDR[0--7], Signal Fail Detect Threshold Registers 0--7 (R/W, Control) ............................... 445 Table 415. RXT_SFCLRR[0--7], Signal Fail Clear Threshold Registers 0--7 (R/W, Control) ............................ 446 Table 416. RXT_SFWSZR[0--3], Signal Fail Window Size 0--3 Registers (R/W, Control) ................................ 447 Table 417. RXT_ECNCTM_TSBSR[A--D], Expected Concatenation Map Time Slots 1--12 in Bytestream A--D (R/W, Control) .......................................................................................................................................... 448 Table 418. RXT_CNCTCPREN_TSBSR[A--D], Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D (R/W, Control) .......................................................................................................................................... 448 Table 419. RXT_RCNCTM_TSBSR[A--D], Received Concatenation Map Time Slots 1--12 in Bytestream A--D (RO).......................................................................................................................................................... 448 Table 420. RXT_SWAIS_ISRTR, Software AIS Insert (R/W, Control) ................................................................. 449 18 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 421. RXT_AISONUNEQ_PR[A--D], Time Slot 1--Time Slot 12 AIS Insert on UNEQ-P Bytestream A--D (R/W, Control) .......................................................................................................................................... 449 Table 422. RXT_AISONPLM_PR[A--D], Time Slot 1--Time Slot 12 AIS Insert on PLM-P Bytestream A--D (R/W, Control) .................................................................................................................................................... 449 Table 423. RXT_AISONTIM_PR[A--D], Time Slot 1--Time Slot 12 Software AIS Insert on TIM-P Bytestream A--D (R/W, Control) .......................................................................................................................................... 449 Table 424. RXT_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W, Control) ............................ 450 Table 425. RXT_TS_INCDECBNR[A--D], Time Slots 1--12 Increment/Decrement Binning Select Bytestream A--D (R/W, Control) ....................................................................................................................... 450 Table 426. RXT_TSPDIVLD_CTLBSR[A--D], Time Slot 1--Time Slot 12 PDI Validate Control Bytestream A--D (R/W, Control) .......................................................................................................................................... 451 Table 427. RXT_EXPC2_PVSNR[1--24], Expected C2 Byte Provisioning (R/W, Control) ................................. 452 Table 428. RXT_TSCBB_ERRBSR[A--D], Time Slot 1--Time Slot 12 Count Block/Bit Errors Bytestream A--D ............................................................................................................................................... 452 Table 429. RXT_TSMNTR[1--48], Time Slots 1--48 Maintenance (R/W, Control)............................................. 453 Table 430. RXT_PI_LSECINCR[A--D], Pointer Interpreter Last Second Increments Bytestream A--D (RO) .... 453 Table 431. RXT_PI_LSECDECR[A--D], Pointer Interpreter Last Second Decrements Bytestream A--D (RO) . 453 Table 432. RXT_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO) .................................... 454 Table 433. RXT_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A--D (RO) ................ 455 Table 434. RXT_TS1BRDI_DPMBSR[A--D], Path Overhead Time Slots 1--12 One-Bit RDI Defect PM Bytestream A--D (RO) ................................................................................................................................ 455 Table 435. RXT_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A--D (RO) ............. 455 Table 436. RXT_TSERDI_PDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Payload Defect PM Bytestream A--D (RO) ...................................................................................................................................... 455 Table 437. RXT_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A--D (RO) ...... 456 Table 438. RXT_TSERDI_CDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Connectivity Defect PM Bytestream A--D (RO) ...................................................................................................................................... 456 Table 439. RXT_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A--D (RO) ............... 456 Table 440. RXT_TSERDI_SDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Server Defect PM Bytestream A--D (RO) ...................................................................................................................................... 456 Table 441. RXT_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A--D (RO) ............ 457 Table 442. RXT_TSUNEQR_PMBSR[A--D], Path Overhead Time Slots 1--12 Unequipped Received PM Bytestream A--D (RO) ...................................................................................................................................... 457 Table 443. RXT_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A--D (RO) ................... 457 Table 444. RXT_TSAIS_PMBSR[A--D], Path Overhead Time Slots 1--12 Alarm Indicator Signal PM Bytestream A--D (RO) ...................................................................................................................................... 457 Table 445. RXT_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A--D (RO) ............................. 458 Table 446. RXT_TSLOP_PMBSR[A--D], Path Overhead Time Slots 1--12 Loss of Pointer PM Bytestream A--D (RO) ...................................................................................................................................... 458 Table 447. RXT_LSECCVP_CPMR[1--48], Last Second CV-P Count Time Slot 1--Time Slot 48 PM (RO) ..... 458 Table 448. RXT_LSECREIP_CPMR[1--48], Last Second REI-P Count Time Slot 1--Time Slot 48 PM (RO) ... 458 Table 449. RXT_TSRDIPR[1--48], Time Slots 1--48 Path RDI Status (RO)...................................................... 459 Table 450. RXT_TSC2R[1--24], Time Slots 1--48 Path C2 Status (RO) ........................................................... 459 Table 451. RXT_TSPDIR[1--24], Time Slots 1--48 Path PDI Status (RO)......................................................... 459 Table 452. RXT Register Map .............................................................................................................................. 460 Table 453. Overhead Bits Defined in a 44.736 Mbits/s Multiframe Structure....................................................... 490 Table 454. RAI Code Words................................................................................................................................. 492 Table 455. POI Values ......................................................................................................................................... 495 Table 456. G1 Byte Definition............................................................................................................................... 496 Table 457. Trailer Length ..................................................................................................................................... 496 Table 458. PLCP Nibble Stuff Sequence ............................................................................................................. 496 Agere Systems Inc. 19 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 459. C-Bit Insert.......................................................................................................................................... 497 Table 460. Overhead Allocation at 34,368 kbits/s ................................................................................................ 502 Table 461. MA Byte Description ........................................................................................................................... 504 Table 462. G.751 E3 Frame Format..................................................................................................................... 505 Table 463. E3-PLCP Mapping of ATM Cells ........................................................................................................ 505 Table 464. Path Overhead Identifier Codes (POI)................................................................................................ 506 Table 465. PLCP G1 byte..................................................................................................................................... 507 Table 466. C1 Values and Transmit Insert Sequence.......................................................................................... 508 Table 467. Receive Mode Control Signals ........................................................................................................... 509 Table 468. Transmit Mode Control Signals .......................................................................................................... 509 Table 469. G.751 E3 Frame Transmit Overhead Operation ................................................................................ 510 Table 470. G.751 E3 Frame Receive Overhead Operation ................................................................................. 510 Table 471. G.751 E3-PLCP Transmit Overhead Operation ................................................................................. 512 Table 472. G.751 E3-PLCP Receive Overhead Operation .................................................................................. 513 Table 473. G.832 E3 Transmit Frame Overhead Operation ................................................................................ 514 Table 474. G.832 E3 Receive Frame Overhead Operation ................................................................................. 515 Table 475. PRBS Receive (Monitor) Pattern Control Signals .............................................................................. 517 Table 476. PRBS Transmit Pattern Control Signals............................................................................................. 517 Table 477. DS3E3_VERR, Version Control (RO)................................................................................................. 518 Table 478. DS3_SCRATCHR, Scratch Register (R/W)........................................................................................ 518 Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event Registers (R/W) ................................................................................................................................................. 518 Table 480. DS3FRMD_A, DS3 Out-of-Frame Delta (COR/COW)........................................................................ 521 Table 481. DS3LOFD_A, DS3 Loss-of-Frame Delta (COR/COW)....................................................................... 521 Table 482. DS3SEFD_A, DS3 Severely Errored Frame (SEF) Delta (COR/COW) ............................................. 522 Table 483. DS3AISD_A, DS3 AIS Detection Delta (COR/COW) ......................................................................... 522 Table 484. DS3IDLED_A, DS3 Idle Detection Delta (COR/COW) ....................................................................... 522 Table 485. DS3CBD_A, DS3 C-Bit Detect Delta (COR/COW)............................................................................. 522 Table 486. DS3RAID_A, DS3 X-Bit Detect Delta (COR/COW)............................................................................ 522 Table 487. DS3FEACALMD_A, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW) ..................... 523 Table 488. DS3FEACCTLD_A, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW) ................ 523 Table 489. DS3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW)............................................. 523 Table 490. DS3_PLCPRAID_A, PLCP RAI (G1[3]) Monitoring Delta (COR/COW) ............................................. 523 Table 491. DS3_RXPRBS_SYNCD_A, PRBS Detector Sync Delta (COR/COW)............................................... 523 Table 492. DS3FRMD_B, DS3 Out-of-Frame Delta (COR/COW)........................................................................ 524 Table 493. DS3LOFD_B, DS3 Loss-of-Frame Delta (COR/COW)....................................................................... 524 Table 494. DS3SEFD_B, DS3 Severely Errored Frame (SEF) Delta (COR/COW) ............................................. 524 Table 495. DS3AISD_B, DS3 AIS Detection Delta (COR/COW) ......................................................................... 524 Table 496. DS3IDLED_B, DS3 Idle Detection Delta (COR/COW) ....................................................................... 524 Table 497. DS3CBD_B, DS3 C-Bit Detect Delta (COR/COW)............................................................................. 525 Table 498. DS3RAID_B, DS3 X-Bit Detect Delta (COR/COW)............................................................................ 525 Table 499. DS3FEACALMD_B, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW) ..................... 525 Table 500. DS3FEACCTLD_B, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW) ................ 525 Table 501. DS3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW)............................................. 525 Table 502. DS3_PLCPRAID_B, PLCP RAI (G1[3]) Monitoring Delta (COR/COW) ............................................. 526 Table 503. DS3_RXPRBS_SYNCD_B, PRBS Detector Sync Delta (COR/COW)............................................... 526 Table 504. DS3_TXFIFOERRE, FIFO Overflow Indicator Event (COR/COW) .................................................... 526 Table 505. DS3_TXEOPERRER, EOP Marker Error Event (COR/COW)............................................................ 526 Table 506. DS3FRMM_A, DS3 Out-of-Frame Mask (R/W).................................................................................. 527 Table 507. DS3LOFM_A, DS3 Loss-of-Frame Mask (R/W)................................................................................. 527 Table 508. DS3SEFM_A, DS3 Severely Errored Frame (SEF) Mask (R/W) ....................................................... 527 20 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 509. DS3AISM_A, DS3 AIS Detection Mask (R/W) ................................................................................... 527 Table 510. DS3IDLEM_A, DS3 Idle Detection Mask (R/W) ................................................................................. 527 Table 511. DS3CBM_A, DS3 C-Bit Detect Mask (R/W)....................................................................................... 528 Table 512. DS3RAIM_A, DS3 X-Bit Detect Mask (R/W) ...................................................................................... 528 Table 513. DS3FEACALMM_A, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W) ............................ 528 Table 514. DS3FEACCTLM_A, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W) .......................... 528 Table 515. DS3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W) ....................................................... 528 Table 516. DS3_PLCPRAIM_A, PLCP RAI (G1[3]) Monitoring Mask (R/W) ....................................................... 529 Table 517. DS3_RXPRBS_SYNCM_A, PRBS Detector Sync Mask (R/W) ......................................................... 529 Table 518. DS3_DS3FRMM_B, DS3 Out-of-Frame Mask (R/W)......................................................................... 529 Table 519. DS3LOFM_B, DS3 Loss-of-Frame Mask (R/W)................................................................................. 529 Table 520. DS3SEFM_B, DS3 Severely Errored Frame (SEF) Mask (R/W) ....................................................... 529 Table 521. DS3AISM_B, DS3 AIS Detection Mask (R/W) ................................................................................... 530 Table 522. DS3IDLEM_B, DS3 Idle Detection Mask (R/W) ................................................................................. 530 Table 523. DS3CBM_B, DS3 C-Bit Detect Mask (R/W)....................................................................................... 530 Table 524. DS3RAIM_B, DS3 X-Bit Detect Mask (R/W) ...................................................................................... 530 Table 525. DS3FEACALMM_B, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W) ............................ 530 Table 526. DS3FEACCTLM_B, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W) .......................... 531 Table 527. DS3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W) ....................................................... 531 Table 528. DS3_PLCPRAIM_B, PLCP RAI (G1[3]) Monitoring Mask (R/W) ....................................................... 531 Table 529. DS3_RXPRBS_SYNCM_B, PRBS Detector Sync Mask (R/W) ......................................................... 531 Table 530. DS3_TXFIFOERRM, FIFO Overflow Indicator Mask (R/W) ............................................................... 532 Table 531. DS3_TXEOPERRM, EOP Marker Error Mask (R/W) ......................................................................... 532 Table 532. DS3FRM_A, DS3 Out-of-Frame State (RO)....................................................................................... 533 Table 533. DS3LOF_A, DS3 Loss-of-Frame State (RO)...................................................................................... 533 Table 534. DS3SEF_A, DS3 Severely Errored Frame (SEF) (RO)...................................................................... 533 Table 535. DS3AIS_A, DS3 AIS Detection (RO).................................................................................................. 533 Table 536. DS3IDLE_A, DS3 Idle Detection (RO) ............................................................................................... 534 Table 537. DS3CB_A, DS3 C-Bit Detect (RO) ..................................................................................................... 534 Table 538. DS3RAI_A, DS3 X-Bit Detect (RO) .................................................................................................... 534 Table 539. DS3FEACALM_A, DS3 Far-End Alarm and Control (FEAC) (RO) .................................................... 534 Table 540. DS3FEACCTL_A, DS3 Far-End Alarm and Control (FEAC) (RO) ..................................................... 535 Table 541. DS3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO) ..................................................................... 535 Table 542. DS3_PLCPRAI_A, PLCP RAI (G1[3]) Monitoring (RO)...................................................................... 535 Table 543. DS3_RXPRBS_SYNC_A, PRBS Detector Sync State (RO).............................................................. 535 Table 544. DS3FEACCODE_A[1--6], DS3 Far-End Alarm and Control (FEAC) (RO) ........................................ 536 Table 545. DS3_RXPRBSERRCNT_A, PRBS Error Counter (RO) ..................................................................... 536 Table 546. DS3FRM_B, DS3 Out-of-Frame State (RO)....................................................................................... 536 Table 547. DS3LOF_B, DS3 Loss-of-Frame State (RO)...................................................................................... 536 Table 548. DS3SEF_B, DS3 Severely Errored Frame (SEF) (RO)...................................................................... 537 Table 549. DS3AIS_B, DS3 AIS Detection (RO).................................................................................................. 537 Table 550. DS3IDLE_B, DS3 Idle Detection (RO) ............................................................................................... 537 Table 551. DS3CB_B, DS3 C-Bit Detect (RO) ..................................................................................................... 537 Table 552. DS3RAI_B, DS3 X-Bit Detect (RO) .................................................................................................... 538 Table 553. DS3FEACALM_B, DS3 Far-End Alarm and Control (FEAC) (RO) .................................................... 538 Table 554. DS3FEACCTL_B, DS3 Far-End Alarm and Control (FEAC) (RO) ..................................................... 538 Table 555. DS3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO) ..................................................................... 538 Table 556. DS3_PLCPRAI_B, PLCP RAI (G1[3]) Monitoring (RO)...................................................................... 539 Table 557. DS3_RXPRBS_SYNC_B, PRBS Detector Sync State (RO).............................................................. 539 Table 558. DS3FEACCODE_B[1--6], DS3 Far-End Alarm and Control (FEAC) (RO)........................................ 539 Table 559. DS3_RXPRBSERRCNT_B, PRBS Error Counter (RO) ..................................................................... 539 Agere Systems Inc. 21 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 560. DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W)................................................. 540 Table 561. DS3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W)................................................. 540 Table 562. DS3_RXPRBS_A, Receive PRBS (R/W) ........................................................................................... 541 Table 563. DS3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W)................................................. 541 Table 564. DS3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W)................................................. 542 Table 565. DS3_RXPRBS_B, Receive PRBS (R/W) ........................................................................................... 542 Table 566. DS3_RXDS3FBIT_A[1--12], DS3 F-Bit and M-Bit Error Count (RO) ................................................ 543 Table 567. DS3_RXDS3_CVP_P_A[1--12], DS3 P-Bit CVP-P Error Counter (CVP-P) (RO) ............................. 543 Table 568. DS3_RXDS3_CVCP_P_A[1--12], DS3 CP-Bit Error Counter (CVCP-P) (RO) ................................. 543 Table 569. DS3_RXDS3FEBE_A[1--12], DS3 FEBE Error Counter (CVCP-PFE) (RO)..................................... 544 Table 570. DS3_RXPLCPB1ECNT_A[1--12], PLCP B1 Error Count (RO)......................................................... 544 Table 571. DS3_PLCPFEBECNT_A[1--12], PLCP FEBE (G1[7:4]) Error Count (RO) ....................................... 544 Table 572. DS3_RXDS3FBIT_B[1--12], DS3 F-Bit and M-Bit Error Count (RO) ................................................ 545 Table 573. DS3_RDS3_CVP_P_B[1--12], DS3 P-Bit CVP-P Error Counter (CVP-P) ........................................ 545 Table 574. DS3_RXDS3_CVCP_P_B[1--12], DS3 CP-Bit Error Counter (CVCP-P) (RO) ................................. 545 Table 575. DS3_RXDS3FEBE_B[1--12], DS3 FEBE Error Counter (CVCP-PFE) (RO)..................................... 546 Table 576. DS3_RXPLCPB1ECNT_B[1--12], PLCP B1 Error Count (RO)......................................................... 546 Table 577. DS3_PLCPFEBECNT_B[1--12], PLCP FEBE (G1[7:4]) Error Count (RO) ....................................... 546 Table 578. DS3_TDS3PLCPCTL1_CHD[1--16], Transmit PLCP (R/W) ............................................................. 547 Table 579. DS3_TDS3CTL_CHD[1--16], Transmit DS3 (R/W)........................................................................... 548 Table 580. DS3_TXPRBSCTL_[1--2], Transmit PRBS Control (R/W) ................................................................ 549 Table 581. DS3_TXFEBEDINS, Transmit Blank Request Counter Reset (R/W) ................................................. 549 Table 582. DS3_TXFIFO, Transmit FIFO Min/Max Thresholds (R/W)................................................................. 549 Table 583. DS3E3_VERR, Version Control (RO)................................................................................................. 550 Table 584. E3_SCRATCHR, Scratch Register (R/W) .......................................................................................... 550 Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event Registers (R/W) ................................................................................................................................................. 550 Table 586. E3FRMD_A, E3 Out-of-Frame Delta (COR/COW)............................................................................. 553 Table 587. E3LOFD_A, E3 Loss-of-Frame Delta (COR/COW)............................................................................ 553 Table 588. E3_TR_MISMATCHD_A, E3 Delta (COR/COW) ............................................................................... 553 Table 589. E3AISD_A, E3 AIS Detection Delta (COR/COW) .............................................................................. 553 Table 590. E3_D_A, E3 Delta (COR/COW) ......................................................................................................... 554 Table 591. E3_MA_SSMD_A, E3 Delta (COR/COW) .......................................................................................... 554 Table 592. E3_D_A, E3 Delta (COR/COW) ......................................................................................................... 554 Table 593. E3_MA_PTD_A, E3 Delta (COR/COW) ............................................................................................. 554 Table 594. E3_PLCP_LOFD_A, E3 Delta (COR/COW)....................................................................................... 555 Table 595. E3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW) ............................................... 555 Table 596. E3_PLCPASD_A, PLCP (G1[3]) Monitoring Delta (COR/COW) ........................................................ 555 Table 597. E3FRMD_B, E3 Out-of-Frame Delta (COR/COW)............................................................................. 556 Table 598. E3LOFD_B, E3 Loss-of-Frame Delta (COR/COW)............................................................................ 556 Table 599. E3_TR_MISMATCHD_B, E3 Delta (COR/COW) ............................................................................... 556 Table 600. E3AISD_B, E3 AIS Detection Delta (COR/COW) .............................................................................. 556 Table 601. E3_D_B, E3 Delta (COR/COW) ......................................................................................................... 557 Table 602. E3_MA_SSMD_B, E3 Delta (COR/COW) .......................................................................................... 557 Table 603. E3_D_B, E3 Delta (COR/COW) ......................................................................................................... 557 Table 604. E3_MA_PTD_B, E3 Delta (COR/COW) ............................................................................................. 557 Table 605. E3_PLCP_LOFD_B, E3 Delta (COR/COW)....................................................................................... 558 Table 606. E3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW) ............................................... 558 Table 607. E3_PLCP_G1_ASD_B, PLCP (G1[3]) Monitoring Delta (COR/COW) ............................................... 558 Table 608. E3FRMM_A, E3 Out-of-Frame Mask (R/W) ....................................................................................... 559 Table 609. E3LOFM_A, E3 Loss-of-Frame Mask (R/W) ...................................................................................... 559 22 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 610. E3SEFM_A, E3 Severely Errored Frame (SEF) Mask (R/W)............................................................. 559 Table 611. E3AISM_A, E3 AIS Detection Mask (R/W)......................................................................................... 559 Table 612. E3_M_A, E3 Mask (R/W) ................................................................................................................... 560 Table 613. E3MAM_A, E3 MA-Bit Detect Mask (R/W)......................................................................................... 560 Table 614. E3_M_A, E3 Detect Mask (R/W) ........................................................................................................ 560 Table 615. E3_MA_PTM_A, E3 Mask (R/W) ....................................................................................................... 560 Table 616. E3_PLCP_LOFM_A, E3 Mask (R/W) ................................................................................................. 561 Table 617. E3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W).......................................................... 561 Table 618. DS3_PLCPASM_A, PLCP (G1[3]) Monitoring Mask (R/W)................................................................ 561 Table 619. E3FRMM_B, E3 Out-of-Frame Mask (R/W) ....................................................................................... 562 Table 620. E3LOFM_B, E3 Loss-of-Frame Mask (R/W) ...................................................................................... 562 Table 621. E3SEFM_B, E3 Severely Errored Frame (SEF) Mask (R/W)............................................................. 562 Table 622. E3AISM_B, E3 AIS Detection Mask (R/W)......................................................................................... 562 Table 623. E3_M_B, E3 Mask (R/W) ................................................................................................................... 563 Table 624. E3MAM_B, E3 MA-Bit Detect Mask (R/W)......................................................................................... 563 Table 625. E3_M_B, E3 Detect Mask (R/W) ........................................................................................................ 563 Table 626. E3_MA_PTM_B, E3 Mask (R/W) ....................................................................................................... 563 Table 627. E3_PLCP_LOFM_B, E3 Mask (R/W) ................................................................................................. 564 Table 628. E3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W).......................................................... 564 Table 629. E3_PLCPASM_B, PLCP (G1[3]) Monitoring Mask (R/W) .................................................................. 564 Table 630. E3FRM_A, E3 Out-of-Frame State (RO)............................................................................................ 565 Table 631. E3LOF_A, E3 Loss-of-Frame State (RO)........................................................................................... 565 Table 632. E3SEF_A, E3 Severely Errored Frame (SEF) (RO)........................................................................... 565 Table 633. E3AIS_A, E3 AIS Detection (RO)....................................................................................................... 565 Table 634. E3E3_A, E3 Detect (RO).................................................................................................................... 566 Table 635. E3_PLCP_LOF_A, E3 PLCP Loss-of-Frame Monitor (RO) ............................................................... 566 Table 636. E3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO)........................................................................ 566 Table 637. E3_PLCPAS_A, PLCP (G1[3]) Monitoring (RO) ................................................................................ 567 Table 638. E3SSMCODE_A[1--6], E3 (RO)........................................................................................................ 567 Table 639. E3FRM_B, E3 Out-of-Frame State (RO)............................................................................................ 568 Table 640. E3LOF_B, E3 Loss-of-Frame State (RO)........................................................................................... 568 Table 641. E3SEF_B, E3 Severely Errored Frame (SEF) (RO)........................................................................... 568 Table 642. E3AIS_B, E3 AIS Detection (RO)....................................................................................................... 568 Table 643. E3_B, E3 Detect (RO) ........................................................................................................................ 569 Table 644. E3_PLCP_LOF_B, E3 PLCP Loss-of-Frame Monitor (RO) ............................................................... 569 Table 645. E3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO)........................................................................ 569 Table 646. E3_PLCPAS_B, PLCP (G1[3]) Monitoring (RO) ................................................................................ 570 Table 647. E3SSMCODE_B[1--6], E3 (RO)........................................................................................................ 570 Table 648. E3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) ................................................... 571 Table 649. E3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W) ................................................... 571 Table 650. RDS3E3_A, Receive Mode Control (R/W) ......................................................................................... 571 Table 651. E3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W) ................................................... 572 Table 652. E3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W) ................................................... 572 Table 653. RDS3E3_B, Receive Mode Control.................................................................................................... 572 Table 654. E3PROV_1, E3 Provisioning Parameters (Per Block) (R/W) ............................................................. 573 Table 655. E3PROV_2, E3 PLCP Provisioning Parameters (Per Block) (R/W)................................................... 573 Table 656. E3PROV_3, E3 AIS Provisioning Parameters (Per Block) (R/W) ...................................................... 573 Table 657. E3PROV_4, E3 Provisioning Parameters (Per Block) (R/W) ............................................................. 574 Table 658. E3PROV_5, E3 Provisioning Parameters (Per Block) (R/W) ............................................................. 574 Table 659. E3_MA_MF_[A--B], E3 Provisioning Parameters.............................................................................. 574 Table 660. E3_TR_NMODE_[A--B][1--2], (R/W)................................................................................................ 575 Agere Systems Inc. 23 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 661. E3PLCP_MON[A--B][1--2], (RO)...................................................................................................... 575 Table 662. E3_MA_REI_ERRCNT_A[1--12], E3 MA REI Error Count (RO)....................................................... 576 Table 663. E3_B1_ERRCNT_A[1--12], E3 B1 Error Counter (RO) .................................................................... 576 Table 664. E3_RXPLCPB1ECNT_A[1--12], PLCP B1 Error Count (RO) ........................................................... 576 Table 665. E3_PLCPFEBECNT_A[1--12], PLCP FEBE (G1[7:4]) Error Count (RO).......................................... 576 Table 666. E3_MA_REI_ERRCNT_B[1--12], E3 MA REI Error Count (RO)....................................................... 577 Table 667. E3_B1_ERRCNT_B[1--12], E3 B1 Error Counter (RO) .................................................................... 577 Table 668. E3_RXPLCPB1ECNT_B[1--12], PLCP B1 Error Count (RO) ........................................................... 577 Table 669. E3_PLCPFEBECNT_B[1--12], PLCP FEBE (G1[7:4]) Error Count (RO).......................................... 577 Table 670. E3_TE3PLCPCTL1_CHD[1--16], Transmit PLCP (R/W) .................................................................. 578 Table 671. E3_TE3CTL_CHD[1--16], Transmit E3 (R/W)................................................................................... 579 Table 672. E3_TXFEBEDINS, Transmit PLCP FEBE Insert Data Value for All Channel (R/W) .......................... 580 Table 673. TXE3PLCP_P[1--3], Transmit G.751 E3 PLCP Z1--Z3, F1 Insert Control (R/W) ............................ 580 Table 674. TXTRACE[1--16]_B[1--8], Transmit E3 G.832 Trail Trace (TR) Insert Registers (128 Locations) (R/W)........................................................................................................................................ 580 Table 675. Receive E3 (G.832) Trail Trace Expected/Captured Value--Expected/Capture Format Same as Transmit Insert Format....................................................................................................................................... 581 Table 676. DS3 Register Map .............................................................................................................................. 582 Table 677. E3 Register Map................................................................................................................................. 595 Table 678. STS-1 Mapping of DS3 Information.................................................................................................... 609 Table 679. (RXSVERSION) Version Control (RO) ............................................................................................... 613 Table 680. RXS_CONTROL, Receive Sequencer Control Register (R/W).......................................................... 613 Table 681. RXS_TS[0--11][A--D], X Sequence Map Register (R/W) ................................................................. 614 Table 682. RYS_TS[0--11][A--D], Y Sequence Map Register (R/W) ................................................................. 614 Table 683. DS3 Support Registers....................................................................................................................... 615 Table 684. RXS PRBS Control Register for Monitor 1 (R/W)............................................................................... 616 Table 685. RXS PRBS Control Register for Monitor 2 (R/W)............................................................................... 616 Table 686. RXS PRBS Status Register for Monitor 1 (Mixed).............................................................................. 617 Table 687. RXS PRBS Status Register for Monitor 2 (Mixed).............................................................................. 617 Table 688. Sequencer Register Map 1 Field Definition ........................................................................................ 618 Table 689. Sequencer Register Map 2 Field Definition ........................................................................................ 622 Table 690. General Registers (RO)...................................................................................................................... 677 Table 691. CORWN Register (R/W)..................................................................................................................... 677 Table 692. TXMUX Mask Register (R/W)............................................................................................................. 677 Table 693. RXMUX Mask Register (R/W) ............................................................................................................ 677 Table 694. FIFO Control (FC) Bandwidth Register (R/W) .................................................................................... 678 Table 695. DE Scratch Register (R/W)................................................................................................................. 678 Table 696. Counter Interrupts (COR/COW) ......................................................................................................... 678 Table 697. GFP Message Interrupts (COR/COW) ............................................................................................... 678 Table 698. Composite Interrupt Register for GFP Interrupts at the Channel Level (COR/COW)......................... 679 Table 699. ATM Frame State Interrupts (COR/COW).......................................................................................... 680 Table 700. ATM Cool Interrupts (COR/COW) ...................................................................................................... 680 Table 701. CDA MAP0 Register (R/W) ................................................................................................................ 681 Table 702. CDA MAP Control Register (R/W)...................................................................................................... 681 Table 703. CDA MAP1 Register (R/W) ................................................................................................................ 681 Table 704. ATM Framer Idle Cell Match Mask (R/W)........................................................................................... 681 Table 705. ATM_LCD[0--15] (R/W)..................................................................................................................... 682 Table 706. ATM_LCDCLK (R/W) ......................................................................................................................... 682 Table 707. ATM_IN_LCD_MASK (R/W)............................................................................................................... 682 Table 708. ATM_OUT_LCD_MASK (R/W)........................................................................................................... 682 Table 709. ATM_IN_LCD (COR/COW) ................................................................................................................ 682 24 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface List of Tables (continued) Table Page Table 710. ATM_OUT_LCD (COR/COW) ............................................................................................................ 682 Table 711. ATM Framer Idle Cell (R/W) ............................................................................................................... 683 Table 712. ATM Unassigned Cell Match/Register (R/W) ..................................................................................... 683 Table 713. ATM Unassigned Cell (R/W) .............................................................................................................. 684 Table 714. ATM Frame State Channel [0--15] Registers (RO) ........................................................................... 684 Table 715. ATM Configuration Registers (R/W) ................................................................................................... 685 Table 716. Rx Channel [0--15] Payload Type and Control (R/W) ....................................................................... 686 Table 717. Rx Payload Type and Payload Control Summary Table .................................................................... 687 Table 718. GFP State Register (R/W, RO)........................................................................................................... 688 Table 719. Registers 0x6470--0x6473 A Message Mailbox Registers (RO)....................................................... 688 Table 720. A Message Mailbox Registers (RO) ................................................................................................... 688 Table 721. Registers 1168--1171 A Message Mailbox Registers (RO) .............................................................. 689 Table 722. Registers 1184--1187 B Message Mailbox Registers (RO) .............................................................. 689 Table 723. B Message Mailbox Registers (RO) ................................................................................................... 689 Table 724. B Message Mailbox Registers (RO) ................................................................................................... 689 Table 725. GFP Interrupt Masks R/W .................................................................................................................. 690 Table 726. Per-Channel Framer State ................................................................................................................. 690 Table 727. GFP Interrupts (COW)........................................................................................................................ 691 Table 728. GFP Receive Configuration Registers (R/W) ..................................................................................... 691 Table 729. PPP Detach Channel 0--15 PPP Protocol Check (R/W) ................................................................... 692 Table 730. PPP Detach Programmable PPP Protocol Register 0--11 (R/W)...................................................... 692 Table 731. PPP Detach Channel 0--15 PPP Header Search (R/W) ................................................................... 693 Table 732. ATM Null Cell Register in TX (R/W) ................................................................................................... 694 Table 733. ATM Header Error Register in Tx (R/W)............................................................................................. 695 Table 734. CRC Transmit Registers (R/W) .......................................................................................................... 695 Table 735. GFP Transmit Registers (R/W)........................................................................................................... 696 Table 736. GFP Transmit Registers (RO) ............................................................................................................ 697 Table 737. GFP Transmit Registers (R/W)........................................................................................................... 697 Table 738. HDLC-Tx Dry Character ..................................................................................................................... 698 Table 739. HDLC-Tx FIFO Threshold .................................................................................................................. 698 Table 740. Tx Payload Type and Control (R/W)................................................................................................... 698 Table 741. Tx Payload Type and Payload Control Summary Table..................................................................... 699 Table 742. ATM/HDLC/GFP Framer--Condition Counter 1 (PMRST Update) (RO) ........................................... 700 Table 743. ATM/HDLC/GFP Framer--Condition Counter 2 (PMRST Update) (RO ............................................ 700 Table 744. CRC Checker--Bad Packet Counter (PMRST Update) (RO) ............................................................ 701 Table 745. PPP Detach--Bad Header Counter (PMRST Update) (RO) .............................................................. 701 Table 746. Interrupts and Interrupt Masks for Packet Counters (R/W) ................................................................ 701 Table 747. Interrupts for Packet Counters (COR/COW) ...................................................................................... 702 Table 748. Transmit (Tx) Good Packet Counter (PMRST Update) (RO) ............................................................. 702 Table 749. DE Register Map ................................................................................................................................ 703 Table 750. Slices, Channels, and Channel IDs .................................................................................................... 717 Table 751. UTOPIA Traffic Types ........................................................................................................................ 719 Table 752. Interface Configurations Supported ................................................................................................... 720 Table 753. UTOPIA Address Modes .................................................................................................................... 727 Table 754. MARS2G5 P-ProLT/MARS2G5 P-Pro UTOPIA (Virtual) Address Pin Mappings............................... 728 Table 755. PHY Channel Address Allocation Related to Status Signal ............................................................... 730 Table 756. UTOPIA Tx Interface Pins that Have Different Meanings in Different Modes .................................... 742 Table 757. UTOPIA Rx Interface Pins that Have Different Meanings in Different Modes .................................... 743 Table 758. Channel B0/B1 Ganging Settings for ATM Cells ................................................................................ 744 Table 759. Transmit UTOPIA Interface Timing Specifications ............................................................................. 745 Table 760. Receive UTOPIA Interface Timing Specifications .............................................................................. 746 Agere Systems Inc. 25 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 List of Tables (continued) Table Page Table 761. UTOPIA Interface Clock Specifications .............................................................................................. 747 Table 762. (UTVER) Version Control (RO) .......................................................................................................... 748 Table 763. (XBARCFGRX) Cross-Bar Configuration Register for Rx (R/W)........................................................ 748 Table 764. (XBARCFGTX) Cross-Bar Configuration Register for Tx (R/W)......................................................... 748 Table 765. (INTSTATUS) Interrupts (RO) ............................................................................................................ 748 Table 766. (INTMASK) Interrupt Masks (R/W) .................................................................................................... 748 Table 767. (ARST) ARST Register (R/W) ............................................................................................................ 749 Table 768. (CORWN) Clear-On-Read or Clear-On-Write Select Register (R/W)................................................. 749 Table 769. UTOPIA Provisioning Field Description.............................................................................................. 750 Table 770. Rx/Tx UTOPIA Interface A--D Provisioning Registers ...................................................................... 752 Table 771. (PARERRA_PM) Interface A Error Count in PMRST Mode (RO) ...................................................... 753 Table 772. (PARERRA) Interface A Error Count (RO/COR) ................................................................................ 753 Table 773. (RXMODEA) Rx Interface A Provisioning Registers (R/W) ................................................................ 753 Table 774. (TXMODEA) Tx Interface A Provisioning Registers (R/W)................................................................. 757 Table 775. (TxWC[A--D]) Channel A--D Transmit Wait Register (R/W)............................................................. 758 Table 776. UTOPIA Channel [A--D](0--3) Provisioning Registers ..................................................................... 759 Table 777. (INTA0) Channel A0--Overflow/Underflow (COR/COW) ................................................................... 760 Table 778. (INTA0m) Channel A0--Overflow/Underflow Mask (R/W) ................................................................. 760 Table 779. (RxProvA0) Channel A0--Provisioning Registers (R/W) ................................................................... 761 Table 780. (TxProvA0) Channel A0--Provisioning Registers (R/W).................................................................... 761 Table 781. (RxThA0) Channel A0--Provisioning Registers (R/W)....................................................................... 762 Table 782. (TxThA0) Channel A0--Provisioning Registers (R/W) ....................................................................... 762 Table 783. (RxThMinA0) Channel A0--Provisioning Registers (R/W)................................................................. 763 Table 784. (TxThMaxA0) Channel A0--Provisioning Registers (R/W) ................................................................ 763 Table 785. UT Register Map ................................................................................................................................ 764 Table 786. JTAG ID Register Codings ................................................................................................................. 778 Table 787. ESD Threshold Voltage ...................................................................................................................... 779 Table 788. LVTTL 3.3 V Logic Interface Characteristics ...................................................................................... 781 Table 789. LVPECL 3.3 V Logic Interface Characteristics ................................................................................... 782 Table 790. Substrate Thickness ........................................................................................................................... 784 Table 791. Loopback Mode .................................................................................................................................. 793 Table 792. Connection Memory Map (WO).......................................................................................................... 795 26 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Description The MARS2G5 P-Pro SONET/SDH interface device provides a versatile solution for quad OC-3, quad OC-12, and for single OC-48 linear datacom/telecom applications. Constructed using COM2 CMOS modular process, this device incorporates integrated SONET/SDH framing, section/line/path termination, pointer processing, and data engine blocks. The device provides complete encapsulation and de-encapsulation for packet and ATM streams into and out of SONET/SDH payloads. Communication with the MARS2G5 P-Pro device is accomplished through a generic microprocessor interface. The device supports separate address and data buses. With the MARS2G5 P-Pro device, support for different types of applications for OC-3/OC-12/OC-48 data equipment is possible, enabling dramatic system cost reduction and the ease of development of extremely competitive solutions. This device integrates the SONET/SDH network termination functions with a generic cell/packet delineation circuit. The interface rates supported are STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1. The UTOPIA interface can process and hand off up to 16 channels transported within an STS-N payload. The concatenation levels supported by this device are STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, . . . , STS-45c, and STS48c. The data formats processed by this device are ATM cells or HDLC framed packets such as PPP or GFP framed packets. DIRECT CELL/PACKET OVER FIBER INTERFACE BLOCK SINGLE STM-16/STS-48 OR QUAD STM-4/STS-12 OR QUAD STM-1/STS-3 OVERHEAD PROCESSOR INSERT TXA PT (SPE MPR) TXB DS3 DE* TXC TXD PACKET/CELL FIFOs UTOPIA INTERFACE RXA TXCLK TRANSPORT OVERHEAD TERMINATION POINTER PROCESSOR SINGLE STM-16/STS-48 OR QUAD STM-4/STS-12 OR QUAD STM-1/STS-3 PT (PTR INTER) OVERHEAD PROCESSOR MONITOR DS3 RXS DE RXB RXC RXD CONTROL DIRECT CELL/PACKET OVER FIBER MISCELLANEOUS TXTOAC RXTOAC TOAC INTERFACE MPU INTERFACE GPIO 5-7393(F).dTDAT16 Note: PT = path terminator, RXS = receive sequencer, and DE = data engine. * In the transmit path, the data engine performs packet/cell processing (encapsulation, scrambling). In the receive path, the data engine performs packet/cell processing (delineation, descrambling, de-encapsulation). Figure 1. MARS2G5 P-Pro Block Diagram Agere Systems Inc. 27 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Description (continued) Generic Framing Procedure (GFP) GFP is an emerging new global standard for data encapsulation over SONET/SDH or G.709 (ITU-T G.gfp draft new standard). It is a generic mechanism for adapting variable length client signals onto an octet synchronous transport network. Client signals may be PDU oriented, such as IP/PPP or ethernet MAC (frame-mapped GFP), or block-code oriented, such as fiber channel or ESCON (transparent GFP). Frame-mapped GFP adaptation may operate at the physical or data-link layer of the client signal. Client PDU visibility is required. Transparent-mapped GFP operates on the coded 8B/10B character stream, rather than on the incoming client PDUs. Figure 2 illustrates the relationship between the higher-layer payloads, GFP, and SDH/OTN paths. GFP benefits include: Equips SONET/SDH with flexible/efficient data transport capabilities. More robust frame delineation than flag-based mechanisms such as HDLC. No payload dependent frame expansion (no HDLC type byte stuffing). Flexibility of extension headers. This allows for topology/application specific fields to be defined without affecting frame delineation functions. Ability to identify the encapsulated client protocol separately from the extension header. This allows frame forwarding based on extension header fields without requiring recognition of the encapsulated client protocol. Optional GFP 16-bit or 32-bit frame check sequence (FCS). This allows for fault location on a GFP frame basis without requiring recognition of the encapsulated client protocol. It also provides a data integrity mechanism for the encapsulation of protocols that may not have such a mechanism. ETHERNET PPP/HDLC OTHER PACKET ORIENTED BEARER SERVICES GFP - PAYLOAD DEPENDENT (CLIENT SPECIFIC ASPECTS) GFP--PAYLOAD INDEPENDENT (COMMON GFP ASPECTS) SDH PATH OTN OPU 2682(F)s Figure 2. GFP Relationship to Transport Payloads GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only) GFP block upgrade on transmit and receive to calculate the CRC-32 over only the payload information area. MARS2G5 P-Pro (version 2.0/2.1) calculated CRC-32 over everything except the PLI field. Two modes are supported for CRC-32 insertion/checking: 1. Null-extension headers: 4-byte header. Calculation starts after PLI field and 4 bytes of TYPE field. 2. Linear-extension headers: 8-byte header. Calculation starts after PLI field and 4 bytes of TYPE field and 4 bytes of EXT header field. PLI field value will be modified on transmit by +4 to include CRC-32 bytes. PLI field value will be modified on receive by -4 when CRC-32 is stripped. MARS2G5 P-Pro (version 2.2 and 2.3) does not touch PFI field value because it will corrupt tHEC. Agere Systems Inc. 28 Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Target Applications Supported MARS2G5 P-Pro (600-Pin LBGA and 792-Pin PBGA) This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications (see Figure 3 for device interface speed/rate information): Mixed ATM/POS-TDM. Access router and aggregation. Wireless, DSLAM, and gateway. LINE INTERFACE SINGLE (16 x 155 Mbits/s LVPECL) or QUAD (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) TXCLK SINGLE (16 x 155 Mbits/s LVPECL) or QUAD (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) DIRECT CELL/PACKET OVER FIBER OVERHEAD PROCESSOR INSERT INTERFACE BLOCK PT (SPE MPR) DS3 DE SEE TABLE 2 TRANSPORT OVERHEAD TERMINATION POINTER PROCESSOR PACKET/CELL FIFOs UTOPIA/DATA INTERFACE PT (PTR INTER) OVERHEAD PROCESSOR MONITOR DS3 RXS DE SEE TABLE 2 CONTROL DIRECT CELL/PACKET OVER FIBER MISCELLANEOUS TXTOAC RXTOAC TOAC INTERFACE MPU INTERFACE GPIO Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram Agere Systems Inc. 29 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Target Applications Supported (continued) MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications (see Figure 4 for device interface speed/rate information): Mixed ATM/POS-TDM. Access router and aggregation. Wireless, DSLAM, and gateway. LINE INTERFACE DIRECT CELL/PACKET OVER FIBER INTERFACE BLOCK DUAL (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) OVERHEAD PROCESSOR INSERT PT (SPE MPR) DS3 DE SEE TABLE 2 TXCLK TRANSPORT OVERHEAD TERMINATION POINTER PROCESSOR PACKET/CELL FIFOs UTOPIA/DATA INTERFACE DUAL (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) PT (PTR INTER) OVERHEAD PROCESSOR MONITOR DS3 RXS DE SEE TABLE 2 CONTROL DIRECT CELL/PACKET OVER FIBER MISCELLANEOUS TXTOAC RXTOAC TOAC INTERFACE MPU INTERFACE GPIO Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram 30 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Target Applications Supported (continued) MARS622 P-Pro (TDAT12622) (792-Pin PBGA) This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications (see Figure 5 for device interface speed/rate information): Mixed ATM/POS-TDM. Access router and aggregation. Wireless, DSLAM, and gateway. LINE INTERFACE DIRECT CELL/PACKET OVER FIBER INTERFACE BLOCK SINGLE (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) OVERHEAD PROCESSOR INSERT PT (SPE MPR) DS3 DE SEE TABLE 2 TXCLK TRANSPORT OVERHEAD TERMINATION POINTER PROCESSOR PACKET/CELL FIFOs UTOPIA/DATA INTERFACE SINGLE (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) PT (PTR INTER) OVERHEAD PROCESSOR MONITOR DS3 RXS DE SEE TABLE 2 CONTROL DIRECT CELL/PACKET OVER FIBER MISCELLANEOUS TXTOAC RXTOAC TOAC INTERFACE MPU INTERFACE GPIO Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram Agere Systems Inc. 31 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Overview This SONET line interface integrated circuit (IC) implements a four-port, sixteen-channel SONET/SDH interface for asynchronous transfer mode (ATM) and packet over SONET (POS) mappings at the STS-3 (STM-1), STS-12 (STM-4), or STS-48 (STM-12) rate. This device also supports direct cell/packet over fiber at up to 2.488 Gbits/s. The receive path terminates and processes section, line, and path overhead. It performs framing (A1, A2) and descrambling, detects alarm conditions, and monitors section, line, and path BIP-8s (B1, B2, and B3), accumulating error counts for each level for performance-monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated. The payload pointers (H1, H2) are interpreted and the synchronous payload envelope (SPE) is extracted. When used to implement an ATM UNI, the device performs cell delineation on the SPE. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled before being passed to a 32-cell FIFO buffer. The received cells are read from the FIFO using one of four generic 8-/16-/32-bit wide UTOPIA level 2 and level 3 compliant interface. Counts of received ATM cells, uncorrectable HCS errors, correctable HCS errors, and idle/unassigned ATM cells are accumulated independently for performance-monitoring purposes. When used to implement a POS UNI, the device descrambles the SPE before extracting HDLC frames. The control escape characters are removed. Descrambling can be performed after control escape byte destuffing (or before to control malicious HDLC expansion). The optional 16- or 32-bit error check sequence is verified for correctness. The packets are placed into a 256-byte FIFO buffer. The received packets are read from the FIFO using a generic 8-/16-/32-bit wide enhanced UTOPIA level 2 and level 3 compliant interface. Counts of errored/dropped packets are accumulated independently for performance-monitoring purposes. The device POS implementation also allows the optional detach of a per-channel provisionable PPP header. The transmit path inserts section, line, and path overhead. It inserts the framing pattern (A1, A2), performs scrambling, inserts AIS (optionally), and calculates and inserts section, line, and path BIP-8s (B1, B2, B3). Line and path remote failure indications (M1, G1) are inserted based on received BIP-8 errors. The payload pointers (H1, H2) are generated, and the SPE is inserted. When used to implement an ATM UNI, ATM cells are written into an internal four-cell (per channel) FIFO buffer using a generic 8-/16-/32-bit wide UTOPIA level 2 and level 3 compliant interface. Idle/unassigned cells are automatically inserted when the internal FIFO is empty. The device provides generation of the header check sequence and scrambles the ATM payload. Also supports cell-based UNI per I.432 (i.e., ATM over fiber). When used to implement a POS UNI, the device writes packets into an internal 256-byte (per channel) FIFO buffer using a generic 8/16/32-bit wide enhanced UTOPIA level 2 and level 3 compliant interface. HDLC framing performs the insertion of flags, control escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 (in regular or reversed mode) can be computed and added to the frame. Counts of transmitted packets and errored/dropped packets are accumulated for performance-monitoring purposes. The device is provisioned, controlled, and monitored using a generic 16-bit microprocessor interface. A standard five-signal IEEE(R) 1149.1 compliant JTAG test port is also provided for scan, boundary scan, and BIST purposes. A 4-bit general-purpose input/output (GPIO) interface is provided to control and/or monitor other onboard devices. 32 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Overview (continued) Figure 6 shows the external interfaces. PLL TEST TXFSYNC 2 4 TXCLKQ TXCLK 2 TXTOH 3 2 TOH SOH STS-48 TXQ STS-3/12 32 LOH POH ATM FRAME INSERTION HDLC UTOPIA INTERFACE SCRM SCRM 110 TXUTOPIA ECLREF 2 ATM CD HDLC STS-3/12 STS-48 RXD 32 FRMR DSCRM POINTER PROCESSOR DSCRM 110 RXUTOPIA RXCLK 2 SOH LOH POH CONTROL 12 RXREF RXTOH 43 MPU INTERFACE 4 GPIO 6 JTAG 5-7395(F).aTDAT162 Figure 6. MARS2G5 P-Pro External Interfaces Agere Systems Inc. 33 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Overview (continued) Clocking The following diagram shows a somewhat simplified picture of the major clock domains within the MARS2G5 P-Pro in the normal SONET/SDH operating mode. There are a total of 16 different clock domains as shown in the following table. Table 1. List of the Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode Clock Domain Name Core PLL MPU Receive Line Interface UTOPIA Interface Number of Clocks 1 2 1 4 (one each for A, B, C, and D) 8 (one each for A, B, C, and D); (one each for Rx and Tx on interface A; one each for Rx and Tx on interface B) 78 MHz CORE CLOCK PLL TXLINE TXOHP A PECL I/O B C D A B C D PATH FOR POF SUPPORT RXLINE RXOHP A PECL I/O B C D A B C D A PT/DS3 B C D POINTER PROCESSOR (PP) DATA ENGINE (DE) UT TX A B C UT I/O 5-8701(F)r.3TDAT16 CORE CLOCK DOMAIN MPU D A PT/DS3 RXS/DE B UT RX C D PATH FOR POF SUPPORT Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode 34 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Overview (continued) Clocking (continued) The following diagram shows a somewhat simplified picture of the clock domains within the MARS2G5 P-Pro when it is configured into the packet over fiber (POF) mode. In this mode, large subsections of the device are unused. 78 MHz CORE CLOCK PLL TXLINE MPU A PECL I/O B C D PATH FOR POF SUPPORT RXLINE A PT/DS3 PECL I/O B C D 5-8702(F) CORE CLOCK DOMAIN DATA ENGINE (DE) UT TX UT I/O UT RX PATH FOR POF SUPPORT RXS/DE Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode Agere Systems Inc. 35 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 MARS2G5 P-Pro (792-Pin PBGA) Low-Speed Devices Available The functionality of the MARS2G5 P-Pro (792-Pin PBGA) is available in lower-speed devices which are indicated below with the limitations noted. MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) MARS1G2 P-Pro is intended for use in quad OC-3 or dual OC-12 TDAT applications. It has the following limitations with respect to MARS2G5 P-Pro (TDAT162G52): Supports quad OC-3 or dual OC-12 rate line ports. The UTOPIA interface for the device can be operated as follows: -- 4 x 16-bit interfaces (A, B, C, and D) operating up to 26 MHz (2 x 16-bit interface (UT ports A and B only) operating up to 52 MHz (U2/U2+)). -- 4 x 8-bit interfaces (A, B, C, and D) operating up to 52 MHz (U2/U2+). -- 1 x 32-bit interface (UT ports A and B) operating up to 52 MHz (U3/U3+). -- 2 x 8-bit interfaces (A and B) operating up to 104 MHz (U3/U3+). MPHY is possible in all UTOPIA interfacing modes, (i.e., channels addressed from any interface in MPHY mode). For example, when connecting to an APP550 (Agere's network processor), the 2 x 8 (UT ports A and B) mode at 104 MHz can be used. MARS622 P-Pro (TDAT12622) (792-Pin PBGA) MARS622 P-Pro is intended for use in quad OC-3 or single OC-12 TDAT applications. The minimum channel size is one STS-1, and the device is limited to 12 channels. In addition to the 12-channel limitation, the MARS622 P-Pro (TDAT12622) also has the following limitations with respect to MARS2G5 P-Pro (TDAT162G52): Supports quad OC-3 rate line ports or a single OC-12 rate line port. The UTOPIA interface for this device can be operated as follows: -- 4 x 16-bit interfaces (UT ports A, B, C, and D) operating up to 26 MHz, (1 x 16-bit interface (UT port A only) operating up to 52 MHz (U2/U2+)). -- 4 x 8-bit interfaces (UT ports A, B, C, and D) operating up to 52 MHz (U2/U2+). -- 1 x 8-bit interfaces (UT port A only) operating up to 104 MHz (U3/U3+). MPHY is possible in all UTOPIA interfacing modes, (i.e., channels can be addressed from any interface in MPHY mode). For example, when connecting to APP550 (Agere's network processor), the 1 x 8 (UT port A only) mode at 104 MHz can be used. 36 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface MARS2G5 P-Pro Device Product Line Table Summaries Table 2 highlights which ports are supported for the line and UTOPIA interfaces for the MARS2G5 P-Pro. Letters in parentheses indicate which ports are available for that particular interface. Table 2. MARS2G5 P-Pro Device Product Line--Data Port Summary Device OC-3 Line Ports OC-12 OC-48 1 (A) UTOPIA MPHY/Data Interface UTOPIA Level Interface Max Frequency UTOPIA Ports MARS2G5 P 4* 4* (TADM042G52) (A, B, C, D) (A, B, C, D) (792-Pin PBGA and 600-Pin LBGA) MARS1G2 P (TADM021G2) (792-Pin PBGA) 4* (A, B, C, D) 2 (A,B) See the UTOPIA (UT) Block section and the MARS2G5 P-VC (TADMVC2G52) Device Advisory for Version 2.2 and Version 2.3 of the Device (AY03-015SONT) item UT27. Limitations in UTOPIA Clock Frequency. U2/U2+ U2/U2+ U2/U2+ U3/U3+ U3/U3+ 4 x 16-bit 2 x 16-bit 4 x 8-bit 1 x 32-bit 2 x 8-bit 4 x 16-bit 1 x 16-bit 4 x 8-bit 1 x 8-bit 26 MHz 52 MHz 52 MHz 52 MHz 104 MHz 26 MHz 52 MHz 52 MHz 104 MHz 4 (A, B, C, D) NA 4 (A, B, C, D) 2 (A, B) 4 (A, B, C, D) 2 (A, B) 2 (A, B) 4 (A, B, C, D) 1 (A) 4 (A, B, C, D) 1 (A) MARS622 P (TADM04622) (792-Pin PBGA) 4 (A, B, C, D) 1 (A) NA U2/U2+ U2/U2+ U2/U2+ U3/U3+ * No support for DS3 and E3 framing on ports C and D. Note: NA = not available. Agere Systems Inc. 37 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information 792-Pin PBGA Pin Assignments A pin assignment conversion between the 792-pin and 600-pin devices is shown in Table 3. Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 792-Pin Signal Name VDDD2 VDDD2 VDDD2 GNDD GNDD VDDD2 VDDD2 NC GNDD NC VDDD2 VDDD2 NC NC GNDD GNDD NC NC VDDD2 VDDD2 VDDD2 MPU_ADDR8 MPU_ADDR2 GNDD GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 600-Pin Signal Name VDDD VDDD GNDD GNDD VDDD2 VDDD2 GNDD GNDD MPU_DATA1 MPU_DATA6 MPU_DATA10 MPU_DATA15 GNDD MPU_ADDR8 MPU_ADDR12 GNDD VDDD VDDD NC GNDD NC NC GNDD NC NC NC GNDD GNDD GNDD VDDD2 VDDD2 GNDD GNDD VDDD VDDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 38 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 792-Pin Signal Name VDDD2 VDDD2 VDDD2 GNDD GNDD VDDD2 NC NC NC NC NC NC NC NC NC NC NC NC NC MPU_ADDR12 MPU_ADDR9 MPU_ADDR3 MPU_DATA13 MPU_DATA9 MPU_DATA8 MPU_DATA4 MPU_DSN VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 600-Pin Signal Name VDDD VDDD GNDD GNDD NC PLL_VDDD2 MPU_INTN MPU_CSN MPU_DATA0 MPU_DATA5 MPU_DATA9 MPU_DATA14 MPU_ADDR3 MPU_ADDR7 MPU_ADDR11 MPU_ADDR15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GNDD GNDD VDDD VDDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 39 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 792-Pin Signal Name VDDD2 VDDD2 VDDD2 GNDD GNDD VDDD2 NC NC NC GNDD NC NC NC NC NC NC NC NC NC MPU_ADDR13 NC MPU_ADDR4 MPU_DATA14 MPU_DATA12 MPU_DATA7 MPU_DATA3 MPU_RWN MPU_MPCLK RSTN PLL_VDDD2 GNDD GNDD GNDD GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 600-Pin Signal Name GNDD GNDD VDDD GNDD PLLREF PLL_GND RSTN MPU_MPCLK MPU_DSN MPU_DATA4 MPU_DATA8 MPU_DATA13 MPU_ADDR2 MPU_ADDR6 MPU_ADDR10 MPU_ADDR14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GNDD VDDD GNDD GNDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 40 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD VDDD2 NC NC NC VDDD2 NC NC NC NC NC NC NC NC NC MPU_ADDR14 MPU_ADDR10 MPU_ADDR5 MPU_DATA15 MPU_DATA10 MPU_DATA6 MPU_DATA2 MPU_ADSN MPU_DTN PMRST PLL_GND GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD 600-Pin Signal Name GNDD GNDD GNDD VDDD2 PLLFB NC PMRST MPU_MPMODE MPU_RWN MPU_DATA3 MPU_DATA7 MPU_DATA12 MPU_ADDR1 MPU_ADDR5 NC MPU_ADDR13 NC NC NC NC NC NC NC NC NC NC VDDD2 NC NC NC NC VDDD2 GNDD GNDD GNDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 41 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD VDDD VDDD NC NC NC NC NC NC NC NC NC NC NC NC MPU_ADDR15 MPU_ADDR11 MPU_ADDR6 MPU_ADDR0 MPU_DATA11 MPU_DATA5 MPU_DATA1 MPU_CSN MPU_INTN ICTN NC NC GNDD VDDD VDDD GNDD GNDD GNDD GNDD GNDD 600-Pin Signal Name VDDD2 IDDQMODE PLL_VDDD2 PLL_GNDD VDDD2 NC ICTN MPU_DTN MPU_ADSN MPU_DATA2 VDDD MPU_DATA11 MPU_ADDR0 MPU_ADDR4 MPU_ADDR9 VDDD2 NC NC NC VDDD2 NC NC NC NC VDDD NC NC NC NC NC VDDD2 NC NC NC VDDD2 -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 42 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 792-Pin Signal Name GNDD GNDD GNDD GNDD VDDD VDDD VDDD NC NC NC GNDD GNDD NC NC VDDD VDDD NC NC GNDD GNDD GNDD MPU_ADDR7 MPU_ADDR1 VDDD VDDD MPU_DATA0 MPU_MPMODE GNDD GNDD NC PLLREF PLLFB VDDD VDDD VDDD GNDD GNDD GNDD GNDD 600-Pin Signal Name VDDD2 TCLK GNDD TMS NC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXSPAA RXSPAB RXSPAC RXSPAD VDDD2 -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 43 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin G1 G2 G3 G4 G5 G6 G31 G32 G33 G34 G35 G36 G37 G38 G39 H1 H2 H3 H4 H5 H6 H31 H32 H33 H34 H35 H36 H37 H38 H39 J1 J2 J3 J4 J5 J6 J31 J32 J33 J34 792-Pin Signal Name VDDD2 VDDD2 GNDD GNDD VDDD VDDD -- -- -- VDDD PLL_GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 VDDD2 GNDD GNDD NC NC -- -- -- PLL_VDDD2 GNDD IDDQMODE GNDD VDDD2 VDDD2 VDDD2 VDDD2 GNDD RXSPAC RXSPAB NC -- -- -- GNDD 600-Pin Signal Name GNDD TDO TRSTN NC TDI -- TXSPAA TXADDRA0 TXADDRA1 TXCLKA GNDD -- -- -- -- GNDD TXCLKQP GNDD CLKDIV GNDD -- TXSZA TXERRA TXPPAA TXENBA GNDD -- -- -- -- TXD14N TXD14P TXD15N TXD15P TXCLKQN -- TXEOPA TXSOPA TXPRTYA TXDATAA15 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 44 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin J35 J36 J37 J38 J39 K1 K2 K3 K4 K5 K6 K31 K32 K33 K34 K35 K36 K37 K38 K39 L1 L2 L3 L4 L5 L6 L31 L32 L33 L34 L35 L36 L37 L38 L39 M1 M2 M3 M4 M5 792-Pin Signal Name NC GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 TXADDRA1 TXSPAA RXSPAD RXSPAA -- -- -- TMS TCLK TDI NC VDDD2 VDDD2 VDDD2 TXEOPA TXERRA TXCLKA TXADDRA0 GNDD -- -- -- GNDD TRSTN TDO CLKDIV VDDD2 VDDD2 VDDD2 TXDATAA15 TXSOPA TXPPAA TXSZA 600-Pin Signal Name TXDATAA14 -- -- -- -- TXD12N TXD12P TXD13N TXD13P VDDD -- TXDATAA13 TXDATAA12 TXDATAA11 TXDATAA10 TXDATAA9 -- -- -- -- TXD10N TXD10P TXD11N TXD11P VDDD -- VDDD TXDATAA8 TXDATAA7 TXDATAA6 TXDATAA5 -- -- -- -- TXD8N TXD8P TXD9N TXD9P VDDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 45 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin M6 M31 M32 M33 M34 M35 M36 M37 M38 M39 N1 N2 N3 N4 N5 N6 N31 N32 N33 N34 N35 N36 N37 N38 N39 P1 P2 P3 P4 P5 P6 P31 P32 P33 P34 P35 P36 P37 P38 P39 792-Pin Signal Name GNDD -- -- -- GNDD TXCLKQP TXCLKQN TXD15P TXD15N VDDD2 TXDATAA7 TXDATAA10 TXDATAA12 TXDATAA13 TXPRTYA TXENBA -- -- -- TXD14P TXD14N TXD13P TXD13N TXD12P TXD12N TXDATAA2 TXDATAA5 TXDATAA8 TXDATAA9 TXDATAA11 TXDATAA14 -- -- -- TXD11P TXD11N TXD10P TXD10N TXD8P TXD8N 600-Pin Signal Name -- TXDATAA4 TXDATAA3 TXDATAA2 TXDATAA1 TXDATAA0 -- -- -- -- GNDD TXD6N TXD6P TXD7N TXD7P -- RXDATAA15 RXDATAA14 RXDATAA13 RXDATAA12 GNDD -- -- -- -- TXD4N TXD4P TXD5N VDDD TXD5P -- RXDATAA11 RXDATAA10 RXDATAA9 RXDATAA8 RXDATAA7 -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 46 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin R1 R2 R3 R4 R5 R6 R31 R32 R33 R34 R35 R36 R37 R38 R39 T1 T2 T3 T4 T5 T6 T31 T32 T33 T34 T35 T36 T37 T38 T39 U1 U2 U3 U4 U5 U6 U31 U32 U33 U34 U35 792-Pin Signal Name GNDD TXDATAA0 TXDATAA3 TXDATAA4 TXDATAA6 VDDD -- -- -- VDDD TXD9P TXD9N TXD7P TXD7N GNDD GNDD RXDATAA11 RXDATAA13 RXDATAA15 TXDATAA1 VDDD -- -- -- VDDD TXD6P TXD6N TXD5P TXD5N GNDD RXDATAA4 RXDATAA6 RXDATAA8 RXDATAA10 RXDATAA12 RXDATAA14 -- -- -- TXD4P TXD4N 600-Pin Signal Name VDDD TXD2N_TXDBN TXD2P_TXDBP TXD3P_TXDAP TXD3N_TXDAN -- RXDATAA6 RXDATAA5 RXDATAA4 RXDATAA3 RXDATAA2 -- -- -- -- GNDD TXD0P_TXDDP TXD1N_TXDCN TXD1P_TXDCP VDDD2 -- VDDD2 RXDATAA1 RXDATAA0 RXPRTYA GNDD -- -- -- -- TXFSYNCN TXD0N_TXDDN TXFSYNCP TXCLKP TXCLKN -- RXSOPA RXEOPA TXADDRA2 RXENBA VDDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 47 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin U36 U37 U38 U39 V1 V2 V3 V4 V5 V6 V31 V32 V33 V34 V35 V36 V37 V38 V39 W1 W2 W3 W4 W5 W6 W31 W32 W33 W34 W35 W36 W37 W38 W39 Y1 Y2 Y3 Y4 Y5 Y6 792-Pin Signal Name TXD3P_TXDAP TXD3N_TXDAN TXD2P_TXDBP TXD2N_TXDBN RXPRTYA RXDATAA2 RXDATAA3 RXDATAA5 RXDATAA7 RXDATAA9 -- -- -- TXD1P_TXDCP TXD1N_TXDCN TXD0P_TXDDP TXD0N_TXDDN TXCLKP TXCLKN VDDD2 RXEOPA RXSOPA RXDATAA0 RXDATAA1 GNDD -- -- -- GNDD GNDD TXFSYNCN TXFSYNCP RXCLKN_RXDAN VDDD2 VDDD2 RXERRA RXPPAA RXENBA TXADDRA2 GNDD 600-Pin Signal Name -- -- -- -- VDDD VDDD GNDD RXCLKN_RXDAN RXCLKP_RXDAP -- GNDD RXERRA RXPPAA RXADDRA2 VDDD -- -- -- -- VDDD RXD14N_RXCLKAN RXD14P_RXCLKAP RXD15N_RXDBN RXD15P_RXDBP -- RXADDRA0 RXADDRA1 RXCLKA TXADDRB0 RXSZA -- -- -- -- GNDD RXD13N_RXCLKBN RXD13P_RXCLKBP GNDD VDDD2 -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 48 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 AA1 AA2 AA3 AA4 AA5 AA6 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AA39 AB1 AB2 AB3 AB4 AB5 AB6 AB31 AB32 AB33 AB34 AB35 AB36 AB37 AB38 AB39 792-Pin Signal Name -- -- -- GNDD RXD13N_RXCLKBN RXD14P_RXCLKAP RXD14N_RXCLKAN RXCLKP_RXDAP VDDD2 RXADDRA2 RXADDRA1 RXSZA RXADDRA0 RXCLKA GNDD -- -- -- GNDD RXD13P_RXCLKBP RXD15P_RXDBP RXD15N_RXDBN VDDD2 VDDD2 TXADDRB0 TXPPAB TXERRB TXSZB TXCLKB TXADDRB1 -- -- -- RXD9P_RXCLKDP RXD9N_RXCLKDN RXD12P_RXDCP RXD12N_RXDCN RXD11P_RXCLKCP RXD11N_RXCLKCN 600-Pin Signal Name VDDD2 TXSZB TXCLKB TXADDRB1 GNDD -- -- -- -- RXD11N_RXCLKCN RXD11P_RXCLKCP RXD12N_RXDCN RXD12P_RXDCP GNDD -- TXEOPB TXSOPB TXENBB TXPPAB TXERRB -- -- -- -- RXD9N_RXCLKDN RXD9P_RXCLKDP RXD10N_RXDDN RXD10P_RXDDP VDDD -- TXDATAB13 TXDATAB12 TXDATAB14 TXDATAB15 TXPRTYB -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 49 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AC1 AC2 AC3 AC4 AC5 AC6 AC31 AC32 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AD1 AD2 AD3 AD4 AD5 AD6 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AE1 AE2 AE3 AE4 AE5 AE6 AE31 AE32 AE33 AE34 AE35 792-Pin Signal Name TXENBB TXDATAB14 TXDATAB15 TXPRTYB TXSOPB TXEOPB -- -- -- RXD8P RXD8N RXD7P RXD7N RXD10P_RXDDP RXD10N_RXDDN GNDD TXDATAB10 TXDATAB11 TXDATAB13 TXDATAB12 VDDD -- -- -- VDDD RXD6P RXD6N RXD5P RXD5N GNDD GNDD TXDATAB9 TXDATAB8 TXDATAB7 TXDATAB6 VDDD -- -- -- VDDD RXD4P 600-Pin Signal Name GNDD RXD7N RXD7P RXD8N RXD8P -- TXDATAB8 TXDATAB9 TXDATAB10 TXDATAB11 GNDD -- -- -- -- RXD5N RXD5P RXD6N RXD6P VDDD -- TXDATAB3 TXDATAB4 TXDATAB5 TXDATAB6 TXDATAB7 -- -- -- -- RXD3N RXD3P RXD4N RXD4P VDDD -- VDDD RXDATAB15 TXDATAB0 TXDATAB1 TXDATAB2 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 50 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AE36 AE37 AE38 AE39 AF1 AF2 AF3 AF4 AF5 AF6 AF31 AF32 AF33 AF34 AF35 AF36 AF37 AF38 AF39 AG1 AG2 AG3 AG4 AG5 AG6 AG31 AG32 AG33 AG34 AG35 AG36 AG37 AG38 AG39 AH1 AH2 AH3 AH4 AH5 AH6 792-Pin Signal Name RXD4N RXD3P RXD3N GNDD TXDATAB5 TXDATAB4 TXDATAB3 TXDATAB2 TXDATAB1 TXDATAB0 -- -- -- RXD0P RXD0N RXD2P RXD2N RXD1P RXD1N RXDATAB15 RXDATAB14 RXDATAB13 RXDATAB12 RXDATAB10 RXDATAB11 -- -- -- GPIO2 GPIO3 ECLREFHI ECLREFLO VDDD2 VDDD2 VDDD2 RXDATAB9 RXDATAB8 RXDATAB7 RXDATAB6 GNDD 600-Pin Signal Name -- -- -- -- RXD1N RXD1P RXD2N RXD2P VDDD -- RXDATAB10 RXDATAB11 RXDATAB12 RXDATAB13 RXDATAB14 -- -- -- -- RXD0N RXD0P ECLREFLO ECLREFHI GPIO3 -- RXDATAB5 RXDATAB6 RXDATAB7 RXDATAB8 RXDATAB9 -- -- -- -- GNDD GPIO2 GPIO1 GPIO0 TXTOHF -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 51 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AH31 AH32 AH33 AH34 AH35 AH36 AH37 AH38 AH39 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AK1 AK2 AK3 AK4 AK5 AK6 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AK39 792-Pin Signal Name -- -- -- GNDD TXTOHF GPIO0 GPIO1 VDDD2 VDDD2 VDDD2 RXDATAB5 RXDATAB4 RXDATAB3 RXDATAB2 GNDD -- -- -- GNDD TXSPAD TXTOHD TXTOHCLK VDDD2 VDDD2 VDDD2 VDDD2 RXDATAB1 RXDATAB0 RXPRTYB RXEOPB -- -- -- RXREF TXSPAB TXSPAC GNDD VDDD2 VDDD2 600-Pin Signal Name RXDATAB1 RXDATAB2 RXDATAB3 RXDATAB4 GNDD -- -- -- -- GNDD TXTOHCLK TXTOHD TXSPAD TXSPAC -- RXEOPB RXSOPB RXPRTYB RXDATAB0 GNDD -- -- -- -- VDDD2 TXSPAB RXREF RXTOHFA RXTOHCLKA -- RXSZB RXERRB RXPPAB RXENBB VDDD2 -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 52 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AL37 AL38 AL39 792-Pin Signal Name VDDD2 VDDD2 RXSOPB RXENBB RXPPAB RXERRB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXTOHDA RXTOHCLKA RXTOHFA GNDD VDDD2 VDDD2 600-Pin Signal Name VDDD2 RXTOHDA RXTOHFB RXTOHCLKB VDDD2 RXTOHCLKC RXTOHCLKD RXADDRD0 RXPPAD RXDATAD0 VDDD RXDATAD9 RXDATAD14 TXDATAD3 TXDATAD8 VDDD2 TXSOPD VDDD RXADDRC1 VDDD2 RXSOPC RXDATAC3 RXDATAC7 RXDATAC12 VDDD TXDATAC5 TXDATAC10 TXDATAC14 TXEOPC TXSZC VDDD2 RXADDRB1 RXADDRB0 RXCLKB VDDD2 -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 53 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 792-Pin Signal Name VDDD2 VDDD2 GNDD RXSZB RXCLKB RXADDRB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXTOHCLKB RXTOHFB GNDD GNDD VDDD2 VDDD2 600-Pin Signal Name GNDD GNDD GNDD VDDD2 RXTOHDB RXTOHDC TXADDRD0 RXCLKD RXENBD RXDATAD1 RXDATAD5 RXDATAD10 RXDATAD15 TXDATAD2 TXDATAD7 TXDATAD12 TXPRTYD TXERRD TXADDRC2 RXSZC RXEOPC RXDATAC2 RXDATAC6 RXDATAC11 TXDATAC0 TXDATAC4 TXDATAC9 TXDATAC13 TXSOPC TXERRC TXADDRC0 VDDD2 GNDD GNDD GNDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 54 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 792-Pin Signal Name VDDD2 VDDD2 GNDD GNDD RXADDRB1 VDDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDDD VDDD GNDD GNDD VDDD2 VDDD2 600-Pin Signal Name GNDD GNDD VDDD GNDD RXTOHFC GNDD RXTOHDD RXSZD RXEOPD RXDATAD2 RXDATAD6 RXDATAD11 TXDATAD0 TXDATAD4 TXDATAD9 TXDATAD13 TXEOPD TXSZD RXADDRC2 RXCLKC RXENBC RXDATAC1 RXDATAC5 RXDATAC10 RXDATAC15 TXDATAC3 TXDATAC8 TXDATAC12 TXPRTYC TXPPAC TXADDRC1 GNDD VDDD GNDD GNDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 55 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 792-Pin Signal Name GNDD GNDD GNDD GNDD VDDD VDDD VDDD TXADDRC1 TXERRC TXSOPC GNDD GNDD TXDATAC4 RXDATAC14 VDDD VDDD RXEOPC RXADDRC0 GNDD GNDD GNDD TXDATAD7 TXDATAD1 VDDD VDDD RXDATAD1 RXENBD GNDD GNDD RXTOHFD TXADDRD1 RXTOHDB VDDD VDDD VDDD GNDD GNDD GNDD GNDD 600-Pin Signal Name VDDD VDDD GNDD GNDD TXADDRD1 RXTOHFD RXADDRD1 RXERRD RXSOPD RXDATAD3 RXDATAD7 RXDATAD12 TXDATAD1 TXDATAD5 TXDATAD10 TXDATAD14 TXDATAD15 TXPPAD TXCLKD RXADDRC0 RXPPAC RXDATAC0 RXDATAC4 RXDATAC9 RXDATAC14 TXDATAC2 TXDATAC7 TXDATAC11 TXDATAC15 TXENBC TXCLKC GNDD GNDD VDDD VDDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 56 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD VDDD TXADDRC0 TXCLKC TXPPAC TXPRTYC TXDATAC13 TXDATAC9 TXDATAC3 RXDATAC15 RXDATAC8 RXDATAC3 RXSOPC RXCLKC RXADDRC2 TXERRD TXDATAD14 TXDATAD9 TXDATAD3 RXDATAD14 RXDATAD9 RXDATAD3 RXSOPD RXSZD RXADDRD1 RXTOHCLKD RXTOHCLKC RXTOHFC VDDD VDDD GNDD GNDD GNDD GNDD GNDD 600-Pin Signal Name VDDD VDDD GNDD GNDD VDDD2 VDDD2 GNDD GNDD RXPRTYD RXDATAD4 RXDATAD8 RXDATAD13 GNDD TXDATAD6 TXDATAD11 GNDD TXENBD VDDD VDDD GNDD RXERRC RXPRTYC GNDD RXDATAC8 RXDATAC13 TXDATAC1 TXDATAC6 GNDD GNDD VDDD2 VDDD2 GNDD GNDD VDDD VDDD -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 57 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD TXSZC TXENBC TXDATAC15 TXDATAC12 TXDATAC8 TXDATAC5 RXDATAC13 RXDATAC9 RXDATAC4 RXPRTYC RXSZC TXCLKD TXPPAD TXDATAD15 TXDATAD10 TXDATAD5 TXDATAD0 RXDATAD11 RXDATAD6 RXDATAD0 RXPPAD RXADDRD0 TXADDRD0 RXTOHDC GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD 600-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 58 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AU1 AU2 AU3 AU4 AU5 AU6 AU7 AU8 AU9 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 792-Pin Signal Name VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD GNDD GNDD TXEOPC TXDATAC14 TXDATAC11 TXDATAC7 TXDATAC2 TXDATAC0 RXDATAC7 RXDATAC5 RXDATAC0 RXPPAC TXADDRC2 TXSZD TXSOPD TXDATAD12 TXDATAD6 TXDATAD2 RXDATAD12 RXDATAD7 RXDATAD2 RXEOPD RXCLKD RXTOHDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 600-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 59 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AV1 AV2 AV3 AV4 AV5 AV6 AV7 AV8 AV9 AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AV37 AV38 AV39 792-Pin Signal Name VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 VDDD2 TXDATAC10 TXDATAC6 TXDATAC1 RXDATAC12 RXDATAC10 RXDATAC6 RXDATAC2 RXENBC RXADDRC1 TXENBD TXEOPD TXDATAD13 TXDATAD8 TXDATAD4 RXDATAD15 RXDATAD10 RXDATAD5 RXPRTYD RXERRD VDDD2 VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 600-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 60 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued) Pin AW1 AW2 AW3 AW4 AW5 AW6 AW7 AW8 AW9 AW10 AW11 AW12 AW13 AW14 AW15 AW16 AW17 AW18 AW19 AW20 AW21 AW22 AW23 AW24 AW25 AW26 AW27 AW28 AW29 AW30 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AW39 792-Pin Signal Name VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 RXDATAC11 GNDD GNDD RXDATAC1 RXERRC VDDD2 VDDD2 VDDD2 TXPRTYD TXDATAD11 GNDD GNDD RXDATAD13 RXDATAD8 RXDATAD4 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 GNDD GNDD GNDD VDDD2 VDDD2 VDDD2 600-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 61 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name Pin L37 AG36 AG37 A4 A5 A9 A15 A16 A24 A25 A26 A27 A34 A35 A36 B4 B5 B34 B35 B36 C4 C5 C31 C32 C33 C34 C35 C36 D1 D2 D3 D4 D5 D31 D32 D33 D34 D35 D36 792-Pin Signal Name CLKDIV ECLREFHI ECLREFLO GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Pin L37 AG36 AG37 A4 A5 A9 A15 A16 A24 A25 A26 A27 A34 A35 A36 B4 B5 B34 B35 B36 C4 C5 C31 C32 C33 C34 C35 C36 D1 D2 D3 D4 D5 D31 D32 D33 D34 D35 D36 600-Pin Signal Name -- -- -- GNDD VDDD2 MPU_DATA1 MPU_ADDR12 GNDD NC NC NC GNDD VDDD VDDD -- GNDD NC VDDD VDDD -- GNDD PLLREF NC GNDD VDDD GNDD GNDD -- GNDD GNDD GNDD VDDD2 PLLFB NC VDDD2 GNDD GNDD GNDD -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 62 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin D37 D38 D39 E1 E2 E3 E4 E5 E32 E35 E36 E37 E38 E39 F1 F2 F3 F4 F11 F12 F19 F20 F21 F28 F29 F36 F37 F38 F39 G3 G4 G36 G37 H3 H4 H35 H37 J3 J34 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Pin D37 D38 D39 E1 E2 E3 E4 E5 E32 E35 E36 E37 E38 E39 F1 F2 F3 F4 F11 F12 F19 F20 F21 F28 F29 F36 F37 F38 F39 G3 G4 G36 G37 H3 H4 H35 H37 J3 J34 600-Pin Signal Name -- -- -- VDDD2 IDDQMODE PLL_VDDD2 PLL_GNDD VDDD2 NC VDDD2 -- -- -- -- VDDD2 TCLK GNDD TMS -- -- -- -- -- -- -- -- -- -- -- TRSTN NC -- -- GNDD CLKDIV GNDD -- TXD15N TXDATAA15 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 63 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin J36 J37 J38 L6 L34 M6 M34 R1 R39 T1 T39 W6 W34 W35 Y6 Y34 AA6 AA34 AD1 AD39 AE1 AE39 AH6 AH34 AJ6 AJ34 AK37 AL37 AM3 AM36 AM37 AN3 AN4 AN36 AN37 AP1 AP2 AP3 AP4 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Pin J36 J37 J38 L6 L34 M6 M34 R1 R39 T1 T39 W6 W34 W35 Y6 Y34 AA6 AA34 AD1 AD39 AE1 AE39 AH6 AH34 AJ6 AJ34 AK37 AL37 AM3 AM36 AM37 AN3 AN4 AN36 AN37 AP1 AP2 AP3 AP4 600-Pin Signal Name -- -- -- -- TXDATAA6 -- TXDATAA1 VDDD -- GNDD -- -- TXADDRB0 RXSZA -- TXADDRB1 -- TXPPAB RXD5N -- RXD3N -- -- RXDATAB4 -- RXDATAB0 -- -- GNDD -- -- VDDD GNDD -- -- VDDD VDDD GNDD GNDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 64 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AP11 AP12 AP19 AP20 AP21 AP28 AP29 AP36 AP37 AP38 AP39 AR1 AR2 AR3 AR4 AR5 AR35 AR36 AR37 AR38 AR39 AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AU4 AU5 AU6 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Pin AP11 AP12 AP19 AP20 AP21 AP28 AP29 AP36 AP37 AP38 AP39 AR1 AR2 AR3 AR4 AR5 AR35 AR36 AR37 AR38 AR39 AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AU4 AU5 AU6 600-Pin Signal Name RXDATAD7 RXDATAD12 TXCLKD RXADDRC0 RXPPAC TXDATAC11 TXDATAC15 -- -- -- -- VDDD VDDD GNDD GNDD VDDD2 VDDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 65 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AU7 AU8 AU31 AU32 AU33 AU34 AU35 AU36 AV4 AV5 AV6 AV34 AV35 AV36 AW4 AW5 AW6 AW15 AW16 AW24 AW25 AW34 AW35 AW36 AH36 AH37 AG34 AG35 C10 D10 E29 H36 B15 C15 D15 E15 E23 F23 A23 792-Pin Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GPIO0 GPIO1 GPIO2 GPIO3 GNDD VDDD2 ICTN IDDQMODE NC NC NC NC MPU_ADDR0 MPU_ADDR1 MPU_ADDR2 Pin AU7 AU8 AU31 AU32 AU33 AU34 AU35 AU36 AV4 AV5 AV6 AV34 AV35 AV36 AW4 AW5 AW6 AW15 AW16 AW24 AW25 AW34 AW35 AW36 AH36 AH37 AG34 AG35 C10 D10 E29 H36 B15 C15 D15 E15 E23 F23 A23 600-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RXDATAB8 RXDATAB9 MPU_DATA4 MPU_DATA3 NC -- MPU_ADDR11 MPU_ADDR10 NC MPU_ADDR9 NC -- GNDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 66 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin B22 C22 D22 E22 F22 A22 B21 D21 E21 B20 C20 D20 E20 D27 E27 F26 E26 D26 C26 B26 E25 D25 C25 B25 B24 D24 E24 C24 B23 C23 D23 B27 D28 E28 C28 F27 C27 C21 D12 792-Pin Signal Name MPU_ADDR3 MPU_ADDR4 MPU_ADDR5 MPU_ADDR6 MPU_ADDR7 MPU_ADDR8 MPU_ADDR9 MPU_ADDR10 MPU_ADDR11 MPU_ADDR12 MPU_ADDR13 MPU_ADDR14 MPU_ADDR15 MPU_ADSN MPU_CSN MPU_DATA0 MPU_DATA1 MPU_DATA2 MPU_DATA3 MPU_DATA4 MPU_DATA5 MPU_DATA6 MPU_DATA7 MPU_DATA8 MPU_DATA9 MPU_DATA10 MPU_DATA11 MPU_DATA12 MPU_DATA13 MPU_DATA14 MPU_DATA15 MPU_DSN MPU_DTN MPU_INTN MPU_MPCLK MPU_MPMODE MPU_RWN NC NC Pin B22 C22 D22 E22 F22 A22 B21 D21 E21 B20 C20 D20 E20 D27 E27 F26 E26 D26 C26 B26 E25 D25 C25 B25 B24 D24 E24 C24 B23 C23 D23 B27 D28 E28 C28 F27 C27 C21 D12 600-Pin Signal Name NC NC NC NC -- NC NC NC NC NC NC NC VDDD2 VDDD2 NC -- NC NC NC NC VDDD NC NC NC NC NC NC NC NC NC NC NC NC NC NC -- NC NC MPU_DATA12 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 67 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin E30 E31 F30 J35 K37 D30 G35 C30 H34 F32 F31 D29 F13 B11 C11 E13 D13 C12 B12 B13 C13 A13 E14 F14 H5 H6 J6 D7 B7 C7 F8 D8 E8 C8 E9 F9 F10 A8 B8 792-Pin Signal Name NC NC NC NC NC PLL_GND PLL_GNDD PLL_VDDD2 PLL_VDDD2 PLLFB PLLREF PMRST NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin E30 E31 F30 J35 K37 D30 G35 C30 H34 F32 F31 D29 F13 B11 C11 E13 D13 C12 B12 B13 C13 A13 E14 F14 H5 H6 J6 D7 B7 C7 F8 D8 E8 C8 E9 F9 F10 A8 B8 600-Pin Signal Name NC VDDD2 -- TXDATAA14 -- NC GNDD NC TXENBA RXSPAB RXSPAA NC -- MPU_DATA9 MPU_DATA8 MPU_ADDR0 MPU_ADDR1 MPU_DATA13 MPU_DATA14 MPU_ADDR3 MPU_ADDR2 GNDD MPU_ADDR4 -- GNDD -- -- PMRST MPU_INTN RSTN -- MPU_MPMODE MPU_DTN MPU_MPCLK MPU_ADSN -- -- GNDD MPU_CSN Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 68 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin E10 C9 D9 B9 D11 E11 E12 A10 B10 C29 AA4 AA2 AA1 AM6 AN5 AP18 AV19 AR19 AT29 AR29 AA5 AM5 AR18 AU29 W38 Y38 AF35 AF34 AF39 AF38 AF37 AF36 AE38 AE37 AE36 AE35 AD38 AD37 AD36 792-Pin Signal Name NC NC NC NC NC NC NC NC NC RSTN RXADDRA0 RXADDRA1 RXADDRA2 RXADDRB0 RXADDRB1 RXADDRC0 RXADDRC1 RXADDRC2 RXADDRD0 RXADDRD1 RXCLKA RXCLKB RXCLKC RXCLKD RXCLKN_RXDAN RXCLKP_RXDAP RXD0N RXD0P RXD1N RXD1P RXD2N RXD2P RXD3N RXD3P RXD4N RXD4P RXD5N RXD5P RXD6N Pin E10 C9 D9 B9 D11 E11 E12 A10 B10 C29 AA4 AA2 AA1 AM6 AN5 AP18 AV19 AR19 AT29 AR29 AA5 AM5 AR18 AU29 W38 Y38 AF35 AF34 AF39 AF38 AF37 AF36 AE38 AE37 AE36 AE35 AD38 AD37 AD36 600-Pin Signal Name MPU_DATA2 MPU_DSN MPU_RWN MPU_DATA0 MPU_DATA7 VDDD MPU_DATA11 MPU_DATA6 MPU_DATA5 NC RXD12P_RXDCP RXD11P_RXCLKCP RXD11N_RXCLKCN RXTOHDC RXTOHFC TXPPAD -- VDDD -- GNDD GNDD RXTOHDB VDDD -- -- -- RXDATAB14 RXDATAB13 -- -- -- -- -- -- -- TXDATAB2 -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 69 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AD35 AC37 AC36 AC35 AC34 AB35 AB34 AC39 AC38 AB39 AB38 AB37 AB36 Y35 AA35 Y37 Y36 AA37 AA36 W4 W5 V2 V3 U1 V4 U2 V5 U3 V6 U4 T2 U5 T3 U6 T4 AK4 AK3 AJ5 AJ4 792-Pin Signal Name RXD6P RXD7N RXD7P RXD8N RXD8P RXD9N_RXCLKDN RXD9P_RXCLKDP RXD10N_RXDDN RXD10P_RXDDP RXD11N_RXCLKCN RXD11P_RXCLKCP RXD12N_RXDCN RXD12P_RXDCP RXD13N_RXCLKBN RXD13P_RXCLKBP RXD14N_RXCLKAN RXD14P_RXCLKAP RXD15N_RXDBN RXD15P_RXDBP RXDATAA0 RXDATAA1 RXDATAA2 RXDATAA3 RXDATAA4 RXDATAA5 RXDATAA6 RXDATAA7 RXDATAA8 RXDATAA9 RXDATAA10 RXDATAA11 RXDATAA12 RXDATAA13 RXDATAA14 RXDATAA15 RXDATAB0 RXDATAB1 RXDATAB2 RXDATAB3 Pin AD35 AC37 AC36 AC35 AC34 AB35 AB34 AC39 AC38 AB39 AB38 AB37 AB36 Y35 AA35 Y37 Y36 AA37 AA36 W4 W5 V2 V3 U1 V4 U2 V5 U3 V6 U4 T2 U5 T3 U6 T4 AK4 AK3 AJ5 AJ4 600-Pin Signal Name TXDATAB7 -- -- GNDD TXDATAB11 TXPRTYB TXDATAB15 -- -- -- -- -- -- GNDD TXERRB -- -- -- -- RXD15N_RXDBN RXD15P_RXDBP VDDD GNDD TXFSYNCN RXCLKN_RXDAN TXD0N_TXDDN RXCLKP_RXDAP TXFSYNCP -- TXCLKP TXD0P_TXDDP TXCLKN TXD1N_TXDCN -- TXD1P_TXDCP RXTOHFA RXREF TXSPAC TXSPAD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 70 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AJ3 AJ2 AH5 AH4 AH3 AH2 AG5 AG6 AG4 AG3 AG2 AG1 AU17 AW17 AV17 AR16 AT16 AU16 AV16 AU15 AR15 AT15 AV15 AW14 AV14 AT14 AP14 AR14 AT27 AP26 AU27 AR26 AW28 AV27 AT26 AU26 AW27 AR25 AV26 792-Pin Signal Name RXDATAB4 RXDATAB5 RXDATAB6 RXDATAB7 RXDATAB8 RXDATAB9 RXDATAB10 RXDATAB11 RXDATAB12 RXDATAB13 RXDATAB14 RXDATAB15 RXDATAC0 RXDATAC1 RXDATAC2 RXDATAC3 RXDATAC4 RXDATAC5 RXDATAC6 RXDATAC7 RXDATAC8 RXDATAC9 RXDATAC10 RXDATAC11 RXDATAC12 RXDATAC13 RXDATAC14 RXDATAC15 RXDATAD0 RXDATAD1 RXDATAD2 RXDATAD3 RXDATAD4 RXDATAD5 RXDATAD6 RXDATAD7 RXDATAD8 RXDATAD9 RXDATAD10 Pin AJ3 AJ2 AH5 AH4 AH3 AH2 AG5 AG6 AG4 AG3 AG2 AG1 AU17 AW17 AV17 AR16 AT16 AU16 AV16 AU15 AR15 AT15 AV15 AW14 AV14 AT14 AP14 AR14 AT27 AP26 AU27 AR26 AW28 AV27 AT26 AU26 AW27 AR25 AV26 600-Pin Signal Name TXTOHD TXTOHCLK TXTOHF GPIO0 GPIO1 GPIO2 GPIO3 -- ECLREFHI ECLREFLO RXD0P RXD0N -- -- -- GNDD -- -- -- -- TXDATAD11 -- -- -- -- -- TXDATAD5 TXDATAD6 -- TXDATAC2 -- TXDATAC1 -- -- -- -- -- RXDATAC13 -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 71 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AT25 AU25 AW26 AR24 AV25 Y4 AL4 AV18 AP27 W2 AK6 AP17 AU28 Y2 AL6 AW18 AV29 Y3 AL5 AU18 AT28 V1 AK5 AT17 AV28 AK34 W3 AL3 AR17 AR27 K6 J5 J4 K5 AA3 AM4 AT18 AR28 AL35 792-Pin Signal Name RXDATAD11 RXDATAD12 RXDATAD13 RXDATAD14 RXDATAD15 RXENBA RXENBB RXENBC RXENBD RXEOPA RXEOPB RXEOPC RXEOPD RXERRA RXERRB RXERRC RXERRD RXPPAA RXPPAB RXPPAC RXPPAD RXPRTYA RXPRTYB RXPRTYC RXPRTYD RXREF RXSOPA RXSOPB RXSOPC RXSOPD RXSPAA RXSPAB RXSPAC RXSPAD RXSZA RXSZB RXSZC RXSZD RXTOHCLKA Pin AT25 AU25 AW26 AR24 AV25 Y4 AL4 AV18 AP27 W2 AK6 AP17 AU28 Y2 AL6 AW18 AV29 Y3 AL5 AU18 AT28 V1 AK5 AT17 AV28 AK34 W3 AL3 AR17 AR27 K6 J5 J4 K5 AA3 AM4 AT18 AR28 AL35 600-Pin Signal Name -- -- -- RXDATAC8 -- GNDD RXTOHCLKB -- TXDATAC7 RXD14N_RXCLKAN -- TXDATAD15 -- RXD13N_RXCLKBN RXTOHCLKC -- -- RXD13P_RXCLKBP VDDD2 -- -- VDDD RXTOHCLKA -- -- RXENBB RXD14P_RXCLKAP RXTOHFB TXENBD TXDATAC6 -- TXCLKQN TXD15P VDDD RXD12N_RXDCN VDDD2 -- GNDD VDDD2 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 72 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AM34 AR31 AR30 AL34 AP32 AT31 AU30 AL36 AM35 AR32 AP30 C18 D18 A18 B18 D19 E19 B19 C19 C14 D14 A14 B14 D16 E16 B16 C16 E17 F17 C17 D17 A17 B17 F18 E18 K35 K36 L36 K34 792-Pin Signal Name RXTOHCLKB RXTOHCLKC RXTOHCLKD RXTOHDA RXTOHDB RXTOHDC RXTOHDD RXTOHFA RXTOHFB RXTOHFC RXTOHFD NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC TCLK TDI TDO TMS Pin AM34 AR31 AR30 AL34 AP32 AT31 AU30 AL36 AM35 AR32 AP30 C18 D18 A18 B18 D19 E19 B19 C19 C14 D14 A14 B14 D16 E16 B16 C16 E17 F17 C17 D17 A17 B17 F18 E18 K35 K36 L36 K34 600-Pin Signal Name GNDD VDDD2 VDDD2 RXCLKB GNDD -- -- -- GNDD GNDD TXENBC NC NC VDDD NC NC NC NC NC MPU_ADDR6 MPU_ADDR5 MPU_ADDR8 MPU_ADDR7 MPU_ADDR13 VDDD2 MPU_ADDR15 MPU_ADDR14 NC -- NC NC VDDD NC -- NC TXDATAA9 -- -- TXDATAA10 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 73 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin L35 L5 K3 Y5 AB1 AB6 AR7 AP8 AU19 AT30 AP31 L4 AB5 AR8 AT19 V39 V38 M36 M35 V37 V36 V35 V34 U39 U38 U37 U36 U35 U34 T38 T37 T36 T35 R38 R37 P39 P38 R36 R35 792-Pin Signal Name TRSTN TXADDRA0 TXADDRA1 TXADDRA2 TXADDRB0 TXADDRB1 TXADDRC0 TXADDRC1 TXADDRC2 TXADDRD0 TXADDRD1 TXCLKA TXCLKB TXCLKC TXCLKD TXCLKN TXCLKP TXCLKQN TXCLKQP TXD0N_TXDDN TXD0P_TXDDP TXD1N_TXDCN TXD1P_TXDCP TXD2N_TXDBN TXD2P_TXDBP TXD3N_TXDAN TXD3P_TXDAP TXD4N TXD4P TXD5N TXD5P TXD6N TXD6P TXD7N TXD7P TXD8N TXD8P TXD9N TXD9P Pin L35 L5 K3 Y5 AB1 AB6 AR7 AP8 AU19 AT30 AP31 L4 AB5 AR8 AT19 V39 V38 M36 M35 V37 V36 V35 V34 U39 U38 U37 U36 U35 U34 T38 T37 T36 T35 R38 R37 P39 P38 R36 R35 600-Pin Signal Name TXDATAA5 VDDD TXD13N VDDD2 RXD9N_RXCLKDN -- GNDD RXERRD -- -- TXCLKC TXD11P VDDD GNDD -- -- -- -- TXDATAA0 -- -- VDDD RXADDRA2 -- -- -- -- VDDD RXENBA -- -- -- GNDD -- -- -- -- -- RXDATAA2 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 74 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin P37 P36 P35 P34 N39 N38 N37 N36 N35 N34 M38 M37 R2 T5 P1 R3 R4 P2 R5 N1 P3 P4 N2 P5 N3 N4 P6 M2 AF6 AF5 AF4 AF3 AF2 AF1 AE5 AE4 AE3 AE2 AD2 792-Pin Signal Name TXD10N TXD10P TXD11N TXD11P TXD12N TXD12P TXD13N TXD13P TXD14N TXD14P TXD15N TXD15P TXDATAA0 TXDATAA1 TXDATAA2 TXDATAA3 TXDATAA4 TXDATAA5 TXDATAA6 TXDATAA7 TXDATAA8 TXDATAA9 TXDATAA10 TXDATAA11 TXDATAA12 TXDATAA13 TXDATAA14 TXDATAA15 TXDATAB0 TXDATAB1 TXDATAB2 TXDATAB3 TXDATAB4 TXDATAB5 TXDATAB6 TXDATAB7 TXDATAB8 TXDATAB9 TXDATAB10 Pin P37 P36 P35 P34 N39 N38 N37 N36 N35 N34 M38 M37 R2 T5 P1 R3 R4 P2 R5 N1 P3 P4 N2 P5 N3 N4 P6 M2 AF6 AF5 AF4 AF3 AF2 AF1 AE5 AE4 AE3 AE2 AD2 600-Pin Signal Name -- -- RXDATAA7 RXDATAA8 -- -- -- -- GNDD RXDATAA12 -- -- TXD2N_TXDBN VDDD2 TXD4N TXD2P_TXDBP TXD3P_TXDAP TXD4P TXD3N_TXDAN GNDD TXD5N VDDD TXD6N TXD5P TXD6P TXD7N -- TXD8P -- VDDD RXD2P RXD2N RXD1P RXD1N VDDD RXD4P RXD4N RXD3P RXD5P Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 75 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AD3 AD5 AD4 AC2 AC3 AU14 AV13 AU13 AR13 AP13 AT13 AV12 AU12 AT12 AR12 AV11 AU11 AT11 AR11 AU10 AT10 AT24 AP23 AU24 AR23 AV24 AT23 AU23 AP22 AV23 AR22 AT22 AW23 AU22 AV22 AR21 AT21 N6 AC1 792-Pin Signal Name TXDATAB11 TXDATAB12 TXDATAB13 TXDATAB14 TXDATAB15 TXDATAC0 TXDATAC1 TXDATAC2 TXDATAC3 TXDATAC4 TXDATAC5 TXDATAC6 TXDATAC7 TXDATAC8 TXDATAC9 TXDATAC10 TXDATAC11 TXDATAC12 TXDATAC13 TXDATAC14 TXDATAC15 TXDATAD0 TXDATAD1 TXDATAD2 TXDATAD3 TXDATAD4 TXDATAD5 TXDATAD6 TXDATAD7 TXDATAD8 TXDATAD9 TXDATAD10 TXDATAD11 TXDATAD12 TXDATAD13 TXDATAD14 TXDATAD15 TXENBA TXENBB Pin AD3 AD5 AD4 AC2 AC3 AU14 AV13 AU13 AR13 AP13 AT13 AV12 AU12 AT12 AR12 AV11 AU11 AT11 AR11 AU10 AT10 AT24 AP23 AU24 AR23 AV24 AT23 AU23 AP22 AV23 AR22 AT22 AW23 AU22 AV22 AR21 AT21 N6 AC1 600-Pin Signal Name RXD6N VDDD RXD6P RXD7N RXD7P -- -- -- GNDD TXDATAD1 -- -- -- -- RXDATAD13 -- -- -- RXDATAD8 -- -- -- RXDATAC4 -- GNDD -- -- -- RXDATAC0 -- RXPRTYC -- -- -- -- RXERRC -- -- GNDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 76 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AT9 AV20 L2 AC6 AU9 AV21 L3 AB3 AP9 AR20 W36 W37 M4 AB2 AR9 AT20 N5 AC4 AR10 AW22 M3 AC5 AP10 AU21 K4 AK35 AK36 AJ35 M5 AB4 AT8 AU20 AJ37 AJ36 AH35 E6 E7 E33 E34 792-Pin Signal Name TXENBC TXENBD TXEOPA TXEOPB TXEOPC TXEOPD TXERRA TXERRB TXERRC TXERRD TXFSYNCN TXFSYNCP TXPPAA TXPPAB TXPPAC TXPPAD TXPRTYA TXPRTYB TXPRTYC TXPRTYD TXSOPA TXSOPB TXSOPC TXSOPD TXSPAA TXSPAB TXSPAC TXSPAD TXSZA TXSZB TXSZC TXSZD TXTOHCLK TXTOHD TXTOHF VDDD VDDD VDDD VDDD Pin AT9 AV20 L2 AC6 AU9 AV21 L3 AB3 AP9 AR20 W36 W37 M4 AB2 AR9 AT20 N5 AC4 AR10 AW22 M3 AC5 AP10 AU21 K4 AK35 AK36 AJ35 M5 AB4 AT8 AU20 AJ37 AJ36 AH35 E6 E7 E33 E34 600-Pin Signal Name -- -- TXD10P -- -- -- TXD11N RXD10N_RXDDN RXSOPD GNDD -- -- TXD9P RXD9P_RXCLKDP RXPRTYD -- TXD7P RXD8N RXDATAD4 -- TXD9N RXD8P RXDATAD3 -- TXD13P VDDD2 -- GNDD VDDD RXD10P_RXDDP -- -- -- -- GNDD NC ICTN NC NC Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 77 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin F5 F6 F7 F15 F16 F24 F25 F33 F34 F35 G5 G6 G34 R6 R34 T6 T34 AD6 AD34 AE6 AE34 AN6 AN34 AN35 AP5 AP6 AP7 AP15 AP16 AP24 AP25 AP33 AP34 AP35 AR6 AR33 AR34 A1 A2 792-Pin Signal Name VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD2 VDDD2 Pin F5 F6 F7 F15 F16 F24 F25 F33 F34 F35 G5 G6 G34 R6 R34 T6 T34 AD6 AD34 AE6 AE34 AN6 AN34 AN35 AP5 AP6 AP7 AP15 AP16 AP24 AP25 AP33 AP34 AP35 AR6 AR33 AR34 A1 A2 600-Pin Signal Name NC -- -- -- -- -- -- RXSPAC RXSPAD VDDD2 TDI -- TXCLKA -- RXDATAA3 -- RXPRTYA -- TXDATAB6 -- TXDATAB1 GNDD GNDD GNDD TXADDRD1 RXTOHFD RXADDRD1 TXDATAD10 TXDATAD14 RXDATAC9 RXDATAC14 GNDD VDDD VDDD VDDD2 GNDD VDDD VDDD VDDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 78 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin A3 A6 A7 A11 A12 A19 A20 A21 A28 A29 A30 A31 A32 A33 A37 A38 A39 B1 B2 B3 B6 B28 B29 B30 B31 B32 B33 B37 B38 B39 C1 C2 C3 C6 C37 C38 C39 D6 G1 792-Pin Signal Name VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 Pin A3 A6 A7 A11 A12 A19 A20 A21 A28 A29 A30 A31 A32 A33 A37 A38 A39 B1 B2 B3 B6 B28 B29 B30 B31 B32 B33 B37 B38 B39 C1 C2 C3 C6 C37 C38 C39 D6 G1 600-Pin Signal Name GNDD VDDD2 GNDD MPU_DATA10 MPU_DATA15 NC GNDD NC GNDD GNDD VDDD2 VDDD2 GNDD GNDD -- -- -- VDDD VDDD GNDD PLL_VDDD2 NC NC NC NC GNDD GNDD -- -- -- GNDD GNDD VDDD PLL_GND -- -- -- NC GNDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 79 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin G2 G38 G39 H1 H2 H38 H39 J1 J2 J39 K1 K2 K38 K39 L1 L38 L39 M1 M39 W1 W39 Y1 Y39 AA38 AA39 AG38 AG39 AH1 AH38 AH39 AJ1 AJ38 AJ39 AK1 AK2 AK38 AK39 AL1 AL2 792-Pin Signal Name VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 Pin G2 G38 G39 H1 H2 H38 H39 J1 J2 J39 K1 K2 K38 K39 L1 L38 L39 M1 M39 W1 W39 Y1 Y39 AA38 AA39 AG38 AG39 AH1 AH38 AH39 AJ1 AJ38 AJ39 AK1 AK2 AK38 AK39 AL1 AL2 600-Pin Signal Name TDO -- -- GNDD TXCLKQP -- -- TXD14N TXD14P -- TXD12N TXD12P -- -- TXD10N -- -- TXD8N -- VDDD -- GNDD -- -- -- -- -- GNDD -- -- GNDD -- -- VDDD2 TXSPAB -- -- VDDD2 RXTOHDA Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 80 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AL38 AL39 AM1 AM2 AM38 AM39 AN1 AN2 AN38 AN39 AU1 AU2 AU3 AU37 AU38 AU39 AV1 AV2 AV3 AV7 AV8 AV9 AV10 AV30 AV31 AV32 AV33 AV37 AV38 AV39 AW1 AW2 AW3 AW7 AW8 AW9 AW10 AW11 AW12 792-Pin Signal Name VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 Pin AL38 AL39 AM1 AM2 AM38 AM39 AN1 AN2 AN38 AN39 AU1 AU2 AU3 AU37 AU38 AU39 AV1 AV2 AV3 AV7 AV8 AV9 AV10 AV30 AV31 AV32 AV33 AV37 AV38 AV39 AW1 AW2 AW3 AW7 AW8 AW9 AW10 AW11 AW12 600-Pin Signal Name -- -- GNDD GNDD -- -- GNDD GNDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 81 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AW13 AW19 AW20 AW21 AW29 AW30 AW31 AW32 AW33 AW37 AW38 AW39 G31 G32 G33 H31 H32 H33 J31 J32 J33 K31 K32 K33 L31 L32 L33 M31 M32 M33 N31 N32 N33 P31 P32 P33 R31 R32 R33 792-Pin Signal Name VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin AW13 AW19 AW20 AW21 AW29 AW30 AW31 AW32 AW33 AW37 AW38 AW39 G31 G32 G33 H31 H32 H33 J31 J32 J33 K31 K32 K33 L31 L32 L33 M31 M32 M33 N31 N32 N33 P31 P32 P33 R31 R32 R33 600-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- TXSPAA TXADDRA0 TXADDRA1 TXSZA TXERRA TXPPAA TXEOPA TXSOPA TXPRTYA TXDATAA13 TXDATAA12 TXDATAA11 VDDD TXDATAA8 TXDATAA7 TXDATAA4 TXDATAA3 TXDATAA2 RXDATAA15 RXDATAA14 RXDATAA13 RXDATAA11 RXDATAA10 RXDATAA9 RXDATAA6 RXDATAA5 RXDATAA4 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 82 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin T31 T32 T33 U31 U32 U33 V31 V32 V33 W31 W32 W33 Y31 Y32 Y33 AA31 AA32 AA33 AB31 AB32 AB33 AC31 AC32 AC33 AD31 AD32 AD33 AE31 AE32 AE33 AF31 AF32 AF33 AG31 AG32 AG33 AH31 AH32 AH33 792-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin T31 T32 T33 U31 U32 U33 V31 V32 V33 W31 W32 W33 Y31 Y32 Y33 AA31 AA32 AA33 AB31 AB32 AB33 AC31 AC32 AC33 AD31 AD32 AD33 AE31 AE32 AE33 AF31 AF32 AF33 AG31 AG32 AG33 AH31 AH32 AH33 600-Pin Signal Name VDDD2 RXDATAA1 RXDATAA0 RXSOPA RXEOPA TXADDRA2 GNDD RXERRA RXPPAA RXADDRA0 RXADDRA1 RXCLKA VDDD2 TXSZB TXCLKB TXEOPB TXSOPB TXENBB TXDATAB13 TXDATAB12 TXDATAB14 TXDATAB8 TXDATAB9 TXDATAB10 TXDATAB3 TXDATAB4 TXDATAB5 VDDD RXDATAB15 TXDATAB0 RXDATAB10 RXDATAB11 RXDATAB12 RXDATAB5 RXDATAB6 RXDATAB7 RXDATAB1 RXDATAB2 RXDATAB3 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 83 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AJ31 AJ32 AJ33 AK31 AK32 AK33 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AM7 AM8 AM9 AM10 AM11 AM12 792-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin AJ31 AJ32 AJ33 AK31 AK32 AK33 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AM7 AM8 AM9 AM10 AM11 AM12 600-Pin Signal Name RXEOPB RXSOPB RXPRTYB RXSZB RXERRB RXPPAB RXTOHCLKD RXADDRD0 RXPPAD RXDATAD0 VDDD RXDATAD9 RXDATAD14 TXDATAD3 TXDATAD8 VDDD2 TXSOPD VDDD RXADDRC1 VDDD2 RXSOPC RXDATAC3 RXDATAC7 RXDATAC12 VDDD TXDATAC5 TXDATAC10 TXDATAC14 TXEOPC TXSZC VDDD2 RXADDRB1 RXADDRB0 TXADDRD0 RXCLKD RXENBD RXDATAD1 RXDATAD5 RXDATAD10 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 84 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 792-Pin Signal Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 600-Pin Signal Name RXDATAD15 TXDATAD2 TXDATAD7 TXDATAD12 TXPRTYD TXERRD TXADDRC2 RXSZC RXEOPC RXDATAC2 RXDATAC6 RXDATAC11 TXDATAC0 TXDATAC4 TXDATAC9 TXDATAC13 TXSOPC TXERRC TXADDRC0 VDDD2 GNDD RXTOHDD RXSZD RXEOPD RXDATAD2 RXDATAD6 RXDATAD11 TXDATAD0 TXDATAD4 TXDATAD9 TXDATAD13 TXEOPD TXSZD RXADDRC2 RXCLKC RXENBC RXDATAC1 RXDATAC5 RXDATAC10 Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. Agere Systems Inc. 85 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 792-Pin PBGA Pin Assignments (continued) Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued) Pin AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 792-Pin Signal Name -- -- -- -- -- -- -- -- -- Pin AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 600-Pin Signal Name RXDATAC15 TXDATAC3 TXDATAC8 TXDATAC12 TXPRTYC TXPPAC TXADDRC1 GNDD VDDD Note: NC refers to no connect. Do not connect pins so designated. -- indicates the pin does not exist for the specified package. 86 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 600-Pin LBGA Pin Assignments Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 Signal Name VDDD VDDD GNDD GNDD VDDD2 VDDD2 GNDD GNDD MPU_DATA1 MPU_DATA6 MPU_DATA10 MPU_DATA15 Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 Signal Name VDDD VDDD GNDD GNDD NC PLL_VDDD2 MPU_INTN MPU_CSN MPU_DATA0 MPU_DATA5 MPU_DATA9 MPU_DATA14 MPU_ADDR3 MPU_ADDR7 MPU_ADDR11 MPU_ADDR15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GNDD GNDD VDDD VDDD Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 Signal Name GNDD GNDD VDDD GNDD PLLREF PLL_GND RSTN MPU_MPCLK MPU_DSN MPU_DATA4 MPU_DATA8 MPU_DATA13 MPU_ADDR2 MPU_ADDR6 MPU_ADDR10 MPU_ADDR14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GNDD VDDD GNDD GNDD Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 Signal Name GNDD GNDD GNDD VDDD2 PLLFB NC PMRST MPU_MPMODE MPU_RWN MPU_DATA3 MPU_DATA7 MPU_DATA12 GNDD MPU_ADDR8 MPU_ADDR12 MPU_ADDR1 MPU_ADDR5 NC MPU_ADDR13 GNDD VDDD VDDD NC GNDD NC NC GNDD NC NC NC GNDD GNDD GNDD VDDD2 VDDD2 GNDD GNDD VDDD VDDD NC NC NC NC NC NC NC NC NC NC VDDD2 NC NC NC NC VDDD2 GNDD GNDD GNDD Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 87 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 Signal Name VDDD2 IDDQMODE PLL_VDDD2 PLL_GNDD VDDD2 NC ICTN MPU_DTN MPU_ADSN MPU_DATA2 VDDD MPU_DATA11 MPU_ADDR0 MPU_ADDR4 MPU_ADDR9 VDDD2 NC NC NC VDDD2 NC NC NC NC VDDD NC NC NC NC NC VDDD2 NC NC NC VDDD2 Pin F1 F2 F3 F4 F5 F31 F32 F33 F34 F35 G1 G2 G3 G4 G5 G31 G32 G33 G34 G35 H1 H2 H3 H4 H5 H31 H32 H33 H34 H35 J1 J2 J3 J4 J5 Signal Name VDDD2 TCLK GNDD TMS NC RXSPAA RXSPAB RXSPAC RXSPAD VDDD2 GNDD TDO TRSTN NC TDI TXSPAA TXADDRA0 TXADDRA1 TXCLKA GNDD GNDD TXCLKQP GNDD CLKDIV GNDD TXSZA TXERRA TXPPAA TXENBA GNDD TXD14N TXD14P TXD15N TXD15P TXCLKQN Pin J31 J32 J33 J34 J35 K1 K2 K3 K4 K5 K31 K32 K33 K34 K35 L1 L2 L3 L4 L5 L31 L32 L33 L34 L35 M1 M2 M3 M4 M5 M31 M32 M33 M34 M35 Signal Name TXEOPA TXSOPA TXPRTYA TXDATAA15 TXDATAA14 TXD12N TXD12P TXD13N TXD13P VDDD TXDATAA13 TXDATAA12 TXDATAA11 TXDATAA10 TXDATAA9 TXD10N TXD10P TXD11N TXD11P VDDD VDDD TXDATAA8 TXDATAA7 TXDATAA6 TXDATAA5 TXD8N TXD8P TXD9N TXD9P VDDD TXDATAA4 TXDATAA3 TXDATAA2 TXDATAA1 TXDATAA0 Pin N1 N2 N3 N4 N5 N31 N32 N33 N34 N35 P1 P2 P3 P4 P5 P31 P32 P33 P34 P35 R1 R2 R3 R4 R5 R31 R32 R33 R34 R35 T1 T2 T3 T4 T5 Signal Name GNDD TXD6N TXD6P TXD7N TXD7P RXDATAA15 RXDATAA14 RXDATAA13 RXDATAA12 GNDD TXD4N TXD4P TXD5N VDDD TXD5P RXDATAA11 RXDATAA10 RXDATAA9 RXDATAA8 RXDATAA7 VDDD TXD2N_TXDBN TXD2P_TXDBP TXD3P_TXDAP TXD3N_TXDAN RXDATAA6 RXDATAA5 RXDATAA4 RXDATAA3 RXDATAA2 GNDD TXD0P_TXDDP TXD1N_TXDCN TXD1P_TXDCP VDDD2 Note: NC refers to no connect. Do not connect pins so designated. 88 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin T31 T32 T33 T34 T35 U1 U2 U3 U4 U5 U31 U32 U33 U34 U35 V1 V2 V3 V4 V5 V31 V32 V33 V34 V35 W1 W2 W3 W4 W5 W31 W32 W33 W34 W35 Signal Name VDDD2 RXDATAA1 RXDATAA0 RXPRTYA GNDD TXFSYNCN TXD0N_TXDDN TXFSYNCP TXCLKP TXCLKN RXSOPA RXEOPA TXADDRA2 RXENBA VDDD VDDD VDDD GNDD RXCLKN_ RXDAN RXCLKP_ RXDAP Pin Y1 Y2 Y3 Y4 Y5 Y31 Y32 Y33 Y34 Y35 AA1 AA2 AA3 AA4 AA5 AA31 AA32 AA33 AA34 Signal Name GNDD RXD13N_RXCLKBN RXD13P_RXCLKBP GNDD VDDD2 VDDD2 TXSZB TXCLKB TXADDRB1 GNDD RXD11N_RXCLKCN RXD11P_RXCLKCP RXD12N_RXDCN RXD12P_RXDCP GNDD TXEOPB TXSOPB TXENBB TXPPAB Pin AC31 AC32 AC33 AC34 AC35 AD1 AD2 AD3 AD4 AD5 AD31 AD32 AD33 AD34 AD35 AE1 AE2 AE3 AE4 AE5 AE31 AE32 AE33 AE34 AE35 AF1 AF2 AF3 AF4 AF5 AF31 AF32 AF33 AF34 AF35 Signal Name TXDATAB8 TXDATAB9 TXDATAB10 TXDATAB11 GNDD RXD5N RXD5P RXD6N RXD6P VDDD TXDATAB3 TXDATAB4 TXDATAB5 TXDATAB6 TXDATAB7 RXD3N RXD3P RXD4N RXD4P VDDD VDDD RXDATAB15 TXDATAB0 TXDATAB1 TXDATAB2 RXD1N RXD1P RXD2N RXD2P VDDD RXDATAB10 RXDATAB11 RXDATAB12 RXDATAB13 RXDATAB14 Pin AG1 AG2 AG3 AG4 AG5 AG31 AG32 AG33 AG34 AG35 AH1 AH2 AH3 AH4 AH5 AH31 AH32 AH33 AH34 Signal Name RXD0N RXD0P ECLREFLO ECLREFHI GPIO3 RXDATAB5 RXDATAB6 RXDATAB7 RXDATAB8 RXDATAB9 GNDD GPIO2 GPIO1 GPIO0 TXTOHF RXDATAB1 RXDATAB2 RXDATAB3 RXDATAB4 AA35 TXERRB AB1 AB2 AB3 AB4 AB5 AB31 AB32 RXD9N_RXCLKDN RXD9P_RXCLKDP RXD10N_RXDDN RXD10P_RXDDP VDDD TXDATAB13 TXDATAB12 AH35 GNDD AJ1 AJ2 AJ3 AJ4 AJ5 AJ31 AJ32 GNDD TXTOHCLK TXTOHD TXSPAD TXSPAC RXEOPB RXSOPB GNDD RXERRA RXPPAA RXADDRA2 VDDD VDDD RXD14N_ RXCLKAN RXD14P_ RXCLKAP RXD15N_ RXDBN RXD15P_ RXDBP RXADDRA0 RXADDRA1 RXCLKA TXADDRB0 RXSZA AB33 TXDATAB14 AB34 TXDATAB15 AB35 TXPRTYB AC1 AC2 AC3 AC4 AC5 GNDD RXD7N RXD7P RXD8N RXD8P AJ33 RXPRTYB AJ34 RXDATAB0 AJ35 GNDD AK1 AK2 AK3 AK4 AK5 VDDD2 TXSPAB RXREF RXTOHFA RXTOHCLKA Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 89 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin AK31 AK32 AK33 AK34 AK35 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 Signal Name RXSZB RXERRB RXPPAB RXENBB VDDD2 VDDD2 RXTOHDA RXTOHFB RXTOHCLKB VDDD2 RXTOHCLKC RXTOHCLKD RXADDRD0 RXPPAD RXDATAD0 VDDD RXDATAD9 RXDATAD14 TXDATAD3 TXDATAD8 VDDD2 TXSOPD VDDD RXADDRC1 VDDD2 RXSOPC RXDATAC3 RXDATAC7 RXDATAC12 VDDD TXDATAC5 TXDATAC10 TXDATAC14 TXEOPC TXSZC Pin AL31 AL32 AL33 AL34 AL35 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 Signal Name VDDD2 RXADDRB1 RXADDRB0 RXCLKB VDDD2 GNDD GNDD GNDD VDDD2 RXTOHDB RXTOHDC TXADDRD0 RXCLKD RXENBD RXDATAD1 RXDATAD5 RXDATAD10 RXDATAD15 TXDATAD2 TXDATAD7 TXDATAD12 TXPRTYD TXERRD TXADDRC2 RXSZC RXEOPC RXDATAC2 RXDATAC6 RXDATAC11 TXDATAC0 TXDATAC4 TXDATAC9 TXDATAC13 TXSOPC TXERRC Pin AM31 AM32 AM33 AM34 AM35 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 Signal Name TXADDRC0 VDDD2 GNDD GNDD GNDD GNDD GNDD VDDD GNDD RXTOHFC GNDD RXTOHDD RXSZD RXEOPD RXDATAD2 RXDATAD6 RXDATAD11 TXDATAD0 TXDATAD4 TXDATAD9 TXDATAD13 TXEOPD TXSZD RXADDRC2 RXCLKC RXENBC RXDATAC1 RXDATAC5 RXDATAC10 RXDATAC15 TXDATAC3 TXDATAC8 TXDATAC12 TXPRTYC TXPPAC Pin AN31 AN32 AN33 AN34 AN35 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 Signal Name TXADDRC1 GNDD VDDD GNDD GNDD VDDD VDDD GNDD GNDD TXADDRD1 RXTOHFD RXADDRD1 RXERRD RXSOPD RXDATAD3 RXDATAD7 RXDATAD12 TXDATAD1 TXDATAD5 TXDATAD10 TXDATAD14 TXDATAD15 TXPPAD TXCLKD RXADDRC0 RXPPAC RXDATAC0 RXDATAC4 RXDATAC9 RXDATAC14 TXDATAC2 TXDATAC7 TXDATAC11 TXDATAC15 TXENBC Note: NC refers to no connect. Do not connect pins so designated. 90 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin AP31 AP32 AP33 AP34 AP35 AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 Signal Name TXCLKC GNDD GNDD VDDD VDDD VDDD VDDD GNDD GNDD VDDD2 VDDD2 GNDD GNDD RXPRTYD RXDATAD4 RXDATAD8 RXDATAD13 GNDD TXDATAD6 TXDATAD11 GNDD TXENBD VDDD VDDD GNDD RXERRC RXPRTYC GNDD RXDATAC8 RXDATAC13 TXDATAC1 TXDATAC6 GNDD GNDD VDDD2 Pin AR31 AR32 AR33 AR34 AR35 Signal Name VDDD2 GNDD GNDD VDDD VDDD Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 91 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 6. Pin Assignments for 600-Pin LBGA by Signal Name Signal Name CLKDIV ECLREFHI ECLREFLO GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Pin H4 AG4 AG3 A3 A4 A7 A8 A13 A16 A20 A23 A28 A29 A32 A33 B3 B4 B32 B33 C1 C2 C4 C32 C34 C35 D1 D2 D3 D33 D34 D35 F3 G1 G35 H1 Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Pin H3 H5 H35 N1 N35 T1 T35 V3 V31 Y1 Y4 Y35 AA5 AC1 AC35 AH1 AH35 AJ1 AJ35 AM1 AM2 AM3 AM33 AM34 AM35 AN1 AN2 AN4 AN6 AN32 AN34 AN35 AP3 AP4 AP32 Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GPIO0 GPIO1 GPIO2 GPIO3 GNDD NC VDDD2 ICTN IDDQMODE NC NC NC NC MPU_ADDR0 MPU_ADDR1 MPU_ADDR2 MPU_ADDR3 MPU_ADDR4 MPU_ADDR5 MPU_ADDR6 MPU_ADDR7 MPU_ADDR8 Pin AP33 AR3 AR4 AR7 AR8 AR13 AR16 AR20 AR23 AR28 AR29 AR32 AR33 AH4 AH3 AH2 AG5 A27 E26 D27 E7 E2 D21 A22 B22 C22 E13 D13 C13 B13 E14 D14 C14 B14 A14 Signal Name MPU_ADDR9 MPU_ADDR10 MPU_ADDR11 MPU_ADDR12 Pin E15 C15 B15 A15 D16 C16 B16 E9 B8 B9 A9 E10 D10 C10 B10 A10 D11 C11 B11 A11 E12 D12 C12 B12 A12 C9 E8 B7 C8 D8 D9 D6 E6 F5 C6 MPU_ADDR13 MPU_ADDR14 MPU_ADDR15 MPU_ADSN MPU_CSN MPU_DATA0 MPU_DATA1 MPU_DATA2 MPU_DATA3 MPU_DATA4 MPU_DATA5 MPU_DATA6 MPU_DATA7 MPU_DATA8 MPU_DATA9 MPU_DATA10 MPU_DATA11 MPU_DATA12 MPU_DATA13 MPU_DATA14 MPU_DATA15 MPU_DSN MPU_DTN MPU_INTN MPU_MPCLK MPU_MPMODE MPU_RWN NC NC NC PLL_GND Note: NC refers to no connect. Do not connect pins so designated. 92 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued) Signal Name PLL_GNDD Pin Signal Name NC Pin C29 Signal Name RXD4N Pin AE3 Signal Name RXDATAA11 Pin P31 E4 B6 E3 D5 C5 D7 C25 D25 A25 B25 B24 C24 D23 E23 E34 D31 E30 B30 E28 D28 E27 D26 A26 E24 D24 A24 E32 E33 B31 C31 C30 D30 D29 E29 B29 PLL_VDDD2 PLL_VDDD2 PLLFB PLLREF PMRST NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B28 C28 B27 C27 B26 C26 G4 D15 B5 C7 W31 W32 V34 AL33 AL32 AP20 AL19 AN19 AL8 AP7 W33 AL34 AN20 AM8 V4 V5 AG1 AG2 AF1 AF2 AF3 AF4 AE1 AE2 RXD4P RXD5N RXD5P RXD6N RXD6P RXD7N RXD7P RXD8N RXD8P RXD9N_RXCLKDN RXD9P_RXCLKDP RXD10N_RXDDN AE4 AD1 AD2 AD3 AD4 AC2 AC3 AC4 AC5 AB1 AB2 AB3 AB4 AA1 AA2 AA3 AA4 Y2 Y3 W2 W3 W4 W5 T33 T32 R35 R34 R33 R32 R31 P35 P34 P33 P32 RXDATAA12 RXDATAA13 RXDATAA14 RXDATAA15 RXDATAB0 RXDATAB1 RXDATAB2 RXDATAB3 RXDATAB4 RXDATAB5 RXDATAB6 RXDATAB7 RXDATAB8 RXDATAB9 RXDATAB10 RXDATAB11 RXDATAB12 RXDATAB13 RXDATAB14 RXDATAB15 RXDATAC0 RXDATAC1 RXDATAC2 RXDATAC3 RXDATAC4 RXDATAC5 RXDATAC6 RXDATAC7 RXDATAC8 RXDATAC9 RXDATAC10 RXDATAC11 RXDATAC12 RXDATAC13 N34 N33 N32 N31 AJ34 AH31 AH32 AH33 AH34 AG31 AG32 AG33 AG34 AG35 AF31 AF32 AF33 AF34 AF35 AE32 AP22 AN22 AM22 AL22 AP23 AN23 AM23 AL23 AR24 AP24 AN24 AM24 AL24 AR25 RSTN RXADDRA0 RXADDRA1 RXADDRA2 RXADDRB0 RXADDRB1 RXADDRC0 RXADDRC1 RXADDRC2 RXADDRD0 RXADDRD1 RXCLKA RXCLKB RXCLKC RXCLKD RXCLKN _RXDAN RXCLKP _RXDAP RXD10P_RXDDP RXD11N_RXCLKCN RXD11P_RXCLKCP RXD12N_RXDCN RXD12P_RXDCP RXD13N_RXCLKBN RXD13P_RXCLKBP RXD14N_RXCLKAN RXD14P_RXCLKAP RXD15N_RXDBN RXD15P_RXDBP RXDATAA0 RXDATAA1 RXDATAA2 RXDATAA3 RXDATAA4 RXDATAA5 RXDATAA6 RXDATAA7 RXDATAA8 RXDATAA9 RXDATAA10 RXD0N RXD0P RXD1N RXD1P RXD2N RXD2P RXD3N RXD3P Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 93 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued) Signal Name RXDATAC14 RXDATAC15 RXDATAD0 RXDATAD1 RXDATAD2 RXDATAD3 RXDATAD4 RXDATAD5 RXDATAD6 RXDATAD7 RXDATAD8 RXDATAD9 RXDATAD10 RXDATAD11 RXDATAD12 RXDATAD13 RXDATAD14 RXDATAD15 RXENBA RXENBB RXENBC RXENBD RXEOPA RXEOPB RXEOPC RXEOPD RXERRA RXERRB RXERRC RXERRD RXPPAA RXPPAB RXPPAC RXPPAD RXPRTYA Pin AP25 AN25 AL10 AM10 AN10 AP10 AR10 AM11 AN11 AP11 AR11 AL12 AM12 AN12 AP12 AR12 AL13 AM13 U34 AK34 AN21 AM9 U32 AJ31 AM21 AN9 V32 AK32 AR21 AP8 V33 AK33 AP21 AL9 T34 Signal Name RXPRTYB RXPRTYC RXPRTYD RXREF RXSOPA RXSOPB RXSOPC RXSOPD RXSPAA RXSPAB RXSPAC RXSPAD RXSZA RXSZB RXSZC RXSZD RXTOHCLKA RXTOHCLKB RXTOHCLKC RXTOHCLKD RXTOHDA RXTOHDB RXTOHDC RXTOHDD RXTOHFA RXTOHFB RXTOHFC RXTOHFD NC NC NC NC NC NC NC Pin AJ33 AR22 AR9 AK3 U31 AJ32 AL21 AP9 F31 F32 F33 F34 W35 AK31 AM20 AN8 AK5 AL4 AL6 AL7 AL2 AM5 AM6 AN7 AK4 AL3 AN5 AP6 D18 B18 C18 E18 C17 B17 E17 Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC TCLK TDI TDO TMS TRSTN TXADDRA0 TXADDRA1 TXADDRA2 TXADDRB0 TXADDRB1 TXADDRC0 TXADDRC1 TXADDRC2 TXADDRD0 TXADDRD1 TXCLKA TXCLKB TXCLKC Pin D17 B23 C23 E22 D22 C21 E21 A21 B21 C20 D20 B19 B20 E19 D19 A19 C19 F2 G5 G2 F4 G3 G32 G33 U33 W34 Y34 AM31 AN31 AM19 AM7 AP5 G34 Y33 AP31 Signal Name TXCLKD TXCLKN TXCLKP TXCLKQN TXCLKQP TXD0N_TXDDN TXD0P_TXDDP TXD1N_TXDCN TXD1P_TXDCP TXD2N_TXDBN TXD2P_TXDBP TXD3N_TXDAN TXD3P_TXDAP Pin AP19 U5 U4 J5 H2 U2 T2 T3 T4 R2 R3 R5 R4 P1 P2 P3 P5 N2 N3 N4 N5 M1 M2 M3 M4 L1 L2 L3 L4 K1 K2 K3 K4 J1 J2 TXD4N TXD4P TXD5N TXD5P TXD6N TXD6P TXD7N TXD7P TXD8N TXD8P TXD9N TXD9P TXD10N TXD10P TXD11N TXD11P TXD12N TXD12P TXD13N TXD13P TXD14N TXD14P Note: NC refers to no connect. Do not connect pins so designated. 94 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued) Signal Name TXD15N TXD15P TXDATAA0 TXDATAA1 TXDATAA2 TXDATAA3 TXDATAA4 TXDATAA5 TXDATAA6 TXDATAA7 TXDATAA8 TXDATAA9 TXDATAA10 TXDATAA11 TXDATAA12 TXDATAA13 TXDATAA14 TXDATAA15 TXDATAB0 TXDATAB1 TXDATAB2 TXDATAB3 TXDATAB4 TXDATAB5 TXDATAB6 TXDATAB7 TXDATAB8 TXDATAB9 TXDATAB10 TXDATAB11 TXDATAB12 TXDATAB13 TXDATAB14 TXDATAB15 TXDATAC0 Pin J3 J4 M35 M34 M33 M32 M31 L35 L34 L33 L32 K35 K34 K33 K32 K31 J35 J34 AE33 AE34 AE35 AD31 AD32 AD33 AD34 AD35 AC31 AC32 AC33 AC34 AB32 AB31 AB33 AB34 AM25 Signal Name TXDATAC1 TXDATAC2 TXDATAC3 TXDATAC4 TXDATAC5 TXDATAC6 TXDATAC7 TXDATAC8 TXDATAC9 TXDATAC10 TXDATAC11 TXDATAC12 TXDATAC13 TXDATAC14 TXDATAC15 TXDATAD0 TXDATAD1 TXDATAD2 TXDATAD3 TXDATAD4 TXDATAD5 TXDATAD6 TXDATAD7 TXDATAD8 TXDATAD9 TXDATAD10 TXDATAD11 TXDATAD12 TXDATAD13 TXDATAD14 TXDATAD15 TXENBA TXENBB TXENBC TXENBD Pin AR26 AP26 AN26 AM26 AL26 AR27 AP27 AN27 AM27 AL27 AP28 AN28 AM28 AL28 AP29 AN13 AP13 AM14 AL14 AN14 AP14 AR14 AM15 AL15 AN15 AP15 AR15 AM16 AN16 AP16 AP17 H34 AA33 AP30 AR17 Signal Name TXEOPA TXEOPB TXEOPC TXEOPD TXERRA TXERRB TXERRC TXERRD TXFSYNCN TXFSYNCP TXPPAA TXPPAB TXPPAC TXPPAD TXPRTYA TXPRTYB TXPRTYC TXPRTYD TXSOPA TXSOPB TXSOPC TXSOPD TXSPAA TXSPAB TXSPAC TXSPAD TXSZA TXSZB TXSZC TXSZD TXTOHCLK TXTOHD TXTOHF VDDD VDDD Pin J31 AA31 AL29 AN17 H32 AA35 AM30 AM18 U1 U3 H33 AA34 AN30 AP18 J33 AB35 AN29 AM17 J32 AA32 AM29 AL17 G31 AK2 AJ5 AJ4 H31 Y32 AL30 AN18 AJ2 AJ3 AH5 A1 A2 Signal Name VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD Pin A17 A18 A34 A35 B1 B2 B34 B35 C3 C33 E11 E25 K5 L5 L31 M5 P4 R1 U35 V1 V2 V35 W1 AB5 AD5 AE5 AE31 AF5 AL11 AL18 AL25 AN3 AN33 AP1 AP2 Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 95 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Information (continued) 600-Pin LBGA Pin Assignments (continued) Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued) Signal Name VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 Pin AP34 AP35 AR1 AR2 AR18 AR19 AR34 AR35 A5 A6 A30 A31 D4 D32 E1 E5 E16 E20 E31 E35 F1 F35 T5 T31 Y5 Y31 AK1 AK35 AL1 AL5 AL16 AL20 AL31 AL35 AM4 Signal Name VDDD2 VDDD2 VDDD2 VDDD2 VDDD2 Pin AM32 AR5 AR6 AR30 AR31 Note: NC refers to no connect. Do not connect pins so designated. 96 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. All LVPECL buffers are differential. LVPECL inputs with an _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage (3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL I/O are given in LVPECL I/O Termination and Load Specifications on page 178. Table 7. Pin Descriptions--Line Interface Signals Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally disabled whenever the core registers are properly provisioned. The unused inputs can be considered to be NC (no-connect). 600 V5 V4 792 Y38 W38 Symbol RXCLKP_ RXDAP RXCLKN_ RXDAN Type I/O* Name/Description LVPECL I Receive Line Clock (STS-48/STM-16)/Receive Data Input Channel A. In STS-48/STM-16 mode, the pins function as receive line clock. This 155 MHz clock comes from an external clock and data recovery circuit. This clock is used to clock in the RXD[15:0] data inputs. This buffer is internally disabled when not in STS-48/ STM-16 mode. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive data input channel A. LVPECL I Receive Data Inputs (STS-48/STM-16). In STS-48/STM-16 mode, the pins function as receive line data inputs [8:0]. The remaining line data inputs [15:9] (described below and on the next page) are LVPECL multiplexed for use in the STS-3/STM-1 or STS-12/STM-4 modes. All 32 differential data input pins (RXD[15:0]P/N) are used when in STS-48/STM-16 mode. LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL I Receive Data Input [9]/Receive Line Clock Channel D. In STS48/STM-16 mode, the pins function as receive data input [9]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive line clock channel D. This 155/622 MHz clock is used to clock in the RXDD data inputs. Receive Data Input [10]/Receive Data Input Channel D. In STS48/STM-16 mode, the pins function as receive data input [10]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive data input channel D. AG2 AG1 AF2 AF1 AF4 AF3 AE2 AE1 AE4 AE3 AD2 AD1 AD4 AD3 AC3 AC2 AC5 AC4 AB2 AB1 AF34 AF35 AF38 AF39 AF36 AF37 AE37 AE38 AE35 AE36 AD37 AD38 AD35 AD36 AC36 AC37 AC34 AC35 AB34 AB35 RXD0P RXD0N RXD1P RXD1N RXD2P RXD2N RXD3P RXD3N RXD4P RXD4N RXD5P RXD5N RXD6P RXD6N RXD7P RXD7N RXD8P RXD8N RXD9P_ RXCLKDP RXD9N_ RXCLKDN RXD10P_ RXDDP RXD10N_ RXDDN AB4 AB3 AC38 AC39 LVPECL I * IU indicates a 100 k internal pull-up. ID indicates a 50 k internal pull-down. This buffer is internally disabled when the input is not active. Agere Systems Inc. 97 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage (3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL I/O are given in LVPECL I/O Termination and Load Specifications on page 178. Table 7. Pin Descriptions--Line Interface Signals (continued) 600 AA2 AA1 792 AB38 AB39 Symbol RXD11P_ RXCLKCP RXD11N_ RXCLKCN Type LVPECL I/O* I Name/Description Receive Data Input [11]/Receive Line Clock Channel C. In STS-48/STM-16 mode, the pins function as receive data input [11]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive line clock channel C. This 155/622 MHz clock is used to clock in the RXDC data inputs. AA4 AA3 AB36 AB37 RXD12P_ RXDCP RXD12N_ RXDCN RXD13P_ RXCLKBP RXD13N_ RXCLKBN LVPECL I LVPECL I Receive Data Input [12]/Receive Data Input Channel C. In STS-48/STM-16 mode, the pins function as receive data input [12]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive data input channel C. Receive Data Input [13]/Receive Line Clock Channel B. In STS-48/STM-16 mode, the pins function as receive data input [13]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive line clock channel B. This 155/622 MHz clock is used to clock in the RXDB data inputs. W3 W2 Y36 Y37 RXD14P_ RXCLKAP RXD14N_ RXCLKAN LVPECL I Receive Data Input [14]/Receive Line Clock Channel A. In STS-48/STM-16 mode, the pins function as receive data input [14]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive line clock channel A. This 155/622 MHz clock is used to clock in the RXDA data inputs. W5 W4 AA36 AA37 RXD15P_ RXDBP RXD15N_ RXDBN CLKDIV 3.3 V (5 V tolerant) IU LVPECL I Receive Data Input [15]/Receive Data Input Channel B. In STS-48/STM-16 mode, the pins function as receive data input [15]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as receive data input channel B. Clock Division. This pin controls a divider in the line transmit block to create a 77.76 MHz clock from either the 155.52 MHz STS-3/STM-1 or STS-48/STM-16 transmit line clock, or the 622.08 MHz STS-12/STM-4 transmit line clock. CLKDIV = 1 for STS-12/STM-4 (divide by 8). CLKDIV = 0 for STS-3/STM-1 and STS-48 /STM-16 (divide by 2). * IU indicates a 100 k internal pull-up. ID indicates a 50 k internal pull-down. This buffer is internally disabled when the input is not active. Y3 Y2 AA35 Y35 H4 L37 98 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage (3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL I/O are given in LVPECL I/O Termination and Load Specifications on page 178. Table 7. Pin Descriptions--Line Interface Signals (continued) 600 AG3 AG4 792 AG37 AG36 Symbol ECLREFLO ECLREFHI Type -- -- I/O* Name/Description -- Reference Voltage for LVPECL I/O Buffers. ECLREFLO and -- ECLREFHI provide the reference for the output level of the LVPECL output buffers. The standard value for ECL termination voltage is VDD - 2 V and the standard termination resistance is 50 . All ECL output buffers on the chip must have the same termination voltage and termination resistance as ECLREFLO and ECLREFHI. ECLREFLO and ECLREFHI must have separate termination. Thevenin termination of 50 into VDDD - 2 V (this may be obtained from a passive voltage divider of a 130 resistor connected from VDDD to one end of an 82 resistor, the other end of which is connected to GNDD) is recommended for all ECL output buffers and ECLREFLO and ECLREFHI. I Transmit Line Clock. When in STS-48/STM-16 or quad STS-3/ STM-1 mode, this clock is a 155.52 MHz input and clocks out TXD[15:0]. When in STS-12/STM-4 mode, it is a 622.08 MHz input and clocks out TXD[A--D]. U4 U5 V38 V39 TXCLKP TXCLKN LVPECL U3 U1 W37 W36 TXFSYNCP TXFSYNCN LVPECL ID I U Transmit Line 8 kHz Frame Sync. This input is the external 8 kHz transmit line frame sync. Driving this input is optional. If undriven from an external source, these pins must be no connects. When this input is used, it must be (1) synchronized to TXCLKP/N, and (2) at least one TXCLKP/N cycle wide, up to a maximum of 1 frame period minus two TXCLKP/N cycles wide. * IU indicates a 100 k internal pull-up. ID indicates a 50 k internal pull-down. This buffer is internally disabled when the input is not active. Agere Systems Inc. 99 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage (3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL I/O are given in LVPECL I/O Termination and Load Specifications on page 178. Table 7. Pin Descriptions--Line Interface Signals (continued) 600 T2 U2 792 V36 V37 Symbol TXD0P_ TXDDP TXD0N_ TXDDN Type LVPECL I/O* O Name/Description Transmit Data Output [0]/Transmit Data Output Channel D. In STS-48/STM-16 mode, the pins function as transmit data output [0]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as transmit data output channel D. All 32 pins are used when in STS-48/STM-16 mode. T4 T3 V34 V35 TXD1P_ TXDCP TXD1N_ TXDCN LVPECL O Transmit Data Output [1]/Transmit Data Output Channel C. In STS-48/STM-16 mode, the pins function as transmit data output [1]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as transmit data output channel C. All 32 pins are used when in STS-48/STM-16 mode. R3 R2 U38 U39 TXD2P_ TXDBP TXD2N_ TXDBN LVPECL O Transmit Data Output [2]/Transmit Data Output Channel B. In STS-48/STM-16 mode, the pins function as transmit data output [2]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as transmit data output channel B. All 32 pins are used when in STS-48/STM-16 mode. R4 R5 U36 U37 TXD3P_ TXDAP TXD3N_ TXDAN LVPECL O Transmit Data Output [3]/Transmit Data Output Channel A. In STS-48/STM-16 mode, the pins function as transmit data output [3]. In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as transmit data output channel A. All 32 pins are used when in STS-48/STM-16 mode. * indicates a 100 k internal pull-up. indicates a 50 k internal pull-down. This buffer is internally disabled when the input is not active. IU ID 100 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage (3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL I/O are given in LVPECL I/O Termination and Load Specifications on page 178. Table 7. Pin Descriptions--Line Interface Signals (continued) 600 H2 J5 792 M35 M36 Symbol TXCLKQP TXCLKQN Type LVPECL I/O* O Name/Description Transmit Line Clock. This 155.52 MHz clock is used in the OC-48 mode for forward-directional timing with the 155 Mbits/s 16-bit parallel-to-2.5 Gbits/s serial MUX to clock out the data. In OC-48 forward clock mode, TXD[15:0]P/N transitions at the rising edge of TXCLKQP. For an OC-48 contraclocking interface with the 155 Mbits/s parallel-to-2.5 Gbits/s serial MUX, this clock is not used. In the contraclocking mode, the SONET PLL must be active (see MPU register MPU_LI_MODER, address 0x0021, bit 5. P2 P1 P5 P3 N3 N2 N5 N4 M2 M1 M4 M3 L2 L1 L4 L3 K2 K1 K4 K3 J2 J1 J4 J3 U U34 U35 T37 T38 T35 T36 R37 R38 P38 P39 R35 R36 P36 P37 P34 P35 N38 N39 N36 N37 N34 N35 M37 M38 TXD4P TXD4N TXD5P TXD5N TXD6P TXD6N TXD7P TXD7N TXD8P TXD8N TXD9P TXD9N TXD10P TXD10N TXD11P TXD11N TXD12P TXD12N TXD13P TXD13N TXD14P TXD14N TXD15P TXD15N LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL O Transmit Data Outputs (STS-48/STM-16). All 32 differential data input pins (TXD[15:0]P/N) are used when in STS-48 mode. * I indicates a 100 k internal pull-up. ID indicates a 50 k internal pull-down. This buffer is internally disabled when the input is not active. Agere Systems Inc. 101 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 8. Pin Descriptions--TOH Interface Signals 600 AK3 792 AK34 Symbol RXREF Type 3.3 V I/O* O Name/Description Receive Line Frame. This output provides the receive 8 kHz frame reference for external timing needs. RXREF is derived from one of the received line clocks (user-selectable). It is a 50% duty cycle clock when MARS2G5 P-Pro is in frame. This signal may be used to implement line timing on a SONET ring. When not provisioned, this signal must not be used. RXREF is valid only when the SONET framer is in frame. Upon LOC, RXREF is not present. Upon LOF, RXREF is present but is free-running. Because jitter may be present on this signal when the device goes into and out of an LOF state, it should not be used as a reference for TXFSYNCP/N. Receive TOH Interface Clock. This clock is nominally a 5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4), or a 20.736 MHz (STS-48/STM-16) clock which provides timing for circuitry that receives and externally processes the receive transport overhead bytes. These clocks are frequency shifted as shown in Figure 32, STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing on page 206 and Figure 33, STS-3/STM-1 Receive TOAC Interface Timing on page 207. Receive TOH Interface Data. This 5.184 Mbits/s or 20.736 Mbits/s signal contains all the receive transport overhead bytes (A1, A2, J0/Z0, B1, E1, F1, D1--D3, H1--H3, K1, K2, D4--D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal can be used by external circuitry to process the TOH bytes. RXTOHD is updated on the falling edge of RXTOHCLK. Receive TOH Interface Frame. This 8 kHz framing signal is used to locate the individual receive transport overhead bits in the RXTOHD bit stream. RXTOHF[D--A] is only high while bit 1 (MSB) of the first framing byte (A1 during parity time in first byte) is present on the RXTOHD output. RXTOHF[D--A] is updated on the falling edge of RXTOHCLK. AL7 AL6 AL4 AK5 AR30 AR31 AM34 AL35 RXTOHCLKD RXTOHCLKC RXTOHCLKB RXTOHCLKA 3.3 V O AN7 AM6 AM5 AL2 AU30 AT31 AP32 AL34 RXTOHDD RXTOHDC RXTOHDB RXTOHDA 3.3 V O AP6 AN5 AL3 AK4 AP30 AR32 AM35 AL36 RXTOHFD RXTOHFC RXTOHFB RXTOHFA 3.3 V O * IU indicates a 100 k internal pull-up. ID indicates a 50 k internal pull-down. Note: [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 102 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 8. Pin Descriptions--TOH Interface Signals (continued) 600 AJ2 792 AJ37 Symbol TXTOHCLK Type 3.3 V I/O* O Name/Description Transmit TOH Interface Clock. This clock is nominally a 5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4), or a 20.736 MHz (STS-48/STM-16) clock which provides timing for circuitry that externally generates and transmits the transmit transport overhead bytes for inclusion in the transmit data stream. This clock is frequency shifted as shown in Figure 31, STS-3/ STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing on page 206. Transmit TOH Interface Data. This 5.184 Mbits/s or 20.736 Mbits/s signal contains all the transmit transport overhead bytes (A1, A2, J0/Z0, E1, F1, D1--D3, D4--D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal is generated by external circuitry for custom TOH byte definitions. TXTOHD is sampled on the rising edge of TXTOHCK. The data format is different from MARS2G5 P-ProLT. Transmit TOH Interface Frame. This 8 kHz framing signal is used to align the individual transmit transport overhead bits in the TXTOHD bit stream. TXTOHF is only high while bit 1 (MSB) of the first framing byte (A1 during parity time in first byte) is expected on the TXTOHD input. TXTOHF is updated on the falling edge of TXTOHCK. This pin function is different from MARS2G5 P-ProLT. AJ3 AJ36 TXTOHD 3.3 V (5 V tolerant) IU AH5 AH35 TXTOHF 3.3 V O * IU indicates a 100 k internal pull-up. ID indicates a 50 k internal pull-down. Note: [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 103 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 U33 G33 G32 Y34 W34 AM19 AN31 AM31 AP5 AM7 792 Y5 K3 L5 AB6 AB1 AU19 AP8 AR7 AP31 AT30 Symbol TXADDRA2 TXADDRA1 TXADDRA0 TXADDRB1 TXADDRB0 TXADDRC2 TXADDRC1 TXADDRC0 TXADDRD1 TXADDRD0 Type 3.3 V (5 V tolerant) I/O* IU Name/Description Transmit Address. The TXADDR is driven by the UTOPIA master to poll and select the appropriate PHY channel of MARS2G5 P-Pro to transmit data. Note: The PHY address (0x00 to 0x1E) for each of the four channels in MARS2G5 P-Pro is configured via software provisioning. TXADDRA[2:0] concatenated with TXDATAA[7:6] forms a 5-bit address bus. TXADDRB[1:0] concatenated with TXDATAB[7:5] forms a 5-bit address bus. TXADDRC[2:0] concatenated with TXDATAC[7:6] forms a 5-bit address bus. TXADDRD[1:0] concatenated with TXDATAD[7:5] forms a 5-bit address bus. 3.3 V (5 V tolerant) IU Transmit Data Channel A. Used to transport data into the UTOPIA PHY Tx block. TXDATAA is only valid when TXENBA is asserted, and is sampled on the rising edge of TXCLKA. Note: TXDATAA is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, TXDATAA[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16), and TXDATAB[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0). J34 J35 K31 K32 K33 K34 K35 L32 L33 L34 L35 M31 M32 M33 M34 M35 M2 P6 N4 N3 P5 N2 P4 P3 N1 R5 P2 R4 R3 P1 T5 R2 TXDATAA15 TXDATAA14 TXDATAA13 TXDATAA12 TXDATAA11 TXDATAA10 TXDATAA9 TXDATAA8 TXDATAA7 TXDATAA6 TXDATAA5 TXDATAA4 TXDATAA3 TXDATAA2 TXDATAA1 TXDATAA0 * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 104 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AB34 AB33 AB31 AB32 AC34 AC33 AC32 AC31 AD35 AD34 AD33 AD32 AD31 AE35 AE34 AE33 AP29 AL28 AM28 AN28 AP28 AL27 AM27 AN27 AP27 AR27 AL26 AM26 AN26 AP26 AR26 AM25 792 AC3 AC2 AD4 AD5 AD3 AD2 AE2 AE3 AE4 AE5 AF1 AF2 AF3 AF4 AF5 AF6 AT10 AU10 AR11 AT11 AU11 AV11 AR12 AT12 AU12 AV12 AT13 AP13 AR13 AU13 AV13 AU14 Symbol TXDATAB15 TXDATAB14 TXDATAB13 TXDATAB12 TXDATAB11 TXDATAB10 TXDATAB9 TXDATAB8 TXDATAB7 TXDATAB6 TXDATAB5 TXDATAB4 TXDATAB3 TXDATAB2 TXDATAB1 TXDATAB0 TXDATAC15 TXDATAC14 TXDATAC13 TXDATAC12 TXDATAC11 TXDATAC10 TXDATAC9 TXDATAC8 TXDATAC7 TXDATAC6 TXDATAC5 TXDATAC4 TXDATAC3 TXDATAC2 TXDATAC1 TXDATAC0 Type 3.3 V (5 V tolerant) I/O* I U Name/Description Transmit Data Channel B. Used to transport data into the UTOPIA PHY Tx block. TXDATAB is only valid when TXENBB is asserted (TXENBA for 32-bit mode), and is sampled on the rising edge of TXCLKB (TXCLKA for 32-bit mode). Note: TXDATAB is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, TXDATAB[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0), and TXDATAA[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16). 3.3 V (5 V tolerant) IU Transmit Data Channel C. Used to transport data into the UTOPIA PHY Tx block. TXDATAC is only valid when TXENBC is asserted, and is sampled on the rising edge of TXCLKC. Note: TXDATAC is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, TXDATAC[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16), and TXDATAD[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0). * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 105 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 792 Symbol Type I/O* I U Name/Description Transmit Data Channel D. Used to transport data into the UTOPIA PHY Tx block. TXDATAD is only valid when TXENBD is asserted, and is sampled on the rising edge of TXCLKD (TXCLKA for 32-bit mode). Note: TXDATAD is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, TXDATAD[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0), and TXDATAC[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16). AP17 AT21 AP16 AR21 AN16 AV22 AM16 AU22 AR15 AW23 AP15 AT22 AN15 AR22 AL15 AV23 AM15 AP22 AR14 AU23 AP14 AT23 AN14 AV24 AL14 AR23 AM14 AU24 AP13 AP23 AN13 AT24 AM17 AW22 AN29 AR10 AB35 AC4 N5 J33 3.3 V TXDATAD15 TXDATAD14 (5 V tolerant) TXDATAD13 TXDATAD12 TXDATAD11 TXDATAD10 TXDATAD9 TXDATAD8 TXDATAD7 TXDATAD6 TXDATAD5 TXDATAD4 TXDATAD3 TXDATAD2 TXDATAD1 TXDATAD0 TXPRTYD TXPRTYC TXPRTYB TXPRTYA 3.3 V (5 V tolerant) IU Transmit Parity. This signal indicates the parity on the TXDATA[D--A][15:0] bus. A parity error raises an alarm but does not cause the cell/packet to be dropped. Odd or even parity may be provisioned through a software register. TXPRTY[D--A] is considered valid only when TXENB[D--A] is asserted, and is sampled on the rising edge of TXCLK[D--A]. In 32-bit mode, the TXPRTYA and TXPRTYC parity pin of port A and port C, respectively, indicates the parity for the entire 32-bit data input. AL17 AM29 AA32 J32 AU21 AP10 AC5 M3 TXSOPD TXSOPC TXSOPB TXSOPA 3.3 V (5 V tolerant) IU Transmit Start of Packet/Cell. In ATM mode, the TXSOP[D--A] signal marks the start of a cell on the TXDATA[D--A][15:0] bus. When TXSOP[D--A] is active, the first word of the cell is present on the TXDATA[D--A][15:0] bus. An alarm will be raised if TXSOP[D--A] goes high before the previous cell was completely sent. In packet modes, the TXSOP[D--A] signal marks the start of a packet on the TXDATA[D--A][15:0] bus. When TXSOP[D--A] is active, the first word of the packet is present on the TXDATA[D-- A][15:0] bus. TXSOP[D--A] is considered valid only when TXENB[D--A] is asserted, and is sampled on the rising edge of TXCLK[D--A]. In 32-bit mode, only the TXSOPA and TXSOPC pin of port A and port C, respectively, is used to indicate a start of packet/cell for the 32-bit data input. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 106 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AP18 AN30 AA34 H33 792 AT20 AR9 AB2 M4 Symbol TXPPAD TXPPAC TXPPAB TXPPAA Type 3.3 V I/O* O Name/Description Transmit Cell/Polled Packet Available. This signal indicates when the transmit FIFO is below a provisionable level. If the FIFO is empty or more than the provisioned space is available in the FIFO, TXPPA[D--A] is set active. In ATM mode, asserting TXPPA[D--A] means that FIFO has room for one entire ATM cell. TXPPA[D--A] should go low four cycles before the end of cell if the selected channel does not have space available for one entire cell. In packet modes, asserting TXPPA[D--A] means that the FIFO has room for several words. If TXPPA[D--A] is inactive, it indicates that the FIFO is full or that less than the provisioned amount of space available. TXPPA[D--A] is updated on the rising edge of TXCLK[D--A]. In 32-bit mode, only the TXPPA and TXPPC pin of port A and port C, respectively, is used to indicate the packet/cell available status. AP19 AP31 Y33 G34 AT19 AR8 AB5 L4 TXCLKD TXCLKC TXCLKB TXCLKA 3.3 V (5 V tolerant) IU Transmit Clock. This clock is used to write cells or packets into the transmit FIFO. TXCLK[D--A] can operate at speeds from dc to 104 MHz. This clock is required to access channels, i.e., to access channel 2 of slice C, this clock must be provided to slice C (see Table 750). In 32-bit mode, both TXCLKA and TXCLKB are used and required to clock data into port A. Both TXCLKC and TXCLKD are used and required to clock data into port C. AR17 AP30 AA33 H34 AV20 AT9 AC1 N6 TXENBD TXENBC TXENBB TXENBA 3.3 V (5 V tolerant) IU Transmit Data Enable (Active-Low). This signal is used to transfer data on the TXDATA[D--A][15:0] bus into the transmit FIFOs. If TXENB[D--A] is high, no operation is performed. If TXENB[D--A] is low, a write occurs. TXENB[D--A] is sampled on the rising edge of TXCLK[D--A]. TXENB[D--A] has the same meaning as data valid. In 32-bit mode, only the TXENBA and TXENBC input pin of port A and port C, respectively, is used to enable the transfer of data. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 107 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AN18 AL30 Y32 H31 792 AU20 AT8 AB4 M5 Symbol TXSZD TXSZC TXSZB TXSZA Type 3.3 V (5 V tolerant) I/O* I U Name/Description Transmit Size. This signal defines the valid bytes transmitted and their packing within (1) TXDATA[D--A][15:0] for 16-bit modes, and (2) TXDATAA[15:0] and TXDATAB[15:0] for the 32-bit mode. The meaning of these bits may be inverted through the appropriate UT control register TXSZ/RXSZ mode. In 8-bit modes, TXSZ[D--A] are unused. For 16-bit mode, TXSZ[D--A] = 0 defines the MSByte of TXDATA[D--A][15:0], i.e., TXDATA[D--A][15:8], to be the last byte of the packet transmitted when using the default configuration. TXSZ[D--A] = 1 defines the LSByte of TXDATA[D--A][15:0], i.e., TXDATA[D--A][7:0], to be the last byte of the packet transmitted when using the default configuration. For 32-bit mode, TXSZA and TXSZB are combined to define four states of the transmitted data stream on ports A and B. Ports C and D are controlled by TXSZC and TXSZD. The following states are assigned by TXSZA and TXSZB (or TXSZC and TXSZD) when TXEOPA (or TXEOPC) is asserted when using the default configuration. TXDATAA TXDATAA[15:8] TXDATAA[7:0] TXSZA TXSZB DATA[31:24] DATA[23:16] TXDATAB TXDATAB[15:8] TXDATAB[7:0] DATA[15:8] DATA[7:0] 0 0 1 1 0 1 0 1 Valid Valid Valid Valid Not Valid Valid Valid Valid Not Valid Not Valid Valid Valid Not Valid Not Valid Not Valid Valid There is no byte swapping and the data bytes are packed into the upper transmitted bytes first. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 108 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AN17 AL29 AA31 J31 792 AV21 AU9 AC6 L2 Symbol TXEOPD TXEOPC TXEOPB TXEOPA Type 3.3 V (5 V tolerant) I/O* I U Name/Description Transmit End of Packet. This signal indicates that the last word of a packet is on the TXDATA[D--A][15:0] bus. TXEOP[D--A] is valid only when TXENB[D--A] is asserted, and is sampled on the rising edge of TXCLK[D--A]. In 32-bit mode, only the TXEOPA and TXEOPC input pin of port A and port C, respectively, is used to indicate the end of the incoming packet. AM18 AM30 AA35 H32 AR20 AP9 AB3 L3 TXERRD TXERRC TXERRB TXERRA 3.3 V (5 V tolerant) IU Transmit Error. TXERR[D--A] is only used in packet modes, and indicates that the current packet is to be aborted and discarded, if possible. TXERR[D--A] is only valid when TXEOP[D--A] and TXENB[D--A] are asserted, and is sampled on the rising edge of TXCLK[D--A]. In 32-bit mode, only the TXERRA and TXERRC input pin of port A and port C, respectively, is used to indicate an error on the incoming packet. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 109 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 V34 W32 W31 AL32 AL33 AN19 AL19 AP20 AP7 AL8 N31 N32 N33 N34 P31 P32 P33 P34 P35 R31 R32 R33 R34 R35 T32 T33 AE32 AF35 AF34 AF33 AF32 AF31 AG35 AG34 AG33 AG32 AG31 AH34 AH33 AH32 AH31 AJ34 792 AA1 AA2 AA4 AN5 AM6 AR19 AV19 AP18 AR29 AT29 T4 U6 T3 U5 T2 U4 V6 U3 V5 U2 V4 U1 V3 V2 W5 W4 AG1 AG2 AG3 AG4 AG6 AG5 AH2 AH3 AH4 AH5 AJ2 AJ3 AJ4 AJ5 AK3 AK4 Symbol RXADDRA2 RXADDRA1 RXADDRA0 RXADDRB1 RXADDRB0 RXADDRC2 RXADDRC1 RXADDRC0 RXADDRD1 RXADDRD0 RXDATAA15 RXDATAA14 RXDATAA13 RXDATAA12 RXDATAA11 RXDATAA10 RXDATAA9 RXDATAA8 RXDATAA7 RXDATAA6 RXDATAA5 RXDATAA4 RXDATAA3 RXDATAA2 RXDATAA1 RXDATAA0 RXDATAB15 RXDATAB14 RXDATAB13 RXDATAB12 RXDATAB11 RXDATAB10 RXDATAB9 RXDATAB8 RXDATAB7 RXDATAB6 RXDATAB5 RXDATAB4 RXDATAB3 RXDATAB2 RXDATAB1 RXDATAB0 Type 3.3 V (5 V tolerant) I/O* I U Name/Description Receive Address. Receive address is driven in MPHY mode to poll and select the appropriate MPHY channel. Note: The address for each channel is configured by the microprocessor. RXADDRA[2:0] concatenated with TXDATAA[1:0] forms a 5-bit address bus. RXADDRB[1:0] concatenated with TXDATAB[2:0] forms a 5-bit address bus. RXADDRC[2:0] concatenated with TXDATAC[1:0] forms a 5-bit address bus. RXADDRD[1:0] concatenated with TXDATAD[2:0] forms a 5-bit address bus. 3.3 V O Receive Data Channel A. Used to transport data out of the UTOPIA PHY Rx block. RXDATAA[15:0] is only valid when RXENBA is asserted, and is updated on the rising edge of RXCLKA. Note: RXDATAA[15:0] is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, RXDATAA[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16), and RXDATAB[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0). 3.3 V O Receive Data Channel B. Used to transport data out of the UTOPIA PHY Rx block. RXDATAB[15:0] is only valid when RXENBB is asserted, and is updated on the rising edge of RXCLKB. Note: RXDATAB[15:0] is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, RXDATAB[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0), and RXDATAA[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16). * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 110 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 792 Symbol Type 3.3 V I/O* O Name/Description Receive Data Channel C. Used to transport data out of the UTOPIA PHY Rx block. RXDATAC[15:0] is only valid when RXENBC is asserted, and is updated on the rising edge of RXCLKC. Note: RXDATAC[15:0] is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, RXDATAC[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16), and RXDATAD[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0). AN25 AR14 RXDATAC15 AP25 AP14 RXDATAC14 AR25 AT14 RXDATAC13 AL24 AV14 RXDATAC12 AM24 AW14 RXDATAC11 AN24 AV15 RXDATAC10 AP24 AT15 RXDATAC9 AR24 AR15 RXDATAC8 AL23 AU15 RXDATAC7 AM23 AV16 RXDATAC6 AN23 AU16 RXDATAC5 AP23 AT16 RXDATAC4 AL22 AR16 RXDATAC3 AM22 AV17 RXDATAC2 AN22 AW17 RXDATAC1 AP22 AU17 RXDATAC0 AM13 AV25 RXDATAD15 AL13 AR24 RXDATAD14 AR12 AW26 RXDATAD13 AP12 AU25 RXDATAD12 AN12 AT25 RXDATAD11 AM12 AV26 RXDATAD10 AL12 AR25 RXDATAD9 AR11 AW27 RXDATAD8 AP11 AU26 RXDATAD7 AN11 AT26 RXDATAD6 AM11 AV27 RXDATAD5 AR10 AW28 RXDATAD4 AP10 AR26 RXDATAD3 AN10 AU27 RXDATAD2 AM10 AP26 RXDATAD1 AL10 AT27 RXDATAD0 AR9 AR22 AJ33 T34 AV28 AT17 AK5 V1 RXPRTYD RXPRTYC RXPRTYB RXPRTYA 3.3 V O Receive Data Channel D. Used to transport data out of the UTOPIA PHY Rx block. RXDATAD[15:0] is only valid when RXENBD is asserted, and is updated on the rising edge of RXCLKD. Note: RXDATAD[15:0] is used in various UTOPIA modes. In 8-bit mode, only bits 15 to 8 are valid. In 32-bit mode, RXDATAD[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0), and RXDATAC[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16). 3.3 V O Receive Parity. This signal indicates the parity on the RXDATA[D--A][15:0] bus, when it is used. Odd or even parity is provisioned through bit 3 of register 0x7012 (Table 773). RXPRTY[D--A] is considered valid only when RXENB[D--A] is asserted, and is updated on the rising edge of RXCLK[D--A]. In 32-bit mode, the RXPRTYA and RXPRTYC parity pin of port A and port C, respectively, indicates the parity for the entire 32-bit data output. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 111 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AP9 AL21 AJ32 U31 792 AR27 AR17 AL3 W3 Symbol RXSOPD RXSOPC RXSOPB RXSOPA Type 3.3 V I/O* O Name/Description Receive Start of Packet/Cell. In ATM mode, RXSOP[D--A] signal marks the start of a cell on the RXDATA[D--A][15:0] bus. When RXSOP[D--A] is high, the first word of the cell structure is present on the RXDATA[D--A][15:0] bus. In packet modes, the RXSOP[D--A] signal marks the start of a packet on the RXDATA[D--A][15:0] bus. When RXSOP[D--A] is high, the first word of the packet is present on the RXDATA[D-- A][15:0] bus. RXSOP[D--A] is considered valid only when RXENB[D--A] is asserted, and is updated on the rising edge of RXCLK[D--A]. In 32-bit mode, only the RXSOPA and RXSOPC pin of port A and port C, respectively, is used to indicate a start of packet/cell for the 32-bit data output. AL9 AP21 AK33 V33 AT28 AU18 AL5 Y3 RXPPAD RXPPAC RXPPAB RXPPAA 3.3 V O Receive Cell/Polled Packet Available. This signal indicates when the receive FIFO is below a provisionable level. If the FIFO is empty or less than the provisioned number of bytes are available in the FIFO, RXPPA[D--A] is set low. If RXPPA[D--A] is high, it indicates that the FIFO is full or that more than the provisioned number of bytes are available. In ATM mode, asserting RXPPA[D--A] means that FIFO has one entire ATM cell to send. On the other hand, in packet modes, RXPPA[D--A] just tells that FIFO has data to send, and it operates on a word-by-word basis. RXPPA[D--A] is updated on the rising edge of RXCLK[D--A]. In 32-bit mode, only the RXPPAA and RXPPAC pin of port A and port C, respectively, is used to indicate the packet/cell available status. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 112 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AM8 AN20 AL34 W33 792 AU29 AR18 AM5 AA5 Symbol Type I/O* Name/Description I/O Receive Clock. This clock is used to read cells or packets from the 3.3 V RXCLKD receive FIFO. RXCLK[D--A] can operate at speeds from dc to RXCLKC (5 V toler104 MHz. ant) RXCLKB RXCLKA This clock is required to access channels, i.e., to access channel 2 of slice C, this clock must be provided to slice C (see Table 750). In 32-bit mode, both RXCLKA and RXCLKB are used and required to clock data out of port A. Both RXCLKC and RXCLKD are used and required to clock data out of port C. AM9 AN21 AK34 U34 AP27 AV18 AL4 Y4 RXENBD 3.3 V RXENBC (5 V tolerRXENBB ant) RXENBA IU Receive Data Enable (Active-Low). This signal is used to indicate to the UTOPIA PHY Rx block that it is selected. If RXENB[D--A] is high, no operation is performed. For an unused interface, RXENB[D--A] must be tied high or left unconnected. If RXENB[D-- A] is low, the UTOPIA PHY Rx block sends the next word. In 32-bit mode, only the RXENBA and RXENBC input pin of port A and port C, respectively, is used to enable the transfer of data. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 113 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AN8 AM20 AK31 W35 792 AR28 AT18 AM4 AA3 Symbol RXSZD RXSZC RXSZB RXSZA Type 3.3 V I/O* O Name/Description Receive Size. This signal defines the valid bytes received and their packing within (1) RXDATA[D--A][15:0] for 16-bit mode, and (2) RXDATAA[15:0] and RXDATAB[15:0] for the 32-bit mode. The meaning of these bits may be inverted through TXSZ/RXSZ mode. In 8-bit modes, RXSZ[D--A] are unused. For 16-bit mode, RXSZ[D--A] = 0 defines the MSByte of RXDATA[D--A][15:0], i.e., RXDATA[D--A][15:8], to be the last byte of the packet received when using the default configuration. RXSZ[D--A] = 1 defines the LSByte of RXDATA[D--A][15:0], i.e., RXDATA[D--A][7:0], to be the last byte of the packet received when using the default configuration. For 32-bit mode, RXSZA and RXSZB are combined to define four states of the transmitted data stream on ports A and B. Ports C and D are controlled by RXSZC and RXSZD. The following states are assigned by RXSZA and RXSZB (or RXSZC and RXSZD) when RXEOPA (or RXEOPC) is asserted when using the default configuration. RXDATAA RXDATAA[15:8] RXDATAA[7:0] RXSZA RXSZB DATA[31:24] DATA[23:16] RXDATAB RXDATAB[15:8] RXDATAB[7:0] DATA[15:8] DATA[7:0] 0 0 1 1 0 1 0 1 Valid Valid Valid Valid Not Valid Valid Valid Valid Not Valid Not Valid Valid Valid Not Valid Not Valid Not Valid Valid There is no byte swapping and the data bytes are packed into the upper transmitted bytes first. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). 114 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 AN9 AM21 AJ31 U32 792 AU28 AP17 AK6 W2 Symbol RXEOPD RXEOPC RXEOPB RXEOPA Type 3.3 V I/O* O Name/Description Receive End of Packet. This signal indicates that the last word of a packet is on the RXDATA[D--A][15:0] bus. RXEOP[D--A] is valid only when RXENB[D--A] is asserted, and is updated on the rising edge of RXCLK[D--A]. In 32-bit mode, only the RXEOPA and RXEOPC output pin of port A and port C, respectively, is used to indicate the end of the outgoing packet. AP8 AR21 AK32 V32 AV29 AW18 AL6 Y2 RXERRD RXERRC RXERRB RXERRA 3.3 V O Receive Error. RXERR[D--A] is only used in POS mode, and indicates that the current packet is to be aborted and discarded, if possible. RXERR[D--A] is only valid when RXEOP[D--A] and RXENB[D--A] are asserted, and is updated on the rising edge of RXCLK[D--A]. In 32-bit mode, only the RXERRA and RXERRC output pin of port A and port C, respectively, is used to indicate an error on the outgoing packet. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D--A] refers to four physical interfaces (when bundled, D = last byte, A = first byte). Agere Systems Inc. 115 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 9. Pin Descriptions--Enhanced UTOPIA Interface Signals (continued) Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) on page 718. 600 F31 F32 F33 F34 G31 AK2 AJ5 AJ4 792 K6 J5 J4 K5 K4 AK35 AK36 AJ35 Symbol RXSPAA RXSPAB RXSPAC RXSPAD TXSPAA TXSPAB TXSPAC TXSPAD Type 3.3 V I/O* O O O O O O O O Name/Description Receive Selected Cell/Packet Available, Interface A. Receive Selected Cell/Packet Available, Interface B. Receive Selected Cell/Packet Available, Interface C. Receive Selected Cell/Packet Available, Interface D. Transmit Selected Cell/Packet Available, Interface A. Transmit Selected Cell/Packet Available, Interface B. Transmit Selected Cell/Packet Available, Interface C. Transmit Selected Cell/Packet Available, Interface D. * IU indicates a 100 k internal pull-up. This makes external pull-up resistors on unused inputs unnecessary. Note: These active-high signals indicate the FIFO status of the selected channel on the given interface. On the MARS2G5 P-Pro, two different types of packet available signals are provided, known as polled packet available (PPA) and selected packet available (SPA). PPA is similar to the normal CLAV (cell available) signal in UTOPIA standard documentation, and operates similarly to the PA signals in the MARS2G5 P-ProLT (TDAT042G5) device. PPA is feedback to the UTOPIA master about whether it can start a transfer at some time in the near future on a given interface. SPA is similar to PPA, except that it is feedback to the master about the current transfer, and tells it whether that transfer needs to pause. For the Tx direction, it would need to pause transmission of a long packet when the UTOPIA interface FIFO becomes full. For the Rx direction, it would need to pause transmission of a long packet if the UTOPIA FIFO becomes empty (or nearly so). So while the function of these two signals is similar, the semantics are quite different. PPA tells a master whether it can start a transfer on a given interface. SPA tells a master whether it has to end it. The distinction between PPA and SPA is only needed in cases where the length of the transfer is not known a priori. For ATM cells, the length is fixed (53 bytes), so when a transfer is started, it is known whether there is enough data to complete the transfer, and the SPA signal is not required. On the other hand, for packets of arbitrary length, there is no guarantee, and the SPA signal can be used to differentiate between the end of a packet and the FIFO temporarily running dry/full. Although the SPA signals need not be used when transferring ATM cells, the SPA can indicate to the master when back-to-back transfers are possible, which maximizes the bandwidth efficiency of the interface. 116 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 10. Pin Descriptions--Microprocessor Interface Signals 600 C7 792 C29 Symbol RSTN Type 3.3 V (5 V tolerant) I/O* IU Name/Description Reset (Synchronous) (Active-Low). The RSTN signal highto-low transition (given that RSTN is high for at least four TXCLKP/TXCLKN clock cycles for the edge detector to work properly) resets the digital auto-trim logic of the OC-48 contraclocking 1x PLL (resets the PLL). After the high-to-low transition of RSTN, the PLL will then reset (the auto-trimming function will be done and then normal locking will be completed, a process which may take up to 100 ms) at the end of which time the PLL will be locked. It is suggested that RSTN remain low during this time. The PLL outputs may change over a wide range of frequencies during the 100 ms. See Figure 9 on page 122. E7 E29 ICTN 3.3 V (5 V tolerant) IU 3-State Control (Active-Low). ICTN has an internal 100 k pull-up. Assertion of this input causes all 3.3 V IO pins to enter a 3-state mode. D7 D29 PMRST 3.3 V IU/ 1 Second PM Clock. PM clock can be generated on-chip. (5 V tolerant) O This signal will have a 50% duty cycle. When the PMRST is under software control (PM mode), it can be activated longer or shorter than once per second. The performance-monitoring registers are updated on the rising edge of this signal. 3.3 V (5 V tolerant) 3.3 V (5 V tolerant) 3.3 V (5 V tolerant) 3.3 V IU IU IU O MPU Mode Select. This signal is set high for a synchronous microprocessor, or low for an asynchronous microprocessor. MPU Clock. This clock can operate at up to 66 MHz when in synchronous mode. Chip Select (Active-Low). This signal must be low during register access. Interrupt (Active-Low). This signal goes low when the device generates an unmasked interrupt. This signal is open drain. D8 C8 B8 B7 A12 B12 C12 D12 E12 A11 B11 C11 D11 A10 B10 C10 D10 E10 A9 B9 F27 C28 E27 E28 D23 C23 B23 C24 E24 D24 B24 B25 C25 D25 E25 B26 C26 D26 E26 F26 MPU_ MPMODE MPU_ MPCLK MPU_CSN MPU_INTN MPU_DATA15 3.3 V IU/ Data Bus. This bus is a bidirectional data bus for writing and MPU_DATA14 (5 V tolerant) O reading software registers. MPU_DATA13 MPU_DATA12 MPU_DATA11 MPU_DATA10 MPU_DATA9 MPU_DATA8 MPU_DATA7 MPU_DATA6 MPU_DATA5 MPU_DATA4 MPU_DATA3 MPU_DATA2 MPU_DATA1 MPU_DATA0 * IU indicates a 100 k internal pull-up. Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). Agere Systems Inc. 117 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 10. Pin Descriptions--Microprocessor Interface Signals (continued) 600 B16 C16 D16 A15 B15 C15 E15 A14 B14 C14 D14 E14 B13 C13 D13 E13 792 E20 D20 C20 B20 E21 D21 B21 A22 F22 E22 D22 C22 B22 A23 F23 E23 Symbol Type I/O* IU Name/Description Address Bus. This bus is used to address registers. MPU_ADDR15 3.3 V MPU_ADDR14 (5 V tolerMPU_ADDR13 ant) MPU_ADDR12 MPU_ADDR11 MPU_ADDR10 MPU_ADDR9 MPU_ADDR8 MPU_ADDR7 MPU_ADDR6 MPU_ADDR5 MPU_ADDR4 MPU_ADDR3 MPU_ADDR2 MPU_ADDR1 MPU_ADDR0 E9 D27 MPU_ADSN 3.3 V (5 V tolerant) 3.3 V (5 V tolerant) 3.3 V (5 V tolerant) 3.3 V IU Address Strobe (Active-Low). This signal indicates the address is valid for MPU access. Read/Write. This signal is low to indicate a write operation and is high to indicate a read operation. Data Strobe (Active-Low). This signal used in the asynchronous mode (MPU_MPMODE = 0) indicates that the data is valid for MPU writes. Data Transfer Acknowledge (Active-Low). This signal acknowledges the data transfer cycle. D9 C27 MPU_RWN IU C9 B27 MPU_DSN IU E8 D28 MPU_DTN O * IU indicates a 100 k internal pull-up. Table 11. Pin Descriptions--General-Purpose I/O Signals: Interface Signals 600 AG5 AH2 AH3 AH4 792 AG35 AG34 AH37 AH36 Symbol GPIO3 GPIO2 GPIO1 GPIO0 Type 3.3 V (5 V tolerant) I/O* IU/ O Name/Description General-Purpose I/O. These programmable I/O pins may be used to monitor or control external circuitry. * IU indicates a 100 k internal pull-up. 118 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can drive standard TTL inputs. Table 12. Pin Descriptions--JTAG Interface Signals 600 F2 792 K35 Symbol TCLK Type 3.3 V (5 V tolerant) 3.3 V (5 V tolerant) 3.3 V (5 V tolerant) 3.3 V I/O* I U Name/Description JTAG Test Clock. This 10 MHz maximum signal provides timing for test operations. JTAG Test Mode Select. Controls test operations. TMS is sampled on the rising edge of TCK. TMS has an internal 100 k pullup resister. JTAG Test Data In. Serial 10 Mbits/s maximum test data input signal. TDI is sampled on the rising edge of TCK. TDI has an internal 100 k pull-up resister. JTAG Test Data Out. This serial 10 Mbits/s maximum data output signal is updated on the falling edge of TCK. The TDO output is 3-stated except when scanning out test data. JTAG Test Reset (Active-Low). This signal provides an asynchronous reset for the test access port (TAP). TRSTN has an internal 200 k pull-up resistor. F4 K34 TMS IU G5 K36 TDI IU G2 L36 TDO O G3 L35 TRSTN 3.3 V (5 V tolerant) I * IU indicates a 100 k internal pull-up. Note: JTAG interface signals are used for test operations that are carried out using the IEEE P1149.1 test access port (TAP). Agere Systems Inc. 119 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Table 13. Pin Descriptions--Power Signals 600 B6 792 C30 Symbol Type* I/O PLL_ VDDD2 VDDD P P Name/Description -- OC-48 Contraclocking 1x PLL 1.6 V Digital Power Supply. -- 3.3 V Digital Power Supply. E6, E7, E33, E34,F5, F6, A1, A2, A17, A18, A34, F7, F15, F16, F24, F25, A35, B1, B2, B34, B35, F33, F34, F35, G5, G6, C3, C33, E11, E25, K5, L5, G34, R6, R34, T6, T34, L31, M5, P4, R1, U35, V1, AD6, AD34, AE6, AE34, V2, V35, W1, AB5, AD5, AN6, AN34, AN35, AP5, AE5, AE31, AF5, AL11, AP6, AP7, AP15, AP16, AL18, AL25, AN3, AN33, AP1, AP2, AP34, AP35, AP24, AP25, AP33, AP34, AP35, AR6, AR33, AR34 AR1, AR2, AR18, AR19, AR34, AR35 A5, A6, A30, A31, D4, D27, D32, E1, E5, E16, E20, E31, E35, F1, F35, T5, T31, Y5, Y31, AK1, AK35, AL1, AL5, AL16, AL20, AL31, AL35, AM4, AM32, AR5, AR6, AR30, AR31 A1, A2, A3, A6, A7, A11, A12, A19, A20, A21, A28, A29, A30, A31, A32, A33, A37, A38, A39, B1, B2, B3, B6, B28, B29, B30, B31, B32, B33, B37, B38, B39, C1, C2, C3, C6, C37, C38, C39, D6, D10, G1, G2, G38, G39, H1, H2, H38, H39, J1, J2, J39, K1, K2, K38, K39, L1, L38, L39, M1, M39, W1, W39, Y1, Y39, AA38, AA39, AG38, AG39, AH1, AH38, AH39, AJ1, AJ38, AJ39, AK1, AK2, AK38, AK39, AL1, AL2, AL38, AL39, AM1, AM2, AM38, AM39, AN1, AN2, AN38, AN39, AU1, AU2, AU3, AU37, AU38, AU39, AV1, AV2, AV3, AV7, AV8, AV9, AV10, AV30, AV31, AV32, AV33, AV37, AV38, AV39, AW1, AW2,AW3, AW7, AW8, AW9, AW10, AW11,AW12, AW13, AW19, AW20, AW21, AW29, AW30, AW31, AW32, AW33, AW37, AW38, AW39 H34 D30 VDDD2 P -- 1.6 V Digital Power Supply. E3 C6 * P = power. PLL_ VDDD2 PLL_ GND P P -- OC-48 Contraclocking 1x PLL 1.6 V Digital Power Supply. -- OC-48 Contraclocking 1x PLL Ground. 120 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pin Descriptions (continued) Table 13. Pin Descriptions--Power Signals (continued) 600 A3, A4, A7, A8, A13, A16, A20, A23, A27, A28, A29, A32, A33, B3, B4, B32, B33, C1, C2, C4, C32, C34, C35, D1, D2, D3, D33, D34, D35, F3, G1, G35, H1, H3, H5, H35, N1, N35, T1, T35, V3, V31, Y1, Y4, Y35, AA5, AC1, AC35, AH1, AH35, AJ1, AJ35, AM1, AM2, AM3, AM33, AM34, AM35, AN1, AN2, AN4, AN6, AN32, AN34, AN35, AP3, AP4, AP32, AP33, AR3, AR4, AR7, AR8, AR13, AR16, AR20, AR23, AR28, AR29, AR32, AR33 792 A4, A5, A9, A15, A16, A24, A25, A26, A27, A34, A35, A36, B4, B5, B34, B35, B36, C4, C5, C10, C31, C32, C33, C34, C35, C36, D1, D2, D3, D4, D5, D31, D32, D33, D34, D35, D36, D37, D38, D39, E1, E2, E3, E4, E5, E32, E35, E36, E37, E38, E39, F1, F2, F3, F4, F11, F12, F19, F20, F21, F28, F29, F36, F37, F38, F39, G3, G4, G36, G37, H3, H4, H35, H37, J3, J34, J36, J37, J38, L6, L34, M6, M34, R1, R39, T1, T39, W6, W34, W35, Y6, Y34, AA6, AA34, AD1, AD39, AE1, AE39, AH6, AH34, AJ6, AJ34, AK37, AL37, AM3, AM36, AM37, AN3, AN4, AN36, AN37, AP1, AP2, AP3, AP4, AP11, AP12, AP19, AP20, AP21, AP28, AP29, AP36, AP37, AP38, AP39, AR1, AR2, AR3, AR4, AR5, AR35, AR36, AR37, AR38, AR39, AT1, AT2, AT3, AT4, AT5, AT6, AT7, AT32, AT33, AT34, AT35, AT36, AT37, AT38, AT39, AU4, AU5, AU6, AU7, AU8, AU31, AU32, AU33, AU34, AU35, AU36, AV4, AV5, AV6, AV34, AV35, AV36, AW4, AW5, AW6, AW15, AW16, AW24, AW25, AW34, AW35, AW36 G35 Symbol Type* I/O GNDD P Name/Description -- Digital Ground. E4 * P = power. PLL_ GNDD P -- OC-48 Contraclocking 1x PLL Digital Ground. Agere Systems Inc. 121 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pin Descriptions (continued) Table 14. PLL Test Outputs 600 C5 D5 792 F31 F32 Symbol PLLREF PLLFB Type -- -- I/O O O Name/Description Test output for PLL (normally no connect). Test output for PLL (normally no connect). Table 15. Pin Descriptions--No-Connect Pins 600 B5, D6, D15, E6, F5, G4 792 C21, E30, E31, F30, J35, K37 Symbol NC NC Type -- -- I/O Name/Description -- No Connection. Has internal 100 k pullup resistor. Do not connect to these pins. -- No Connection. Do not connect to these pins. B26, B27, B28, B29, A8, A10, B7, B8, B31, B24, B25, B22, B10, B11, B13, B15, A22, A25, C22, C24, C7, C9, C11, C12, C25, C26, C27, C28, C13, C15, D8, D9, C29, C30, C31, D21, D11, D13, D15, E8, D23, D25, D29, D30, E9, E11, E14, E15, E23, E29, E32, E33 F9, F14, H6, J6 A24, A26, B30, D24, D26, D28, D31, E24, E27, E28, E30, E34 A19, A21, B17, B18, B19, B20, B21, B23, C17, C18, C19, C20, C21, C23, D17, D18, D19, D20, D22, E17, E18, E19, E21, E22, E26 A13, B9, B12, C8, D7, E10, E12, E13 F8, F10, F13, H5 A14, A17, A18, B14, B16, B17, B18, B19, C14, C16, C17, C18, C19, D12, D14, D16, D17, D18, D19, E16, E17, E18, E19, F17, F18 NC -- -- No Connection. Do not connect to these pins. -- No Connection. Do not connect to these pins. NC -- Table 16. Leakage Test Pin 600 E2 792 H36 Symbol IDDQMODE Type -- I/O I Name/Description Leakage Test Pin. This must be connected to digital ground via a 1 k resistor. A B C 2668(F) Note: A = 4 TXCLKP/TXCLKN clock cycles, B = 100 ms, and C = PLL in normal-locking mode. Figure 9. PLL Outputs Lock-In Process 122 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface Device Address Space Assignments This device is equipped with a generic 16-bit microprocessor interface that allows operation with most commercially available microprocessors. A 16-bit address space allows the selection of the registers in each block of the chip, shown in the following table. The addresses are 16-bit word addresses, not byte addresses. When writing reserved bits, a value of 0 should be used, unless otherwise specified. Note: Specified device reset default values are valid only when line interface RXCLK[A--D][P/N] and TXCLK[P/N] clocks; UTOPIA interface TXCLK[A--D] and RXCLK[A--D] clocks are present, the microprocessor clock (MPU_MPCLK) does not need to be present. Table 17. Device Address Space Assignment Base Address and Page 0x0000 (page 164) 0x0800 (page 208) 0x1000 (page 258) 0x2000 0x3000 0x4000 (page 357) 0x5000 (page 518) 0x5800 (page 613) 0x6000 (page 677) 0x7000 (page 748) 0x7400 0x8000 (page 415) 0x8968--0xFFFF Block Microprocessor Interface. Transport Overhead Processor. Pointer Processor. Reserved. Reserved. Path Terminator. DS3/E3 Mapper. Receive Sequencer. Data Engine. UTOPIA Interface. Reserved. Receive Terminator. Reserved. Block Name MPU TOHP PP -- -- PT DS3 RXS DE UT -- RXT -- Reset Default Value of Registers/Bits The reset default value is defined as: 1. 2. 3. 4. The value after RSTN (pin C7, Table 10) is pulled high. OC-48 optics transponder is attached to the device line interface with valid STS-48 data being transferred. Valid TXCLKP/N clock. All UTOPIA clocks supplied. A reset default value of X represents an undefined value of either a 0 or 1. Generally, status register contents after a reset are dependent on architecture and system design; therefore, may vary from one design to the next. Agere Systems Inc. 123 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Microprocessor Interface Modes Input MPU_MPMODE (pin D8) is used to configure the microprocessor interface into one of two possible modes (synchronous or asynchronous). In synchronous mode, the microprocessor interface can operate at speeds from 1 MHz up to 66 MHz. In asynchronous mode, the internal 78 MHz system clock is used to operate this interface. This interface is functionally identical to the interface in the MARS2G5 P-ProLT (TDAT042G5) device with one enhancement made to the synchronous interface mode. In order to enhance reliability, the internal 78 MHz system clock is used to transfer data between the internal device blocks and the MPU interface. The data transferred is then resynchronized to the external MPU clock at the microprocessor interface. The net effect will be a slight uncertainty in the length of an access cycle. Thus, the location of the MPU_DTN (pin E8) signal may not be deterministic. A compatibility mode with MARS2G5 P-ProLT has been preserved, which utilizes the MPU_MPCLK (pin C8) for internal data transfer, but this mode is not recommended. Table 18. MPU Modes MPU_ MPMODE 0 1 Mode Async Sync Microprocessor Interface Signals MPU_CSN, MPU_INTN, MPU_DATA[15:0], MPU_ADDR[15:0], MPU_ADSN, MPU_RWN, MPU_DSN, MPU_DTN MPU_MPCLK, MPU_CSN, MPU_INTN, MPU_DATA[15:0], MPU_ADDR[15:0], MPU_ADSN, MPU_RWN, MPU_DSN, MPU_DTN The host interface is designed to connect directly to a commonly used asynchronous or synchronous host buses. The interface to this block includes a separate clock, MPU_MPCLK, which is used in the synchronous interface mode. The interface is only a slave on the host bus. There is no posting of writes in the host interface all registers are directly accessible. Following are the timing diagrams for reads and writes in both synchronous and asynchronous modes. 124 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing Synchronous Mode The synchronous microprocessor interface mode is selected when MPU_MPMODE (pin D8) = 1. Interface timing for the synchronous mode write cycle is given in Figure 10 and in Table 19 (pages 125--126), and for the read cycle in Figure 11 and in Table 20 (pages 127--128). T0 MPU_MPCLK (66 MHz MAX) t1 MPU_ADDR[15:0] t3 MPU_CSN t4 MPU_ADSN t1 MPU_RWN t2 t5 t2 T1 T2 Tn - 2 Tn - 1 Tn t1 MPU_DATA[15:0] (INPUT) t6 HIGH IMPEDANCE MPU_DTN t2 t7 5-8718(F)r.5 Figure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1) Agere Systems Inc. 125 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) Table 19. Microprocessor Interface Synchronous Write Cycle Specifications (See Figure 10 on page 125 for the timing diagram.) Symbol Parameter Setup (ns) (Min) t1 t2 t3 t4 t5 t6 t7 MPU_ADDR, MPU_RWN, MPU_DATA (write) Valid to MPU_MPCLK MPU_MPCLK to ADDR, MPU_RWN, MPU_DATA (write) Invalid MPU_CSN Valid to MPU_MPCLK MPU_ADSN Valid to MPU_MPCLK MPU_MPCLK to MPU_ADSN Invalid MPU_MPCLK to MPU_DTN Valid MPU_MPCLK to MPU_DTN Invalid 3 -- 3.5 5.5 -- -- -- Hold (ns) (Min) -- 5 -- -- 5 -- 1 Delay (ns) (Max) -- -- -- -- -- 8 -- 126 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) T0 MPU_MPCLK (66 MHz MAX) t8 MPU_ADDR[15:0] t10 MPU_CSN t11 MPU_ADSN t12 t9 T1 T2 Tn - 3 Tn - 2 Tn - 1 Tn MPU_RWN HIGH IMPEDANCE t13 t14 MPU_DTN t15 MPU_DATA[15:0] (OUTPUT) t16 5-8719(F)r.4 Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1) Agere Systems Inc. 127 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) Table 20. Microprocessor Interface Synchronous Read Cycle Specifications (See Figure 11 on page 127 for the timing diagram.) Symbol Parameter Setup (ns) (Min) t8 t9 t10 t11 t12 t13 t14 t15 t16 MPU_ADDR Valid to MPU_MPCLK MPU_MPCLK to MPU_ADDR Invalid MPU_CSN Valid to MPU_MPCLK MPU_ADSN Valid to MPU_MPCLK MPU_MPCLK to MPU_ADSN Invalid MPU_MPCLK to MPU_DTN Valid MPU_MPCLK to MPU_DTN Invalid MPU_MPCLK to MPU_DATA Valid MPU_MPCLK to MPU_DATA 3-state 3 -- 3.5 5.5 -- -- -- -- -- Hold (ns) (Min) -- 5 -- -- 5 -- 1 -- 1 Delay (ns) (Max) -- -- -- -- -- 8 -- 24 -- 128 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) Asynchronous Mode The asynchronous microprocessor interface mode is selected when MPU_MPMODE (pin D8) = 0. Interface timing for the asynchronous mode write cycle is given in Figure 12 and in Table 21 on page 130, and for the read cycle in Figure 13 and in Table 22 (see pages 131--132). MPU_ADDR[15:0] t17 MPU_CSN t19 MPU_ADSN t21 MPU_DSN t23 MPU_RWN t24 t22 t20 t18 t25 MPU_DATA[15:0] (INPUT) t26 t29 t27 t28 MPU_DTN 5-8720(F)r.1 t30 Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0) Agere Systems Inc. 129 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) Table 21. Microprocessor Interface Asynchronous Write Cycle Specifications (See Figure 12 on page 129 for the timing diagram.) Symbol t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 Parameter MPU_CSN Fall to MPU_DSN Fall MPU_ADDR Invalid to MPU_CSN Rise MPU_ADDR Valid to MPU_ADSN Fall MPU_ADSN Rise to MPU_ADDR Invalid MPU_ADDR Valid to MPU_DSN Fall MPU_DSN Rise to MPU_ADDR Invalid MPU_RWN Fall to MPU_DSN Fall MPU_DSN Rise to MPU_RWN Rise MPU_DATA Valid to MPU_DSN Fall MPU_DSN Rise to MPU_DATA Invalid MPU_CSN Fall to MPU_DTN High MPU_DSN Fall to MPU_DTN Fall MPU_ADSN Rise to MPU_DTN Rise MPU_CSN Rise to MPU_DTN 3-state Min Interval Max Interval (ns) (ns) 0 0 0 5 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- --* 37.5 -- * Use the following formula to obtain the maximum value of t28, which is dependent on the UTOPIA clock frequency (TXCLK[D--A], RXCLK[D--A]), which can vary from dc to 104 MHz. t28 maximum = 145 ns + 4(1/UTOPIA clock frequency). For example, at a UTOPIA clock frequency of 52 MHz the maximum value of t28 is: t28 (@ 52 MHz) = 145 ns + 4(1/52,000,000) = 232 ns and t28 (@ 104 MHz) = 193 ns. 130 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) MPU_ADDR t31 MPU_CSN t33 MPU_ADSN t35 MPU_DSN t36 t34 t32 MPU_RWN t37 t38 MPU_DTN t41 MPU_DATA t42 t39 t40 5-8721(F)r.1 Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) Agere Systems Inc. 131 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Microprocessor Interface Timing (continued) Table 22. Microprocessor Interface Asynchronous Read Cycle Specifications (See Figure 13 on page 131 for the timing diagram.) Symbol t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 Parameter MPU_CSN Fall to MPU_DSN Fall MPU_ADDR Invalid to MPU_CSN Rise MPU_ADDR Valid to MPU_ADSN Fall MPU_ADSN Rise to MPU_ADDR Invalid MPU_ADDR Valid to MPU_DSN Fall MPU_DSN Rise to MPU_ADDR Invalid MPU_CSN Fall to MPU_DTN High MPU_DSN Fall to MPU_DTN Fall MPU_ADSN Rise to MPU_DTN Rise MPU_CSN Rise to MPU_DTN 3-state MPU_DTN Valid to MPU_DATA Valid MPU_ADSN Rise to MPU_DATA 3-state Min Interval Max Interval (ns) (ns) 0 0 0 0 0 0 0 0 -- 0 -- 0 -- -- -- -- -- -- -- --* 37.5 -- 12 -- * Use the following formula to obtain the maximum value of t38, which is dependent on the UTOPIA clock frequency (TXCLK[D--A], RXCLK[D--A]), which can vary from dc to 104 MHz. t38 maximum = 145 ns + 4(1/UTOPIA clock frequency). For example, at a UTOPIA clock frequency of 52 MHz the maximum value of t38 is: t38 (@ 52 MHz) = 145 ns + 4(1/52,000,000) = 232 ns and t38 (@ 104 MHz) = 193 ns. 132 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Necessary Register Provisioning Sequence and Clocks When configuring the device internal clock rates, core registers must be written (programmed) prior to provisioning any other registers because writing to certain core registers resets the remainder of the device. Specific clocks must be present to read/write registers prior to provisioning the device. One of the following clocks must be present prior to provisioning to enable register access: TXCLKP (pin U4) and TXCLKN (pin U5). MPU clock (microprocessor interface synchronous mode only). Provisioning must be implemented in the following sequence: Core register 0x0021 (MPU_LI_MODER (Table 41)). Remainder of the core registers must then be provisioned (order does not matter). It is recommended that the remainder of the device be provisioned in the following order (allowing the path terminator (PT) synchronous payload envelop (SPE) FIFO to operate properly, i.e., FIFO overflow on setup is prevented): TOHP, PP, CDA maps within the DE, remainder of the DE, DS3 mapper, SPE mapper/pointer interpreter (PT), RXS block (order does not matter). UT block to turn on the data source to the master and slave. If after provisioning the device as described above there is a lockup in the SPE transmit FIFO, software reset the SPE FIFO by writing a 1 to the appropriate channel through the PT_TX_SOFTRST (Table 266) register and then writing a 0 to release the reset. Agere Systems Inc. 133 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers Several registers in MARS2G5 P-Pro require that certain clocks be present in order to be read or written by the microprocessor. Internal clocks SYSCLK, PAY_RXCLK, PAY_SYSCLK, RX_CLK1, RX_CLK2, RX_CLK3, and RX_CLK4 are used as domain names only. How to ensure the activation of each clock domain is described below the reference to that domain. All RXT registers are in the PAY_RXCLK domain. > > > > > > > > > else MPU_LI_MODE reg 0x0021 bit 11 is 1 A clock is present on RXD14P_RXCLKAP and RXD14N_RXCLKAN MPU_PAY_RXCLKPDN_SYSCLKPDN reg 0x001b bit 4 must be 0 and if MPU_LI_MODE reg 0x0021 bit 6 is 0 (not POF) or MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback) A clock must be present on TXCLKP and TXCLKN else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48) A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN Other PT registers are in the PAY_SYSCLK domain. MPU_PAY_TXCLKPDN_SYSCLKPDN reg 0x001b bit 5 must be 0. A clock must be present on TXCLKP and TXCLKN. Some DS3 registers are in the PAY_RXCLK domain. PAY_RXCLK is as specified for RXT. 0x5081 and 0x5094 registers require PAY_RXCLK to complete the MPU bus cycle. Otherwise, the MPU must drop MPU_CSN (Chip Select) before proceeding. 134 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) The following UTOPIA registers require clocks as specified. (PAY_SYSCLK and PAY_RXCLK are as specified for PT and RXT. TxClkA, TxClkB, TxClkC, TxClkD, RxClkA, RxClkB, RxClkC, and RxClkD are pins.) 0x7011 TxClkA 0x7015 TxClkB 0x7019 TxClkC 0x701D TxClkD 0x7030 TxClkA 0x7038 TxClkA 0x7040 TxClkA 0x7048 TxClkA 0x7050 TxClkB 0x7058 TxClkB 0x7060 TxClkB 0x7068 TxClkB 0x7070 TxClkC 0x7078 TxClkC 0x7080 TxClkC 0x7088 TxClkC 0x7090 TxClkD 0x7098 TxClkD 0x70A0 TxClkD 0x70A8 TxClkD If these UTOPIA registers do not have the required clocks, the MPU bus cycle will not complete. In this case, the MPU must drop MPU_CSN (chip select) before proceeding. Agere Systems Inc. 135 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) PP registers fall in five domains: 1. For PP registers in the SYSCLK domain. MPU_SON_PP_SYSCLKPDN reg 0x001b bit 2 must be 0. A clock must be present on TXCLKP and TXCLKN. 2. For PP registers in RX_CLK1 domain (A). > if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback) > > > > > > else MPU_LI_MODE reg 0x0021 bit 11 is 1 A clock is present on RXD14P_RXCLKAP and RXD14N_RXCLKAN A clock must be present on TXCLKP and TXCLKN else if MPU_LI_MODE reg 0x0021 bit4 is 1 (OC48) A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN 3. For PP registers in RX_CLK2 domain (B). > if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback) > > > > > > else MPU_LI_MODE reg 0x0021 bit 10 is 1 A clock is present on RXD13P_RXCLKBP and RXD13N_RXCLKBN A clock must be present on TXCLKP and TXCLKN else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48) A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN 136 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 4. For PP registers in RX_CLK3 domain (C). > if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback) > > > > > > else MPU_LI_MODE reg 0x0021 bit 9 is 1 A clock is present on RXD11P_RXCLKCP and RXD11N_RXCLKCN A clock must be present on TXCLKP and TXCLKN else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48) A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN 5. For PP registers in RX_CLK3 domain (D) > if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback) > > > > > > else MPU_LI_MODE reg 0x0021 bit 8 is 1 A clock is present on RXD9P_RXCLKDP and RXD9N_RXCLKDN A clock must be present on TXCLKP and TXCLKN else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48) A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN Agere Systems Inc. 137 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) If PP registers in an unclocked domain are written, they will not be written but the MPU bus cycle will complete. If PP registers in an unclocked domain are read, garbage will be read and the MPU bus cycle will complete. The following PP registers are in the SYSCLK domain: 0x1300: 32 // PATH_TRACE_BUF_1f 0x1301: 31 // PATH_TRACE_BUF_1e 0x1302: 30 // PATH_TRACE_BUF_1d 0x1303: 29 // PATH_TRACE_BUF_1c 0x1304: 28 // PATH_TRACE_BUF_1b 0x1305: 27 // PATH_TRACE_BUF_1a 0x1306: 26 // PATH_TRACE_BUF_19 0x1307: 25 // PATH_TRACE_BUF_18 0x1308: 24 // PATH_TRACE_BUF_17 0x1309: 23 // PATH_TRACE_BUF_16 0x130A: 22 // PATH_TRACE_BUF_15 0x130B: 21 // PATH_TRACE_BUF_14 0x130C: 20 // PATH_TRACE_BUF_13 0x130D: 19 // PATH_TRACE_BUF_12 0x130E: 18 // PATH_TRACE_BUF_11 0x130F: 17 // PATH_TRACE_BUF_10 0x1310: 16 // PATH_TRACE_BUF_f 0x1311: 15 // PATH_TRACE_BUF_e 0x1312: 14 // PATH_TRACE_BUF_d 0x1313: 13 // PATH_TRACE_BUF_c 0x1314: 12 // PATH_TRACE_BUF_b 0x1315: 11 // PATH_TRACE_BUF_a 0x1316: 10 // PATH_TRACE_BUF_9 0x1317: 9 // PATH_TRACE_BUF_8 0x1318: 8 // PATH_TRACE_BUF_7 0x1319: 7 // PATH_TRACE_BUF_6 0x131A: 6 // PATH_TRACE_BUF_5 0x131B: 5 // PATH_TRACE_BUF_4 0x131C: 4 // PATH_TRACE_BUF_3 0x131D: 3 // PATH_TRACE_BUF_2 0x131E: 2 // PATH_TRACE_BUF_1 0x131F: 1 // PATH_TRACE_BUF_0 0x1333: 0 // J1_BUFFER_ACCESS_BEGIN Agere Systems Inc. 138 Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) > Dpathtrace_regsel[32:0] = 33'h0; 0x1000: 102 // PP_ID 0x1001: 101 // CORW_SETTING 0x1010: 100 // GLOBAL_ALARM 0x1210: 99 // GLOBAL_ALARM_IMR 0x100F: 98 // GLOBAL_ALARM2 0x120F: 97 // GLOBAL_ALARM2_IMR 0x1021: 96 // MAIN_ELASTIC_STORE_OVERRUN 0x1211: 95 // MAIN_ELASTIC_STORE_OVERRUN_IMR 0x1031: 94 // MAIN_SF_P 0x1221: 93 // MAIN_SF_P_IMR 0x1041: 92 // MAIN_RDI_P 0x1231: 91 // MAIN_RDI_P_IMR 0x1111: 90 // MAIN_RDI_DELTA_P 0x1291: 89 // MAIN_RDI_DELTA_P_IMR 0x1051: 88 // MAIN_PLM_P 0x1241: 87 // MAIN_PLM_P_IMR 0x1121: 86 // MAIN_PLM_DELTA_P 0x12A1: 85 // MAIN_PLM_DELTA_P_IMR 0x1061: 84 // MAIN_UNEQ_P 0x1251: 83 // MAIN_UNEQ_P_IMR 0x1131: 82 // MAIN_UNEQ_DELTA_P 0x12B1: 81 // MAIN_UNEQ_DELTA_P_IMR 0x1071: 80 // MAIN_AIS_P 0x1261: 79 // MAIN_AIS_P_IMR 0x1141: 78 // MAIN_AIS_DELTA_P 0x12C1: 77 // MAIN_AIS_DELTA_P_IMR 0x1081: 76 // MAIN_LOP_P 0x1271: 75 // MAIN_LOP_P_IMR 0x1151: 74 // MAIN_LOP_DELTA_P 0x12D1: 73 // MAIN_LOP_DELTA_P_IMR 0x1181: 72 // MAIN_SS_NEW_VALIDATED 0x12F9: 71 // MAIN_SS_NEW_VALIDATED_IMR 0x1187: 70 // MAIN_SS_MISMATCH Agere Systems Inc. 139 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x12E2: 69 // MAIN_SS_MISMATCH_IMR 0x117F: 68 // F2_NEW_VALIDATED 0x12F7: 67 // F2_NEW_VALIDATED_IMR 0x117D: 66 // H4_NEW_VALIDATED 0x12F5: 65 // H4_NEW_VALIDATED_IMR 0x117B: 64 // Z3_NEW_VALIDATED 0x12F3: 63 // Z3_NEW_VALIDATED_IMR 0x1179: 62 // Z4_NEW_VALIDATED 0x12F1: 61 // Z4_NEW_VALIDATED_IMR 0x1177: 60 // Z5_NEW_VALIDATED 0x12EF: 59 // Z5_NEW_VALIDATED_IMR 0x1101: 58 // MAIN_PDI_P 0x1281: 57 // MAIN_PDI_P_IMR 0x1171: 56 // MAIN_PDI_DELTA_P 0x12E9: 55 // MAIN_PDI_DELTA_P_IMR 0x1091: 54 // CONC_MISMATCH 0x1277: 53 // CONC_MISMATCH_MASK 0x10A1: 52 // CONC_UNSUPPORT 0x1279: 51 // CONC_UNSUPPORT_MASK 0x1400: 50 // SET_SF_WINDOW_SIZE_SEL[0:7] 0x1401: 49 // CLEAR_SF_WINDOW_SIZE_SEL[0:7] 0x1410--0x1417 // TH_DETECT_[0:7] 0x1418--0x141F // TH_CLEAR_[0:7] 0x1420: 32 // SF_WINDOW_SIZE0 0x1430: 31 // SF_WINDOW_SIZE1 0x1440: 30 // SF_WINDOW_SIZE2 0x1450: 29 // SF_WINDOW_SIZE3 0x1590: 28 // INC_DEC_SEL_1 0x1591: 27 // INC_DEC_SEL_2 0x1592: 26 // INC_DEC_SEL_3 0x1593: 25 // INC_DEC_SEL_4 0x162C: 24 // ES_INC_MIN, // ES_DEC_MAX 0x162D: 23 // ES_OVR_MIN, // ES_OVR_MAX 0x1330: 22 // J1_CHANNEL_SEL 140 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x1331: 21 // J1_BUFFER_MESSAGE_TYPE 0x1332: 20 // J1_BUFFER_ACCESS_TYPE 0x1338: 19 // J1_MESSAGE_MODE_STREAM_SEL 0x1339: 18 // J1_MESSAGE_TYPE_STREAM_SEL 0x133C: 17 // J1_ACCUM_CHANNEL_SEL_1 0x133D: 16 // J1_ACCUM_CHANNEL_SEL_2 0x133E: 15 // J1_ACCUM_CHANNEL_SEL_3 0x133F: 14 // J1_ACCUM_CHANNEL_SEL_4 0x1160: 13 // J1_ACCESS_COMPLETE 0x12E0: 12 // J1_ACCESS_COMPLETE_IMR 0x1C1: 11 // J1_NEW_VALIDATED 0x127B: 10 // J1_NEW_VALIDATED_IMR 0x10D1: 9 // J1_MISMATCH 0x127D: 8 // J1_MISMATCH_IMR 0x1780: 7 // GLOBAL_PM 0x1781: 6 // ONE_BIT_RDI_P_PM_STREAM 0x1791: 5 // ERDI_PAYLOAD_P_PM_STREAM 0x17A1: 4 // ERDI_CONNECT_P_PM_STREAM 0x17B1: 3 // ERDI_SERVER_P_PM_STREAM 0x17C1: 2 // UNEQ_P_PM_STREAM 0x17D1: 1 // AIS_P_PM_STREAM 0x17E1: 0 // LOP_P_PM_STREAM Dsys_regsel[102:0] = 103'h0; > Agere Systems Inc. 141 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) The following PP registers are in RX_CLK1 domain: 0x1022: 148 // ELASTIC_STORE_OVERRUN_1 0x1212: 147 // ELASTIC_STORE_OVERRUN_MASK_1 0x1032: 146 // SF_P_1 0x1222: 145 // SF_P_MASK_1 0x1042: 144 // RDI_P_1 0x1232: 143 // RDI_P_MASK_1 0x1112: 142 // RDI_DELTA_P_1 0x1292: 141 // RDI_DELTA_P_MASK_1 0x1382: 140 // RDI_PERSIST_P_1 0x13C2: 139 // RDI_DELTA_STATE_P_1 0x1052: 138 // PLM_P_1 0x1242: 137 // PLM_P_MASK_1 0x1122: 136 // PLM_DELTA_P_1 0x12A2: 135 // PLM_DELTA_P_MASK_1 0x138A: 134 // PLM_PERSIST_P_1 0x13CA: 133 // PLM_DELTA_STATE_P_1 0x1062: 132 // UNEQ_P_1 0x1252: 131 // UNEQ_P_MASK_1 0x1132: 130 // UNEQ_DELTA_P_1 0x12B2: 129 // UNEQ_DELTA_P_MASK_1 0x1392: 128 // UNEQ_PERSIST_P_1 0x13D2: 127 // UNEQ_DELTA_STATE_P_1 0x1072: 126 // AIS_P_1 0x1262: 125 // AIS_P_MASK_1 0x1142: 124 // AIS_DELTA_P_1 0x12C2: 123 // AIS_DELTA_P_MASK_1 0x139A: 122 // AIS_PERSIST_P_1 0x13DA: 121 // AIS_DELTA_STATE_P_1 PDI_DELTA_STATE_P_1 0x1082: 120 // LOP_P_1 0x1272: 119 // LOP_P_MASK_1 0x1152: 118 // LOP_DELTA_P_1 0x12D2: 117 // LOP_DELTA_P_MASK_1 0x13A2: 116 // LOP_PERSIST_P_1 142 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x13E2: 115 // LOP_DELTA_STATE_P_1 0x1102: 114 // PDI_P_1 0x1282: 113 // PDI_P_MASK_1 SS_MISMATCH_MASK_1 0x1172: 112 // PDI_DELTA_P_1 0x12EA: 111 // PDI_DELTA_P_MASK_1 0x13AA: 110 // PDI_PERSIST_P_1 0x1182: 109 // SS_NEW_VLD_1 0x12FA: 108 // SS_NEW_VLD_MASK_1 0x1188: 107 // SS_MISMATCH_1 0x1502: 106 // EXP_CONC_1 0x1507: 105 // CONC_EN_1 0x1512: 104 // REC_CONC_1 0x1542: 103 // PATH_AIS_INS_1 0x1547: 102 // UNEQ_AIS_INS_1 0x154C: 101 // PLM_AIS_INS_1 0x1551: 100 // TIM_AIS_INS_1 0x1582: 99 // SS_INSERT_CONTROL_1 0x1587: 98 // E1_F1_INSERT_CONTROL_1 0x158C: 97 // E2_INSERT_CONTROL_1 0x15A2: 96 // PDI_VALIDATE_ENABLE_1 0x1594: 95 // TIM_P_INSERT_CONTROL_1 0x1341: 94 // REC_F2_1 REC_H4_1 0x1342: 93 // REC_Z3_1 REC_Z4_1 0x1343: 92 // REC_Z5_1 0x1344: 91 // F2_VLDP_1 H4Z3Z4_VLDP_1 Z5_VLDP_1 CH_SEL_1 0x1351: 90 // REC_SS_1_TSLOT[1:6] 0x1352: 89 // REC_SS_1_TSLOT[7:12] 0x1600--0x1605 // EXP_C2_STS_[1:12] 0x1618: 82 // COUNT_BB_ERRORS_SEL_1 0x1580: 81 // SONET_SDH_RULES_1 0x1620: 80 // SS_BITS_SETTING_[1:6] 0x1621: 79 // SS_BITS_SETTING_[7:12] 0x1650--0x1655 //E1_F1_INSERT_BYTE_[1:12] 0x1668: 72 // E2_INSERT_BYTE_1 Agere Systems Inc. 143 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x1682: 71 // SD_INSERT_1 0x1690: 70 // SF_THRESH_SEL_STS_1 0x1691: 69 // SF_THRESH_SEL_STS_2 0x1692: 68 // SF_THRESH_SEL_STS_3 0x1693: 67 // SF_THRESH_SEL_STS_4 0x1694: 66 // SF_THRESH_SEL_STS_5 0x1695: 65 // SF_THRESH_SEL_STS_6 0x1696: 64 // SF_THRESH_SEL_STS_7 0x1697: 63 // SF_THRESH_SEL_STS_8 0x1698: 62 // SF_THRESH_SEL_STS_9 0x1699: 61 // SF_THRESH_SEL_STS_10 0x169A: 60 // SF_THRESH_SEL_STS_11 0x169B: 59 // SF_THRESH_SEL_STS_12 0x1702: 58 // LAST_INT_INC_1 0x1712: 57 // LAST_INT_DEC_1 0x1742: 56 // LAST_GEN_INC_1 0x1752: 55 // LAST_GEN_DEC_1 0x1782: 54 // ONE_BIT_RDI_PM_1 0x1792: 53 // ERDI_PAYLOAD_PM_1 0x17A2: 52 // ERDI_CONNECT_PM_1 0x17B2: 51 // ERDI_SERVER_PM_1 0x17C2: 50 // UNEQ_P_PM_1 0x17D2: 49 // AIS_P_PM_1 0x17E2: 48 // LOP_P_PM_1 0x1800: 47 // CV_COUNT_STS_1_PM 0x1801: 46 // CV_COUNT_STS_2_PM 0x1802: 45 // CV_COUNT_STS_3_PM 0x1803: 44 // CV_COUNT_STS_4_PM 0x1804: 43 // CV_COUNT_STS_5_PM 0x1805: 42 // CV_COUNT_STS_6_PM 0x1806: 41 // CV_COUNT_STS_7_PM 0x1807: 40 // CV_COUNT_STS_8_PM 0x1808: 39 // CV_COUNT_STS_9_PM 0x1809: 38 // CV_COUNT_STS_10_PM 144 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x180A: 37 // CV_COUNT_STS_11_PM 0x180B: 36 // CV_COUNT_STS_12_PM 0x1880: 35 // REI_COUNT_STS_1_PM 0x1881: 34 // REI_COUNT_STS_2_PM 0x1882: 33 // REI_COUNT_STS_3_PM 0x1883: 32 // REI_COUNT_STS_4_PM 0x1884: 31 // REI_COUNT_STS_5_PM 0x1885: 30 // REI_COUNT_STS_6_PM 0x1886: 29 // REI_COUNT_STS_7_PM 0x1887: 28 // REI_COUNT_STS_8_PM 0x1888: 27 // REI_COUNT_STS_9_PM 0x1889: 26 // REI_COUNT_STS_10_PM 0x188A: 25 // REI_COUNT_STS_11_PM 0x188B: 24 // REI_COUNT_STS_12_PM 0x1900--0x190B // RECEIVED_RDI_STS_[1:12] 0x1930: 11 // REC_C2_STS_1, // REC_C2_STS_2 0x1931: 10 // REC_C2_STS_3, // REC_C2_STS_4 0x1932: 9 // REC_C2_STS_5, // REC_C2_STS_6 0x1933: 8 // REC_C2_STS_7, // REC_C2_STS_8 0x1934: 7 // REC_C2_STS_9, // REC_C2_STS_10 0x1935: 6 // REC_C2_STS_11, // REC_C2_STS_12 0x1960: 5 // REC_PDI_STS_1, // REC_PDI_STS_2 0x1961: 4 // REC_PDI_STS_3, // REC_PDI_STS_4 0x1962: 3 // REC_PDI_STS_5, // REC_PDI_STS_6 0x1963: 2 // REC_PDI_STS_7, // REC_PDI_STS_8 0x1964: 1 // REC_PDI_STS_9, // REC_PDI_STS_10 0x1965: 0 // REC_PDI_STS_11, // REC_PDI_STS_12 Agere Systems Inc. 145 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) The following PP registers are in RX_CLK2 domain: 0x1023: 149 // ELASTIC_STORE_OVERRUN_2 0x1213: 148 // ELASTIC_STORE_OVERRUN_MASK_2 0x1033: 147 // SF_P_2 0x1223: 146 // SF_P_MASK_2 0x1043: 145 // RDI_P_2 0x1233: 144 // RDI_P_MASK_2 0x1113: 143 // RDI_DELTA_P_2 0x1293: 142 // RDI_DELTA_P_MASK_2 0x1383: 141 // RDI_PERSIST_P_2 0x13C3: 140 // RDI_DELTA_STATE_P_2 0x1053: 139 // PLM_P_2 0x1243: 138 // PLM_P_MASK_2 0x1123: 137 // PLM_DELTA_P_2 0x12A3: 136 // PLM_DELTA_P_MASK_2 0x138B: 135 // PLM_PERSIST_P_2 0x13CB: 134 // PLM_DELTA_STATE_P_2 0x1063: 133 // UNEQ_P_2 0x1253: 132 // UNEQ_P_MASK_2 0x1133: 131 // UNEQ_DELTA_P_2 0x12B3: 130 // UNEQ_DELTA_P_MASK_2 0x1393: 129 // UNEQ_PERSIST_P_2 0x13D3: 128 // UNEQ_DELTA_STATE_P_2 0x1073: 127 // AIS_P_2 0x1263: 126 // AIS_P_MASK_2 0x1143: 125 // AIS_DELTA_P_2 0x12C3: 124 // AIS_DELTA_P_MASK_2 0x139B: 123 // AIS_PERSIST_P_2 0x13DB: 122 // AIS_DELTA_STATE_P_2, // PDI_DELTA_STATE_P_2 0x1083: 121 // LOP_P_2 0x1273: 120 // LOP_P_MASK_2 0x1153: 119 // LOP_DELTA_P_2 0x12D3: 118 // LOP_DELTA_P_MASK_2 0x13A3: 117 // LOP_PERSIST_P_2 146 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x13E3: 116 // LOP_DELTA_STATE_P_2 0x1103: 115 // PDI_P_2 0x1283: 114 // PDI_P_MASK_2 0x1173: 113 // PDI_DELTA_P_2 0x12EB: 112 // PDI_DELTA_P_MASK_2 0x13AB: 111 // PDI_PERSIST_P_2 0x1183: 110 // SS_NEW_VLD_2 0x12FB: 109 // SS_NEW_VLD_MASK_2 0x1189: 108 // SS_MISMATCH_2 0x12E4: 107 // SS_MISMATCH_MASK_2 0x1503: 106 // EXP_CONC_2 0x1508: 105 // CONC_EN_2 0x1513: 104 // REC_CONC_2 0x1543: 103 // PATH_AIS_INS_2 0x1548: 102 // UNEQ_AIS_INS_2 0x154D: 101 // PLM_AIS_INS_2 0x1552: 100 // TIM_AIS_INS_2 0x1583: 99 // SS_INSERT_CONTROL_2 0x1588: 98 // E1_F1_INSERT_CONTROL_2 0x158D: 97 // E2_INSERT_CONTROL_2 0x15A3: 96 // PDI_VALIDATE_ENABLE_2 0x1345: 95 // REC_F2_2, // REC_H4_2 0x1346: 94 // REC_Z3_2, // REC_Z4_2 0x1347: 93 // REC_Z5_2 0x1348: 92 // F2_VLDP_2 H4Z3Z4_VLDP_2 Z5_VLDP_2 CH_SEL_2 0x1353: 91 // REC_SS_2_TSLOT[1:6] 0x1354: 90 // REC_SS_2_TSLOT[7:12] 0x1606--0x160B // EXP_C2_STS_[13:24] 0x1619: 83 // COUNT_BB_ERRORS_SEL_2 0x1580: 82 // SONET_SDH_RULES_2 0x1622: 81 //SS_BITS_SETTING_[13:18] 0x1623: 80 //SS_BITS_SETTING_[19:24] 0x1656--0x165B // E1_F1_INSERT_BYTE_[13:24] 0x1669: 73 // E2_INSERT_BYTE_2 Agere Systems Inc. 147 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x1595: 72 // TIM_P_INSERT_CONTROL_2 0x1683: 71 // SD_INSERT_2 0x169C: 70 // SF_THRESH_SEL_STS_13 0x169D: 69 // SF_THRESH_SEL_STS_14 0x169E: 68 // SF_THRESH_SEL_STS_15 0x169F: 67 // SF_THRESH_SEL_STS_16 0x16A0: 66 // SF_THRESH_SEL_STS_17 0x16A1: 65 // SF_THRESH_SEL_STS_18 0x16A2: 64 // SF_THRESH_SEL_STS_19 0x16A3: 63 // SF_THRESH_SEL_STS_20 0x16A4: 62 // SF_THRESH_SEL_STS_21 0x16A5: 61 // SF_THRESH_SEL_STS_22 0x16A6: 60 // SF_THRESH_SEL_STS_23 0x16A7: 59 // SF_THRESH_SEL_STS_24 0x1703: 58 // LAST_INT_INC_2 0x1713: 57 // LAST_INT_DEC_2 0x1743: 56 // LAST_GEN_INC_2 0x1753: 55 // LAST_GEN_DEC_2 0x1783: 54 // ONE_BIT_RDI_PM_2 0x1793: 53 // ERDI_PAYLOAD_PM_2 0x17A3: 52 // ERDI_CONNECT_PM_2 0x17B3: 51 // ERDI_SERVER_PM_2 0x17C3: 50 // UNEQ_P_PM_2 0x17D3: 49 // AIS_P_PM_2 0x17E3: 48 // LOP_P_PM_2 0x180C: 47 // CV_COUNT_STS_13_PM 0x180D: 46 // CV_COUNT_STS_14_PM 0x180E: 45 // CV_COUNT_STS_15_PM 0x180F: 44 // CV_COUNT_STS_16_PM 0x1810: 43 // CV_COUNT_STS_17_PM 0x1811: 42 // CV_COUNT_STS_18_PM 0x1812: 41 // CV_COUNT_STS_19_PM 0x1813: 40 // CV_COUNT_STS_20_PM 0x1814: 39 // CV_COUNT_STS_21_PM 148 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x1815: 38 // CV_COUNT_STS_22_PM 0x1816: 37 // CV_COUNT_STS_23_PM 0x1817: 36 // CV_COUNT_STS_24_PM 0x188C: 35 // REI_COUNT_STS_13_PM 0x188D: 34 // REI_COUNT_STS_14_PM 0x188E: 33 // REI_COUNT_STS_15_PM 0x188F: 32 // REI_COUNT_STS_16_PM 0x1890: 31 // REI_COUNT_STS_17_PM 0x1891: 30 // REI_COUNT_STS_18_PM 0x1892: 29 // REI_COUNT_STS_19_PM 0x1893: 28 // REI_COUNT_STS_20_PM 0x1894: 27 // REI_COUNT_STS_21_PM 0x1895: 26 // REI_COUNT_STS_22_PM 0x1896: 25 // REI_COUNT_STS_23_PM 0x1897: 24 // REI_COUNT_STS_24_PM 0x190C--0x1917 // RECEIVED_RDI_STS_[13:24] 0x1936: 11 // REC_C2_STS_13, // REC_C2_STS_14 0x1937: 10 // REC_C2_STS_15, // REC_C2_STS_16 0x1938: 9 // REC_C2_STS_17, // REC_C2_STS_18 0x1939: 8 // REC_C2_STS_19, // REC_C2_STS_20 0x193A: 7 // REC_C2_STS_21, // REC_C2_STS_22 0x193B: 6 // REC_C2_STS_23, // REC_C2_STS_24 0x1966: 5 // REC_PDI_STS_13, // REC_PDI_STS_14 0x1967: 4 // REC_PDI_STS_15, // REC_PDI_STS_16 0x1968: 3 // REC_PDI_STS_17, // REC_PDI_STS_18 0x1969: 2 // REC_PDI_STS_19, // REC_PDI_STS_20 0x196A: 1 // REC_PDI_STS_21, // REC_PDI_STS_22 0x196B: 0 // REC_PDI_STS_23, // REC_PDI_STS_24 Agere Systems Inc. 149 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) The following PP registers are in RX_CLK3 domain: 0x1024: 151 // ELASTIC_STORE_OVERRUN_3 0x1214: 150 // ELASTIC_STORE_OVERRUN_MASK_3 0x1034: 149 // SF_P_3 0x1224: 148 // SF_P_MASK_3 0x1044: 147 // RDI_P_3 0x1234: 146 // RDI_P_MASK_3 0x1114: 145 // RDI_DELTA_P_3 0x1294: 144 // RDI_DELTA_P_MASK_3 0x1384: 143 // RDI_PERSIST_P_3 0x13C4: 142 // RDI_DELTA_STATE_P_3 0x1054: 141 // PLM_P_3 0x1244: 140 // PLM_P_MASK_3 0x1124: 139 // PLM_DELTA_P_3 0x12A4: 138 // PLM_DELTA_P_MASK_3 0x138C: 137 // PLM_PERSIST_P_3 0x13CC: 136 // PLM_DELTA_STATE_P_3 0x1064: 135 // UNEQ_P_3 0x1254: 134 // UNEQ_P_MASK_3 0x1134: 133 // UNEQ_DELTA_P_3 0x12b4: 132 // UNEQ_DELTA_P_MASK_3 0x1394: 131 // UNEQ_PERSIST_P_3 0x13D4: 130 // UNEQ_DELTA_STATE_P_3 0x1074: 129 // AIS_P_3 0x1264: 128 // AIS_P_MASK_3 0x1144: 127 // AIS_DELTA_P_3 0x12C4: 126 // AIS_DELTA_P_MASK_3 0x139C: 125 // AIS_PERSIST_P_3 0x13DC: 124 // AIS_DELTA_STATE_P_3, // PDI_DELTA_STATE_P_3 0x1084: 123 // LOP_P_3 0x1274: 122 // LOP_P_MASK_3 0x1154: 121 // LOP_DELTA_P_3 0x12D4: 120 // LOP_DELTA_P_MASK_3 0x13A4: 119 // LOP_PERSIST_P_3 150 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x13E4: 118 // LOP_DELTA_STATE_P_3 0x1104: 117 // PDI_P_3 0x1284: 116 // PDI_P_MASK_3 0x1174: 115 // PDI_DELTA_P_3 0x12EC: 114 // PDI_DELTA_P_MASK_3 0x13AC: 113 // PDI_PERSIST_P_3 0x1184: 112 // SS_NEW_VLD_3 0x12FC: 111 // SS_NEW_VLD_MASK_3 0x118A: 110 // SS_MISMATCH_3 0x12E5: 109 // SS_MISMATCH_MASK_3 0x1504: 108 // EXP_CONC_3 0x1509: 107 // CONC_EN_3 0x1514: 106 // REC_CONC_3 0x1544: 105 // PATH_AIS_INS_3 0x1549: 104 // UNEQ_AIS_INS_3 0x154E: 103 // PLM_AIS_INS_3 0x1553: 102 // TIM_AIS_INS_3 0x1584: 101 // SS_INSERT_CONTROL_3 0x1589: 100 // E1_F1_INSERT_CONTROL_3 0x158E: 99 // E2_INSERT_CONTROL_3 0x15A4: 98 // PDI_VALIDATE_ENABLE_3 0x1349: 97 // REC_F2_3, // REC_H4_3 0x134A: 96 // REC_Z3_3, // REC_Z4_3 0x134B: 95 // REC_Z5_3 0x134C: 94 // F2_VLDP_3 H4Z3Z4_VLDP_3 Z5_VLDP_3 CH_SEL_3 0x1355: 93 // REC_SS_3_TSLOT[1:6] 0x1356: 92 // REC_SS_3_TSLOT[7:12] 0x160C--0x1611 // EXP_C2_STS_[25:36] 0x161A: 85 // COUNT_BB_ERRORS_SEL_3 0x1580: 84 // SONET_SDH_RULES_3 0x1624: 83 // SS_BITS_SETTING_[25:30] 0x1625: 82 // SS_BITS_SETTING_[31:36] 0x1629: 81 // SS_BITS_MONITOR_MODE 0x162A: 80 // SS_BITS_VALIDATE_PERIOD Agere Systems Inc. 151 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x165C--0x1661 // E1_F1_INSERT_BYTE_[25:36] 0x166A: 73 // E2_INSERT_BYTE_3 0x1596: 72 // TIM_P_INSERT_CONTROL_3 0x1684: 71 // SD_INSERT_3 0x16A8: 70 // SF_THRESH_SEL_STS_25 0x16A9: 69 // SF_THRESH_SEL_STS_26 0x16AA: 68 // SF_THRESH_SEL_STS_27 0x16AB: 67 // SF_THRESH_SEL_STS_28 0x16AC: 66 // SF_THRESH_SEL_STS_29 0x16AD: 65 // SF_THRESH_SEL_STS_30 0x16AE: 64 // SF_THRESH_SEL_STS_31 0x16AF: 63 // SF_THRESH_SEL_STS_32 0x16B0: 62 // SF_THRESH_SEL_STS_33 0x16B1: 61 // SF_THRESH_SEL_STS_34 0x16B2: 60 // SF_THRESH_SEL_STS_35 0x16B3: 59 // SF_THRESH_SEL_STS_36 0x1704: 58 // LAST_INT_INC_3 0x1714: 57 // LAST_INT_DEC_3 0x1744: 56 // LAST_GEN_INC_3 0x1754: 55 // LAST_GEN_DEC_3 0x1784: 54 // ONE_BIT_RDI_PM_3 0x1794: 53 // ERDI_PAYLOAD_PM_3 0x17A4: 52 // ERDI_CONNECT_PM_3 0x17B4: 51 // ERDI_SERVER_PM_3 0x17C4: 50 // UNEQ_P_PM_3 0x17D4: 49 // AIS_P_PM_3 0x17E4: 48 // LOP_P_PM_3 0x1818: 47 // CV_COUNT_STS_25_PM 0x1819: 46 // CV_COUNT_STS_26_PM 0x181A: 45 // CV_COUNT_STS_27_PM 0x181B: 44 // CV_COUNT_STS_28_PM 0x181C: 43 // CV_COUNT_STS_29_PM 0x181D: 42 // CV_COUNT_STS_30_PM 0x181E: 41 // CV_COUNT_STS_31_PM 152 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x181F: 40 // CV_COUNT_STS_32_PM 0x1820: 39 // CV_COUNT_STS_33_PM 0x1821: 38 // CV_COUNT_STS_34_PM 0x1822: 37 // CV_COUNT_STS_35_PM 0x1823: 36 // CV_COUNT_STS_36_PM 0x1898: 35 // REI_COUNT_STS_25_PM 0x1899: 34 // REI_COUNT_STS_26_PM 0x189A: 33 // REI_COUNT_STS_27_PM 0x189B: 32 // REI_COUNT_STS_28_PM 0x189C: 31 // REI_COUNT_STS_29_PM 0x189D: 30 // REI_COUNT_STS_30_PM 0x189E: 29 // REI_COUNT_STS_31_PM 0x189F: 28 // REI_COUNT_STS_32_PM 0x18A0: 27 // REI_COUNT_STS_33_PM 0x18A1: 26 // REI_COUNT_STS_34_PM 0x18A2: 25 // REI_COUNT_STS_35_PM 0x18A3: 24 // REI_COUNT_STS_36_PM 0x1918--0x1923 // RECEIVED_RDI_STS_[25:36] 0x193C: 11 // REC_C2_STS_25, // REC_C2_STS_26 0x193D: 10 // REC_C2_STS_27, // REC_C2_STS_28 0x193E: 9 // REC_C2_STS_29, // REC_C2_STS_30 0x193F: 8 // REC_C2_STS_31, // REC_C2_STS_32 0x1940: 7 // REC_C2_STS_33, // REC_C2_STS_34 0x1941: 6 // REC_C2_STS_35, // REC_C2_STS_36 0x196C: 5 // REC_PDI_STS_25, // REC_PDI_STS_26 0x196D: 4 // REC_PDI_STS_27, // REC_PDI_STS_28 0x196E: 3 // REC_PDI_STS_29, // REC_PDI_STS_30 0x196F: 2 // REC_PDI_STS_31, // REC_PDI_STS_32 0x1970: 1 // REC_PDI_STS_33, // REC_PDI_STS_34 0x1971: 0 // REC_PDI_STS_35, // REC_PDI_STS_36 Agere Systems Inc. 153 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) The following PP registers are in RX_CLK4 domain: 0x1025: 149 // ELASTIC_STORE_OVERRUN_4 0x1215: 148 // ELASTIC_STORE_OVERRUN_MASK_4 0x1035: 147 // SF_P_4 0x1225: 146 // SF_P_MASK_4 0x1045: 145 // RDI_P_4 0x1235: 144 // RDI_P_MASK_4 0x1115: 143 // RDI_DELTA_P_4 0x1295: 142 // RDI_DELTA_P_MASK_4 0x1385: 141 // RDI_PERSIST_P_4 0x13C5: 140 // RDI_DELTA_STATE_P_4 0x1055: 139 // PLM_P_4 0x1245: 138 // PLM_P_MASK_4 0x1125: 137 // PLM_DELTA_P_4 0x12A5: 136 // PLM_DELTA_P_MASK_4 0x138D: 135 // PLM_PERSIST_P_4 0x13CD: 134 // PLM_DELTA_STATE_P_4 0x1065: 133 // UNEQ_P_4 0x1255: 132 // UNEQ_P_MASK_4 0x1135: 131 // UNEQ_DELTA_P_4 0x12B5: 130 // UNEQ_DELTA_P_MASK_4 0x1395: 129 // UNEQ_PERSIST_P_4 0x13D5: 128 // UNEQ_DELTA_STATE_P_4 0x1075: 127 // AIS_P_4 0x1265: 126 // AIS_P_MASK_4 0x1145: 125 // AIS_DELTA_P_4 0x12C5: 124 // AIS_DELTA_P_MASK_4 0x139D: 123 // AIS_PERSIST_P_4 0x13DD: 122 // AIS_DELTA_STATE_P_4, PDI_DELTA_STATE_P_4 0x1085: 121 // LOP_P_4 0x1275: 120 // LOP_P_MASK_4 0x1155: 119 // LOP_DELTA_P_4 0x12D5: 118 // LOP_DELTA_P_MASK_4 0x13A5: 117 // LOP_PERSIST_P_4 154 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x13E5: 116 // LOP_DELTA_STATE_P_4 0x1105: 115 // PDI_P_4 0x1285: 114 // PDI_P_MASK_4 0x1175: 113 // PDI_DELTA_P_4 0x12ED: 112 // PDI_DELTA_P_MASK_4 0x13AD: 111 // PDI_PERSIST_P_4 0x1185: 110 // SS_NEW_VLD_4 0x12FD: 109 // SS_NEW_VLD_MASK_4 0x118B: 108 // SS_MISMATCH_4 0x12E6: 107 // SS_MISMATCH_MASK_4 0x1505: 106 // EXP_CONC_4 0x150A: 105 // CONC_EN_4 0x1515: 104 // REC_CONC_4 0x1545: 103 // PATH_AIS_INS_4 0x154A: 102 // UNEQ_AIS_INS_4 0x154F: 101 // PLM_AIS_INS_4 0x1554: 100 // TIM_AIS_INS_4 0x1585: 99 // SS_INSERT_CONTROL_4 0x158A: 98 // E1_F1_INSERT_CONTROL_4 0x158F: 97 // E2_INSERT_CONTROL_4 0x134D: 96 // REC_F2_4, // REC_H4_4 0x134E: 95 // REC_Z3_4, // REC_Z4_4 0x134F: 94 // REC_Z5_4 0x1350: 93 // F2_VLDP_4 H4Z3Z4_VLDP_4 Z5_VLDP_4 CH_SEL_4 0x1357: 92 // REC_SS_4_TSLOT[1:6] 0x1358: 91 // REC_SS_4_TSLOT[7:12] 0x1612--0x1617 // EXP_C2_STS_[37:48] 0x15A5: 84 // PDI_VALIDATE_ENABLE_4 0x161B: 83 // COUNT_BB_ERRORS_SEL_4 0x1580: 82 // SONET_SDH_RULES_4 0x1626: 81 // SS_BITS_SETTING_[37:42] 0x1627: 80 // SS_BITS_SETTING_[43:48] 0x1662--0x1667 // E1_F1_INSERT_BYTE_[37:48] 0x166B: 73 // E2_INSERT_BYTE_4 Agere Systems Inc. 155 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x1597: 72 // TIM_P_INSERT_CONTROL_4 0x1685: 71 // SD_INSERT_4 0x16B4: 70 // SF_THRESH_SEL_STS_37 0x16B5: 69 // SF_THRESH_SEL_STS_38 0x16B6: 68 // SF_THRESH_SEL_STS_39 0x16B7: 67 // SF_THRESH_SEL_STS_40 0x16B8: 66 // SF_THRESH_SEL_STS_41 0x16B9: 65 // SF_THRESH_SEL_STS_42 0x16BA: 64 // SF_THRESH_SEL_STS_43 0x16BB: 63 // SF_THRESH_SEL_STS_44 0x16BC: 62 // SF_THRESH_SEL_STS_45 0x16BD: 61 // SF_THRESH_SEL_STS_46 0x16BE: 60 // SF_THRESH_SEL_STS_47 0x16BF: 59 // SF_THRESH_SEL_STS_48 0x1705: 58 // LAST_INT_INC_4 0x1715: 57 // LAST_INT_DEC_4 0x1745: 56 // LAST_GEN_INC_4 0x1755: 55 // LAST_GEN_DEC_4 0x1785: 54 // ONE_BIT_RDI_PM_4 0x1795: 53 // ERDI_PAYLOAD_PM_4 0x17A5: 52 // ERDI_CONNECT_PM_4 0x17B5: 51 // ERDI_SERVER_PM_4 0x17C5: 50 // UNEQ_P_PM_4 0x17D5: 49 // AIS_P_PM_4 0x17E5: 48 // LOP_P_PM_4 0x1824: 47 // CV_COUNT_STS_37_PM 0x1825: 46 // CV_COUNT_STS_38_PM 0x1826: 45 // CV_COUNT_STS_39_PM 0x1827: 44 // CV_COUNT_STS_40_PM 0x1828: 43 // CV_COUNT_STS_41_PM 0x1829: 42 // CV_COUNT_STS_42_PM 0x182A: 41 // CV_COUNT_STS_43_PM 0x182B: 40 // CV_COUNT_STS_44_PM 0x182C: 39 // CV_COUNT_STS_45_PM 156 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued) 0x182D: 38 // CV_COUNT_STS_46_PM 0x182E: 37 // CV_COUNT_STS_47_PM 0x182F: 36 // CV_COUNT_STS_48_PM 0x18A4: 35 // REI_COUNT_STS_37_PM 0x18A5: 34 // REI_COUNT_STS_38_PM 0x18A6: 33 // REI_COUNT_STS_39_PM 0x18A7: 32 // REI_COUNT_STS_40_PM 0x18A8: 31 // REI_COUNT_STS_41_PM 0x18A9: 30 // REI_COUNT_STS_42_PM 0x18AA: 29 // REI_COUNT_STS_43_PM 0x18AB: 28 // REI_COUNT_STS_44_PM 0x18AC: 27 // REI_COUNT_STS_45_PM 0x18AD: 26 // REI_COUNT_STS_46_PM 0x18AE: 25 // REI_COUNT_STS_47_PM 0x18AF: 24 // REI_COUNT_STS_48_PM 0x1924--0x192F // RECEIVED_RDI_STS_[37:48] 0x1942: 11 // REC_C2_STS_37, // REC_C2_STS_38 0x1943: 10 // REC_C2_STS_39, // REC_C2_STS_40 0x1944: 9 // REC_C2_STS_41, // REC_C2_STS_42 0x1945: 8 // REC_C2_STS_43, // REC_C2_STS_44 0x1946: 7 // REC_C2_STS_45, // REC_C2_STS_46 0x1947: 6 // REC_C2_STS_47, // REC_C2_STS_48 0x1972: 5 // REC_PDI_STS_37, // REC_PDI_STS_38 0x1973: 4 // REC_PDI_STS_39, // REC_PDI_STS_40 0x1974: 3 // REC_PDI_STS_41, // REC_PDI_STS_42 0x1975: 2 // REC_PDI_STS_43, // REC_PDI_STS_44 0x1976: 1 // REC_PDI_STS_45, // REC_PDI_STS_46 0x1977: 0 // REC_PDI_STS_47, // REC_PDI_STS_48 Agere Systems Inc. 157 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Performance Monitor (PM) Reset A PM reset signal is sent to all blocks for performing monitoring (collecting statistics). A PM reset signal can come from external pins, internal 1 second timer, or be controlled by software, depending on the PM mode, MPU_PMMODE[1:0] bits (Table 31). Table 23. PM Reset Signal Provisioning MPU_ PMMODE[1:0] (Table 31) 00 01 Description PM Reset Signal Comes from External Pin (1 Hz, 50% Duty Cycle Signal). PM Reset Signal Comes from Internal 1 Second Counter (1 Hz, 50% Duty Cycle Signal). Writing a logic 1 to the PM reset signal bit MPU_PM_TRIGGER_SWRS (Table 29) in this mode will reset the counter so that a 01 transition occurs on the PM reset signal within 10 clock cycles of the 77.76 MHz clock. PM Reset Signal Is Software Controlled. Writing a logic 1 to the PM reset signal bit MPU_PM_TRIGGER_SWRS will cause a 01 transition on the internal PM reset signal. This pulse will be high for 100 cycles of the 77.76 MHz clock and low for 100 cycles of the 77.76 MHz clock. Writing the PM reset signal bit to a logic 1 during this 200 clock cycle interval will have no effect (2.57 s). The PM reset signal rising edge must occur within 10 clock cycles of writing the PM reset signal bit. 11 The external PMRST pin is a bidirectional signal controlled by the MPU_PMRST_OE bit (Table 31). This bit defaults to 0, making the pin an input. 158 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Performance Monitor (PM) Reset (continued) PMRSTI EXTERNAL (MPU_PMMODE[1:0] = 00) IPMRST(TO BLOCKS) MPU_SWRSR REGISTER MPU_PM_TRIGGER_SWRS BIT MPU_PM_TRIGGER_SWRS MPU_MPCLK DELAY SOFTWARE CONTROLLED (MPU_PMMODE[1:0] = 11) PMRSTO CLK78M FREE RUNNING (MPU_PMMODE[1:0] = 01) PMRST PIN 1/2 SECOND COUNTER MPU_PROVISION0 REGISTER MPU_PMMODE[1:0] BITS MPU_PMMODE[1:0] MPU_MPCLK MPU_PROVISION0 REGISTER MPU_PMRST_OE BIT MPU_MPCLK MPU_PMRST_OE MPU BLOCK 5-8157(F)r.1 Figure 14. PM Reset Signal Generation Agere Systems Inc. 159 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) General-Purpose Input/Output Interface The programmable I/O general-purpose input/output (GPIO) consists of four device pins that can be used for internal block state observation. There functionality is controlled by MPU_GPIO_MODE[3:0] bits (Table 34). MPU_GPIO_MODE[3:0] = 0000 normal mode MPU_GPIO_MODE[3:0] = others undefined Mode 0 (normal mode): In normal mode, GPIO pins can be programmed individually to be either input or output through MPU_GPIO_DIR_CTL[3:0] bits (Table 34). Figure 15 shows pictorially the GPIO functionality. These pins are useful for board designers who need the ability to monitor or control signals on their boards. If the pin is an input, the value on the pin can be read from MPU_GPIO_I_CND[3:0] bits (Table 26). It can also be programmed to generate a level-sensitive interrupt or a positive-edge detect interrupt contributing to the external interrupt pin. If the pin is an output, the value provisioned in MPU_GPIO_O_CTL[3:0] bits (Table 30) will appear on the device pin immediately. 160 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) General-Purpose Input/Output Interface (continued) Programmable I/O Bus 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0008 0x000A 0x000C 0x000E 0x000F 0x0010 0x0012 0x0013 0x001F VERSION NAME = TADMVC2G52 IRQ GPIO INPUT 3 2 1 0 3 2 1 0 GPIO OUT INTERRUPTS GPIO INPUTS IRQ MASKS 3 2 1 0 + MPU_GPIOCFG ONE SHOTS GPIO OUTPUTS LINE PROVISION LOOPBACK GPIO MODE GPIO MODE ACTIVE H/L 3 2 1 0 LEVEL/EDGE 3 2 1 0 DIRECTION 3 2 1 0 POSITIVE EDGE DET STM_DCC_RX_CLK STM_DCC_TX_CLK SCRATCH STM_DCC_RX_DATA STM_DCC_TX_DATA STM/DCC MODE 2 0 MODE 1 INPUT 2 INPUT 1 OUTPUT ENABLE CONTROLS: NORMAL MODE 0 EN = MPU_GPIO_MODE[3:0] STM/DCC MODE 2 EN = 0111 GPIO3 PIN GPIO2 PIN GPIO1 PIN GPIO0 PIN 5-8158(F).a Figure 15. General Input/Output (GPIO) Agere Systems Inc. INPUT 0 INPUTS 161 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) Interrupts The interrupt functionality is shown in Figure 16. 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0008 0x000A 0x000C 0x000E 0x000F 0x0010 0x0012 0x0013 0x0014 0x0015 0x001F VERSION IRQ[1] (PT) IRQ[0] (TOHP) PMIRQ DE IRQ 3 2 1 0 UT PM PT OH NAME = TADMVC2G52 IRQ[3] (UT) IRQ[2] (DE) SYNC_ERR (GPIO) IRQ MASKS 3210 INTERRUPTS GPIO INPUTS IRQ MASKS ONE SHOTS GPIO OUTPUTS LINE PROVISION LOOPBACK GPIO MODE GPIO SELECT[1:0] GPIO SELECT[3:2] SCRATCH INT 5-7409(F).a Figure 16. Interrupt Functionality 162 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) Loopback Operation Figure 17 illustrates the different types of loopback provided in the device. SOURCE LAYER 2 5-7411(F)r.2TDAT16 SINK FACILITY TERMINAL NEAR END LAYER 2 TOHP OPTICS OPTICS TOHP LINE LINE DE DE PP PP UT CONT FACILITY (OPTICS) CONT TERMINAL B TERMINAL A Figure 17. Loopback Operation In the following description, only the data path from A to B is discussed, but the same terms apply to the reverse direction. Near-End Loopback (NELB) The packet/cell payload is looped back to the data source (layer 2 device) as soon as it crosses the layer 1 to layer 2 mapping (UTOPIA block). Terminal Loopback The SDH signal is looped back to the terminal at the end of the piece of equipment (before it is transmitted onto the facility). Facility Loopback The optical signal is looped back to the facility as soon as it enters the terminal. Agere Systems Inc. UT 163 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) MPU Register Descriptions Table 24. MPU_VERR[0--5], Version Control Registers (RO) Address 0x0000 Bit 15:0 Name MPU_VER0 Function Indicates version number for version 2.0. Indicates version number for version 2.2. Indicates version number for version 2.3. 0x0001 0x0002 0x0003 0x0004 0x0005 15:0 15:0 15:0 15:0 15:0 MPU_VER1 MPU_VER2 MPU_VER3 MPU_VER4 MPU_VER5 Indicates version number. ASCII T A. Indicates version number. ASCII D M. Indicates version number. ASCII 0 4. Indicates version number. ASCII 2 G. Indicates version number. ASCII 5 CR. Reset Default 0x0207 0x0227 0x0237 0x5441 0x444D 0x3034 0x3247 0x350D 164 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 25. MPU_ISR, Interrupt Status Register (RO or COR/W) Address 0x0008 Bit 15 Name MPU_SYNC_ERR_IS Function Sync Error Interrupt (RO). This is a read-only bit. This bit is set when the TXFSYNCP/N pins (U3, U1) are not driven by a 2 kHz or greater frame sync signal. When the TXFSYNCP/N pins are not used, simply ignore this interrupt by setting the corresponding mask bit MPU_SYNC_ERR_IM (Table 27) so that the interrupt does not contribute to the MPU_INTN pin (B7). This bit can be cleared by setting bit MPU_SYNC_ERR_ICLR (Table 28). Reserved. PP Composite Interrupt (RO). When set, indicates that an interrupt from the PP block is active. General-Purpose Inputs Interrupt (RO or COR/W). Signal indicating the associated input is active. When the GPIO are outputs, this signal will be forced low. These interrupts are COR/COW when the interrupt is programmed to the positive edge mode; otherwise, this is a read-only (RO) location. UTOPIA Composite Interrupt (RO). Active-high signal indicating an unmasked delta or event is active in the UTOPIA block. Data Engine Composite Interrupt (RO). Active-high signal indicating an unmasked delta or event is active in the data engine block. Performance-Monitor Reset Interrupt (COR/W). Active-high signal indicating a 1 second event has occurred. Reserved. DS3 Composite Interrupt (RO). When set, indicates that an interrupt from the DS3 block is active. RXT Composite Interrupt (RO). When set, indicates that an interrupt from the RXT block is active. Path Terminator Composite Interrupt (RO). Activehigh signal indicating an unmasked delta or event is active in the path terminator block. Transport Overhead Processor Composite Interrupt (RO). Active-high signal indicating an unmasked delta or event is active in the transport overhead processor block. Reset Default X 14:13 12 11:8 -- MPU_PP_IS MPU_GPI_IS[3:0] 7 MPU_UT48_IS 6 MPU_DE48_IS 5 MPU_PMRST_IS 4 3 2 1 -- MPU_DS3_IS MPU_RXT_IS MPU_PT48_IS 0 MPU_TOHP48_IS Agere Systems Inc. 165 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 26. MPU_CNDR, Condition Register (RO) Address 0x000A Bit 15:4 3:0 Name -- MPU_GPIO_I_CND[3:0] Reserved. General-Purpose Input Value. These values are direction connections between the GPIO[3:0] input pins and the register map. The value at the GPIO pins is latched when this register is read. Function Reset Default -- N/A Table 27. MPU_IMR, Interrupt Mask Register (R/W) Address 0x000C Bit 15 Name MPU_SYNC_ERR_IM Function Sync Error Interrupt Mask. When set (active-high), the associated interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN). Reserved. Pointer Processor Composite Interrupt Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN). General-Purpose Inputs Composite Interrupt Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN). UTOPIA Composite Interrupt Mask. When set (activehigh), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN). Data Engine Composite Interrupt Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN). Performance-Monitor Composite Reset Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN). Reset Default 1 14:13 12 -- MPU_PP_IM 11 1 11:8 MPU_GPI_IM[3:0] 1111 7 MPU_UT48_IM 1 6 MPU_DE48_IM 1 5 MPU_PMRST_IM 1 166 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 27. MPU_IMR, Interrupt Mask Register (R/W) (continued) Address 0x000C Bit 4 3 Name -- MPU_DS3_IM Reserved. DS3 Composite Interrupt Mask. When set (activehigh), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin MPU_INTN (pin B7). Receive Terminator Composite Interrupt Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin MPU_INTN. Path Terminator Composite Interrupt Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin MPU_INTN. Transport Overhead Processor Composite Interrupt Mask. When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt pin MPU_INTN. Function Reset Default -- 1 2 MPU_RXT_IM 1 1 MPU_PT48_IM 1 0 MPU_TOHP48_IM 1 Table 28. MPU_ICLRR, Interrupt Clear Register (R/W) Address 0x000D Bit 15 Name Function Reset Default 0 MPU_SYNC_ERR_ICLR Sync Error Interrupt Clear. When this bit is set, interrupt status bit MPU_SYNC_ERR_IS (Table 25) will be cleared. -- Reserved. 14:0 0 Table 29. MPU_SWRSR, Software Reset Register (R/W) Address 0x000E Bit 15:8 7 Name -- Reserved. Function Reset Default 0 0 MPU_PM_TRIGGER_SWRS Performance-Monitor Reset Trigger. This bit is used in software controlled mode to generate a PM reset signal pulse. It is also used in free-running mode to synchronize the PM reset signal pulse. To generate the trigger, write 1, then write 0 to this bit. -- MPU_RST_SWRS Reserved. Software Reset. Writing 1 to this bit will reset the device. This bit will clear itself. 6:1 0 0 0 Agere Systems Inc. 167 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 30. MPU_GPIO_CTLR, GPIO Output Value (R/W) Address 0x000F Bit 15:4 3:0 Name -- MPU_GPIO_O_CTL[3:0] Reserved. General-Purpose Output Values. The value written into these registers will appear on the associated output. Function Reset Default 0 0000 Table 31. MPU_PROVISION0, Provisioning Register 0 (R/W) Address 0x0010 Bit 15 Name MPU_PMRST_OE Function PMRST Output Enable. Controls the 3-state buffer that drives the external PMRST (pin D7). If 0, the buffer is disabled, and PMRST is input. If 1, PMRST is output. Reserved. Performance-Monitoring Mode. 00 or 10 = PM reset signal comes from external pin; 01 = PM reset signal comes from internal 1 second counter; 11 = PM reset signal is software controlled. Reserved. Clear-on-Read/Clear-on-Write Control for MPU Registers. 1 = COR, 0 = COW. Reserved. OC-48/OC-3 Mode for Internal System Clock Divisor. 1 = OC-48, 0 = OC-12 and OC-3. Reserved. Reset Default 0 14:10 9:8 -- MPU_PMMODE[1:0] 00100 00 7 6 5 4 3:0 -- MPU_COR_COW_CTL -- -- -- 0 0 1 1 0 Table 32. MPU_PROVISION1, Provisioning Register 1 (R/W) Address 0x0011 Bit 15 14:12 11 10:8 7 6:4 3 2:0 168 Name MPU_EQA -- MPU_EQB -- MPU_EQC -- MPU_EQD -- Function Equip Channel A. 1 = enable; 0 = disable. Turn off clock in receive direction, no effect in transmit direction. Reserved. Equip Channel B. 1 = enable; 0 = disable. Turn off clock in receive direction, no effect in transmit direction. Reserved. Equip Channel C. 1 = enable; 0 = disable. Turn off clock in receive direction, no effect in transmit direction. Reserved. Equip Channel D. 1 = enable; 0 = disable. Turn off clock in receive direction, no effect in transmit direction. Reserved. Reset Default 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 33. MPU_LPBKCTLR, Loopback Control Register (R/W) Address 0x0012 Bit 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Name MPU_LPBKD[3:2] MPU_LPBKA[1:0] MPU_LPBKC[3:2] MPU_LPBKB[1:0] MPU_LPBKB[3:2] MPU_LPBKC[1:0] MPU_LPBKA[3:2] MPU_LPBKD[1:0] Function Loopback Control. SONET facility and terminal loopback are only available in STS-3/STM-1 and STS-12/STM-4 modes. For MPU_LPBK[A--D][1:0]: 00 = No loopbacks. 01 = SONET facility loopback. 10 = SONET terminal loopback. 11 = Reserved. For MPU_LPBK[D--A][3:2]: 00 = No loopbacks. 01 = Reserved. 10 = UTOPIA near-end loopback. 11 = Reserved. Table 34. MPU_GPIOCFG, GPIO Configuration Register (R/W) Address 0x0013 Bit 15:12 Name MPU_GPIO_MODE[3:0] GPIO Mode. 0000 = Normal mode. Enables all four GPIO signals. 0001 = Reserved. Else = Undefined. 11:8 MPU_GPIO_POL[3:0] GPIO Interrupt Active State. 0 = report received value unchanged. (Level = input pin value, positive edge = 1 when signal rises); 1 = invert received value (level = invert input pin value, positive edge = 0 when detected). GPIO Interrupt Type. 0 = positive edge; 1 = level. 0000 Function Reset Default 0000 Reset Default 00 00 00 00 00 00 00 00 7:4 3:0 MPU_GPIO_ITYPE[3:0] 0000 0000 MPU_GPIO_DIR_CTL[3:0] GPIO Direction Control. 0 = input; 1 = output. Agere Systems Inc. 169 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 35. MPU_GPIO_OER[1--2], GPIO Output Enable (R/W) Address 0x0014 Bit 15:9 8 7:1 0 0x0015 15:9 8 7:1 0 Name -- Reserved. Function Reset Default 0x0000 MPU_GPIO1_OE GPIO1 Output Enable. Write 1 to enable output. Write 0 to 3-state the output. -- Reserved. MPU_GPIO0_OE GPIO0 Output Enable. Write 1 to enable output. Write 0 to 3-state the output. -- Reserved. 0x0000 MPU_GPIO3_OE GPIO3 Output Enable. Write 1 to enable output. Write 0 to 3-state the output. -- Reserved. MPU_GPIO2_OE GPIO2 Output Enable. Write 1 to enable output. Write 0 to 3-state the output. 170 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 36. MPU_PDN1, Powerdown Register 1 (R/W) Note: A read or write should not be performed to blocks that are powered down, since it may not be completed. The MPU_DTN signal may not be generated for blocks that are powered down. Address 0x001B Bit 15:14 13 12:9 8 7:6 5 4 3 2 1:0 Name -- MPU_LI_PDN -- -- -- MPU_PAY_TXCLKPDN Reserved. Power Down the Line Interface Block. 1 = powerdown. Reserved. Must Be Set to 1. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 00 Power Down PAY Transmit Clock. 1 = powerdown. MPU_PAY_RXCLKPDN Power Down PAY Receive Clock. 1 = powerdown. MPU_SON_TOH_SYCLKPDN Power Down the TOH System Clock. 1 = powerdown. MPU_SON_PP_SYCLKPDN Power Down the PP System Clock. 1 = powerdown. -- Must Be Set to 11. Table 37. MPU_PDN2, Powerdown Register 2 (R/W) Address 0x001D Bit 15:12 11:0 Name -- -- Reserved. Must Be Set to 0xFFF. Function Reset Default 0000 0x000 Table 38. MPU_PDN3, Powerdown Register 3 (R/W) Address 0x001E Bit 15:12 11:0 Name -- -- Reserved. Must Be Set to 0xFFF. Function Reset Default 0000 0x000 Table 39. MPU_SCRATCHR, Scratch Register (R/W) Address 0x001F Bit 15:0 Name Function Reset Default 0x0 MPU_SCRATCH[15:0] Read/Write Register with No Other Internal Connections. Table 40. MPU_TDAT16_MODER, MARS2G5 P-Pro Mode Selection Register (R/W) Address 0x0020 Bit 15:1 0 Name -- -- Reserved. Must Be Set to 1. Function Reset Default 0 0 171 Agere Systems Inc. MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) MPU Register Descriptions (continued) Table 41. MPU_LI_MODER, Register (R/W)* Address 0x0021 Bit 15:12 11 10 9 8 7 6 Name -- Reserved. Function Reset Default 0 0 0 0 0 0 0 MPU_LI_MODE[11:0] Channel A OC-12 and OC-3 Enable. 1 = enable, 0 = disable. Channel B OC-12 and OC-3 Enable. 1 = enable, 0 = disable. Channel C OC-12 and OC-3 Enable. 1 = enable, 0 = disable. Channel D OC-12 and OC-3 Enable. 1 = enable, 0 = disable. Additional Delay in PLL Feedback Path When Set to 1. POF/SONET Select. 1 = packet over fiber (POF), 0 = SONET. Note: For proper operation of POF mode, register 0x400F bit 5 (Table 263) and register 0x5801 (Table 680) need to be configured correctly. 5 PLL On/Off Select. Controls the transmit line clock PLL used for STS-48/STM-16 contraclocking mode. 1 = PLL off (inactive), 0 = PLL on (active). OC-48/OC-3 Mode for Internal System Clock Divisor. 1 = OC-48, 0 = OC-12 and OC-3. Channel A OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3. Channel B OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3. Channel C OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3. Channel D OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3. 1 4 3 2 1 0 1 0 0 0 0 * For normal OC-12 operation write 0x0F0F, normal OC-3 operation write 0x0F00, and normal OC-48 operation write 0x0010. For OC-48 mode, channels A, B, C, and D are always enabled (on). There is no way to disable them in OC-48 mode. Table 42. MPU_HSI_TST_CTL, High-Speed Interface Control Address 0x0030 Bit 15 14 13:11 10:8 7:0 Name -- -- -- -- -- Reserved. Must Be Set to 1. Reserved. Reserved. Reserved. Function Reset Default 0 0 000 110 0x00 Table 43. MPU_HSI_LPBKR, High-Speed Interface Loopback Register Address 0x0032 Bit 15:12 11:0 Name -- -- Reserved. Must Be Set to 0xFFF. Function Reset Default 0x0 0x000 172 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Microprocessor (MPU) Interface (continued) MPU Register Map Table 44. MPU Register Map Note: Shading denotes reserved bits. Addr 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 Symbol MPU_VER0 MPU_VER1 MPU_VER2 MPU_VER3 MPU_VER4 MPU_VER5 -- -- MPU_ISR Type RO RO RO RO RO RO -- -- RO or COR/W -- R/W -- R/W MPU_ SYNC_ ERR_IM MPU_ SYNC_ER R_ICLR MPU_PM_ TRIGGER _SWRS MPU_GPIO_O_CTL[3:0] MPU_ PMRST_ IOCTL MPU_EQA MPU_LPBKD[3:2] MPU_LPBKA[1:0] MPU_EQB MPU_LPBKC[3:2] MPU_LPBKB[1:0] MPU_PMMODE[1:0] MPU_ COR_CO W_CTL MPU_EQC MPU_LPBKB[3:2] MPU_LPBKC[1:0] -- MPU_ RST_ SWRS MPU_ PP_IM MPU_ GP_IM3 MPU_ GP_IM2 MPU_ GP_IM1 MPU_ GP_IM0 MPU_ UT48_IM MPU_ DE48_IM MPU_ PMRST_ IM MPU_ DS3_IM MPU_ RXT_IM MPU_ PT48_IM MPU_ TOHP48_ IM MPU_GPIO_I_CND[3:0] MPU_ SYNC_ ERR_IS MPU_ PP_IS MPU_GP_IS[3:0] MPU_ UT48_IS MPU_ DE48_IS MPU_ PMRST_ IS MPU_ DS3_IS MPU_ RXT_IS MPU_ PT48_IS MPU_ TOHP48_ IS Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 0x41 = A 0x4C = M 0x34 = 4 0x47 = G 0x0D = CR Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 VERSION = 0x01 0x54 = T 0x44 = D 0x30 = 0 0x32 = 2 0x35 = 5 0x0009 0x000A 0x000B 0x000C -- MPU_CNDR -- MPU_IMR 0x000D MPU_ICLRR R/W 0x000E MPU_SWRSR R/W 0x000F 0x0010 MPU_GPIO_CTLR MPU_PROVISION0 R/W R/W 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 -- 0x001A MPU_PROVISION1 MPU_LPBKCTLR MPU_GPIOCFG MPU_GPIO_OER1 MPU_GPIO_OER2 -- R/W R/W R/W R/W R/W -- MPU_EQD MPU_LPBKA[3:2] MPU_LPBKD[1:0] MPU_GPIO_MODE[3:0] MPU_GPIO_POL[3:0] MPU_GPI O1_OE MPU_GPI O3_OE MPU_GPIO_ITYPE[3:0] MPU_GPIO_DIR_CTL[3:0] MPU_GPI O0_OE MPU_GPI O2_OE Agere Systems Inc. 173 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Microprocessor (MPU) Interface (continued) MPU Register Map (continued) Table 44. MPU Register Map (continued) Note: Shading denotes reserved bits. Addr 0x001B Symbol MPU_PDN1 Type R/W Bit 15 Bit 14 Bit 13 MPU_LI_P DN Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 MPU_PAY _TXCLKP DN Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MPU_PAY MPU_SON MPU_SON _RXCLKP _TOH_SY _PP_SYC DN CLKPDN LKPDN 0x001C-- 0x001E 0x001F 0x0020 0x0021 0x0022-- 0x07FF -- MPU_SCRATCHR -- MPU_LI_MODER -- -- R/W -- R/W -- MPU_LI_MODE[11:0] MPU_SCRATCH[15:0] 174 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Functional Description The block diagram for the MARS2G5 P-Pro indicating the signal pins per block is shown in Figure 18. TXCLKQP/N, TXCLKP/N, AND TXF 6 TXTOH 6 350 SIGNAL PINS TXLINE TXD ECL REF RXD RXC 32 2 32 2 4 x 24 UTOPIA INTERFACE TX UTOPIA 4 x 24 RX UTOPIA RXLINE OHP PP DE UT CTRL 12 RXREF RXTOH 43 6 4 JTAG ALM/GPIO MPU INTERFACE 5-7396(F)r.2TDAT162 Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block Agere Systems Inc. 175 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Line Interface This block provides the interface between the SONET/SDH line and the transport overhead (TOH) processing block. The line interface must provide transmit/receive functions for quad OC-3, quad OC-12, and single OC-48 applications. All external inputs and outputs for the MARS2G5 P-Pro line I/O block are referenced to the positive edge of the clock. The following is a list of the receive line interface functions: The quad OC-3 application consists of four differential PECL 155.52 Mbits/s data inputs and four 155.52 MHz differential clocks from an optical transceiver. The quad OC-12 application consists of four differential PECL 622.08 Mbits/s data inputs and four 622.08 MHz differential clocks from an optical transceiver. The OC-48 application consists of 16 differential PECL data inputs at 155.52 Mbits/s with a single differential PECL 155.52 MHz clock. The transmit interface performs the following functions: The quad OC-3 application consists of four differential PECL 155.52 Mbits/s data outputs to an optical transceiver. A SONET compliant 155 MHz differential PECL clock input is required in this mode. The quad OC-12 application consists of four each: a differential PECL 622.08 Mbits/s data to an optical transceiver. A SONET compliant 622 MHz differential PECL clock input is required in this mode. The OC-48 application consists of 16 differential PECL data outputs at 155.52 Mbits/s with a differential PECL 155.52 MHz clock. The 8k frame sync is a clock cycle wide pulse latched in at the system rate (622.08 MHz or 155.52 MHz). This signal will set the transmit frame location. If this signal is kept low, the transmit frame will free-run at the 8 kHz rate. The line interface also supports loopback functions: In the quad OC-3 and quad OC-12 applications, the line interface supports both terminal and facility loopback on a per-port basis. 176 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Line Interface (continued) This device is designed to work with commonly available multiplexer and demultiplexer chipsets for STS-3, STS12, and STS-48 line interface rates. The line interface will operate in one of three possible modes. Table 45. Line Interface Modes MPU_LI_MODE[4:0] 0x0021 (Table 41) 10000 01111 Interfaces OC-48 OC-12 Line Interface Signals RXCLK[P/N], RXD[15:0], TXCLK[P/N], TXD[15:0] RXCLKD[P/N], RXDD[P/N], TXCLK[P/N], TXDD[P/N] RXCLKC[P/N], RXDC[P/N], TXCLK[P/N], TXDC[P/N] RXCLKB[P/N], RXDB[P/N], TXCLK[P/N], TXDB[P/N] RXCLKA[P/N], RXDA[P/N], TXCLK[P/N], TXDA[P/N] RXCLKD[P/N], RXDD[P/N], TXCLK[P/N], TXDD[P/N] RXCLKC[P/N], RXDC[P/N], TXCLK[P/N], TXDC[P/N] RXCLKB[P/N], RXDB[P/N], TXCLK[P/N], TXDB[P/N] RXCLKA[P/N], RXDA[P/N], TXCLK[P/N], TXDA[P/N] 00000 OC-3 TXCLKP TXCLKN TXD[15:0] VALID RXCLK[A:D]P RXCLK[A:D]N RXD[15:0] VALID 5-7418(F)r.2 Figure 19. Line Interface Agere Systems Inc. 177 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Line Interface (continued) LVPECL I/O Termination and Load Specifications The LVPECL buffers are compatible with the temperature independent ECL 100K levels, but the output levels that are guaranteed are relaxed 30 mV from the actual 100K levels allowing for noise and variations in the power supply and process. All LVPECL output buffers require a terminating resistor. These terminating resistors, which must also be connected to both LVPECLREFHI and LVPECLREFLO, go to a common terminating voltage. All of the terminating resistors used with a chip must be identical precision (1%) resistors. The value of these terminating resistors is usually chosen to match the characteristic impedance of the board. To save on power, a terminating voltage equal to VDDD - 2 V is available in most ECL systems. The minimum value of the terminating resistor that can be used on these buffers is 50 . This is also the standard termination used in most ECL systems. Larger values of resistance will save power, but will also slow down the high-to-low transition of the output, since it is RC limited. If no VDDD - 2 V supply is available, a larger value resistor may be connected directly to GND. It should be chosen such that the current through it does not exceed the current through a 50 resistor to VDDD - 2 V (21 mA in the high state). This large resistor will most likely be a poor match to the board impedance. The match can be improved by the use of a Thevenin equivalent resistor pair. Such a Thevenin equivalent resistor will burn much more system power (but not on-chip power) than would a single resistor, but it does allow for impedance matching in the absence of a VDDD - 2 V supply. Termination resistor options are shown in Table 46 and Figure 20. Experienced ECL designers sometimes use the (bipolar) ECL output buffers in a tied-OR configuration. Unfortunately, this cannot be done with these LVPECL buffers. 178 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Line Interface (continued) LVPECL I/O Termination and Load Specifications (continued) Table 46. Nominal dc Power for Suggested Terminations Note: The value is the average of the high and low states in LVPECL output buffer and external terminating resistors, for a single-ended output. The values double for double-ended outputs. Terminating Resistor and Voltage 50 (RP) to VDDD - 2 V* 130 (R1) to VDDD and 82 (R2) to GND * Standard ECL termination (parallel). Thevenin equivalent of 50 to VDDD - 2 V. VDDD VDDD - 2 V RP RP R1 R1 VDDD Output Transistor (On-Chip) Power (mW) 15 15 Terminating Resistor (Off-Chip) Power (mW) 13 52 LVPECL OUTPUT LVPECL INPUT LVPECL OUTPUT LVPECL INPUT DIFFERENTIAL CONFIGURATION WITH PARALLEL TERMINATION R2 R2 DIFFERENTIAL CONFIGURATION WITH THEVENIN TERMINATION VDDD - 2 V VDDD - 1.3 V RP VDDD VDDD LVPECL OUTPUT LVPECL INPUT LVPECL OUTPUT R1 R2 LVPECL INPUT X X SINGLE-ENDED CONFIGURATION WITH PARALLEL TERMINATION R2 R1 SINGLE-ENDED CONFIGURATION WITH THEVENIN TERMINATION 1264(F)a Figure 20. LVPECL Load Connections Agere Systems Inc. 179 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Line Interface (continued) Line Interface I/O Timing Note: VDD = VDDA = VDDD (3.300 volts nominal) in this section. Figure 21, Figure 22, Table 47, and Table 48 give the timing specifications for the STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 interfaces. tRCCP tRCR RXCLKP/RXCLK[D--A]P VIH (MIN) 50% VIL (MAX) tRCF RXCLKN/RXCLK[D--A]N tRCPL tRCPH RXD[15:0]P/RXD[D--A]P tRSU tRH RXD[15:0]N/RXD[D--A]N 5-9252 (F).ar.2 Figure 21. Receive Line-Side Timing Waveform 180 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Line Interface (continued) Line Interface I/O Timing (continued) tTCCP tTCR TXCLKP VIH (MIN) 50% VIL (MAX) tTCF TXCLKN tTCPL tPDCC tTCPH TXD[15:0]P/TXD[D--A]P* 50% TXD[15:0]N/TXD[D--A]N* 5-9253(F).dr.1 * Loading of TXD[15:4][P/N] is 12 pF. Loading of TXD[3:0][P/N]/TXD[D:A][P/N] is 8 pF with the PLL on, and 12 pF with the PLL off. Figure 22. Transmit Line-Side Timing Waveform--OC-48 Contraclocking TXCLKP VIH (MIN) 50% VIL (MAX) TXCLKN tPDFC1 TXCLKQP 50% TXCLKQN tPDFC2 TXD[15:0]P/TXD[D--A]P* 50% TXD[15:0]N/TXD[D--A]N* tPDFC3 5-9253(F).fr.2 * Loading of TXD[15:4][P/N] is 12 pF. Loading of TXD[3:0][P/N]/TXD[D:A][P/N] is 8 pF with the PLL on, and 12 pF with the PLL off. Figure 23. Transmit Line-Side Timing Waveform--OC-48 Forward Clocking TXCLKP VIH (MIN) 50% VIL (MAX) TXCLKN tTFSSU TXFSYNCN tTFSH TXFSYNCP tTFSPW 5-9253(F).er.4 Figure 24. Transmit Line-Side Timing Waveform--Frame Sync Agere Systems Inc. 181 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Line Interface (continued) Line Interface I/O Timing (continued) For the following tables, VIL (max) = (VDD - 1.475) V, nominal of 1.825 V; VIH (min) = (VDD - 1.165) V, nominal of 2.135 V; VOH (min) = (VDD - 1.025) V, nominal of 2.275 V; VOL (max) = (VDD - 1.620) V, nominal of 1.680 V. Table 47. Receive Line-Side Timing Specifications Symbol tRCCP Parameter Receive Clock-Cycle Period: STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Receive Clock/Data Rise Time: OC-3 Mode OC-12 Mode OC-48 Mode Receive Clock/Data Fall Time: OC-3 Mode OC-12 Mode OC-48 Mode Receive Clock Pulse Low (for P input): STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Receive Clock Pulse High (for P input): STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Receive Data Setup Time: RXD[D--A][P/N] OC-3 Mode OC-12 Mode RXD[15:0][P/N] OC-48 Mode Receive Data Hold Time: RXD[D--A][P/N] OC-3 Mode OC-12 Mode RXD[15:0][P/N] OC-48 Mode Min -- -- 200 200 200 200 200 200 2.800 700 2.800 700 Typ 6.4300 1.60751 -- -- -- -- -- -- 3.2150 803.75 3.2150 803.75 Max -- -- 2200 600 1500 2200 600 1500 3.630 907 3.630 907 Units ns ns ps ps ps ps ps ps ns ps ns ps tRCR tRCF tRCPL tRCPH tRSU 600 400 500 -- -- -- -- -- -- ps ps ps tRH 600 400 1 -- -- -- -- -- -- ps ps ns 182 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Line Interface (continued) Line Interface I/O Timing (continued) Table 48. Transmit Line-Side Timing Specifications Note: The recommended termination for LVPECL outputs is 50 to a termination voltage equal to VDD - 2 V. Symbol tTCCP Parameter Transmit Clock-Cycle Period: STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Transmit Clock (TXCLK[P/N])/Transmit Frame Sync (TXFSYNC[P/N]) Rise Time: OC-3 Mode OC-12 Mode OC-48 Mode Transmit Clock (TXCLK[P/N])/Frame Sync (TXFSYNC[P/N]) Fall Time: OC-3 Mode OC-12 Mode OC-48 Mode Transmit Clock Pulse Low (for P input): STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Transmit Clock Pulse High (for P input): STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Propagation Delay--Contraclocking*: (TXCLK[P/N] to TXD[15:0][P/N], with PLL) Propagation Delay--Forward Clocking: (TXCLK[P/N] to TXCLKQ[P/N]) Propagation Delay--Forward Clocking: (TXCLKQ[P/N] to TXD[15:0][P/N], no PLL)* Propagation Delay--Forward Clocking: (TXCLK[P/N] to TXD[15:0][P/N], no PLL) TXFSYNC[P/N] Setup Time: OC-3 Mode OC-12 Mode OC-48 Mode (no PLL) OC-48 Mode (with PLL) TXFSYNC[P/N] Hold Time: OC-3 Mode OC-12 Mode OC-48 Mode (no PLL) OC-48 Mode (with PLL) Transmit TXFSYNC[P/N] Width: STS-3/STM-1 and STS-48/STM-16 STS-12/STM-4 Min -- -- Typ 6.4300 1.60751 Max -- -- Unit ns ns tTCR 200 200 200 -- -- -- 2200 600 1500 ps ps ps tTCF 200 200 200 2.800 700 2.800 700 1 1.5 0 2 600 400 0 2 600 400 2 0 6.430 1.608 -- -- -- 3.2150 803.75 3.2150 803.75 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2200 600 1500 3.630 907 3.630 907 3 4.5 1.5 5 -- -- -- -- -- -- -- -- 19,438 77,758 ps ps ps ns ps ns ps ns ns ns ns ps ps ns ns ps ps ns ns clock cycles clock cycles tTCPL tTCPH tPDCC tPDFC1 tPDFC2 tPDFC3 tTFSSU tTFSH tTFSPW * TXFSYNC[P/N] must be synchronized to TXCLK[P/N]; it must be at least one TXCLK[P/N] clock-cycle wide, but less than one frame period minus two TXCLK[P/N] clock-cycles wide. TXCLKQ[P/N] is used in STS-48/STM-16 mode only. The PLL can be invoked in STS-48/STM-16 mode only. Agere Systems Inc. 183 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block Introduction This section describes the functions of the transport overhead processing block (TOHP-48) in the MARS2G5 PPro. This block supports regenerator section overhead (RSOH) or line section overhead and multiplex section overhead (MSOH) processing for quad STS-3/STM-1, quad STS-12/STM-4 signals, or a single STS-48/STM-16 signal. Control inputs and outputs for each functional block are specified, along with the appropriate control register bit definitions. TOHP-48 Functional Block Diagram Figure 25 shows a high-level view of the interconnect between the TOHP-48 processor block and other blocks (pointer interpreter, SPE mapper block, serial-to-parallel and parallel-to-serial conversion blocks, and the microprocessor interface). RECEIVE TOAC CHANNELS TOH PROCESSOR RX_DATAO[31:0] POINTER PROCESSOR RX_SYNCO RX_DATAI[31:0] SERIAL-TO-PARALLEL CONVERSION RECEIVE DIRECTION (FROM SONET/SDH LINE) TX_DATAO[31:0] PARALLEL-TO-SERIAL CONVERSION TRANSMIT DIRECTION (TO SONET/SDH LINE) TX_DATAI[31:0] PATH TERMINATOR TX_SYNCI CONTROL AND STATUS MICROPROCESSOR TRANSMIT TOAC CHANNELS 5-8127(F)r.1TDAT16 Figure 25. High-Level Block Interconnect 184 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Functional Block Diagram (continued) The TOHP-48 functional blocks are shown in Figure 26. FROM SONET/SDH LINE (RECEIVE DIRECTION) RDATAI [31:0] RDATAO [7:0] RSYNCO FRAME ALIGN DESCRAMBLER B1 J0 F1 F1 MONITOR B2 B2 BIP N CHECK K1 K2 K1/K2 APS MONITOR INSERT AIS-L K2 AIS-L RDI-L DETECT M1 M1 REI-L DETECT S1 SYNC STATUS MONITOR INPUT LOC MONITOR OOF LOF MONITOR LOS DETECTOR J0 MONITOR B1 BIP-8 CHECK TOAC DROP M1 REI COUNTER BER ALGORITHM TO SONET/SDH LINE (TRANSMIT DIRECTION) TSYNCO TDATAO[7:0] INSERT J0 Z0-X, A1/A2 SCRAMBLER INSERT SECTION/RSOH TRANSPOSE INSERT AIS MSOH B2 B2 GENERATE INSERT LINE/MSOH DIVIDER K1 K2 K1/K2 APS TSYNCI K2[2:0] RDI-L INSERT M1 M1 REI-L S1 SYNC STATUS TDATAI[31:0] B1 B1 GENERATE F1 F1 J0, E1, F1, D1--D3 INSERT TOAC INSERT D4--D12, S1, AND E2 (Z1 AND Z2 ONLY OC-12/OC-48) 5-8129(F)r.1 Figure 26. TOHP-48 Block Diagram (One Channel) Figure 26 describes a detailed view of one of four TOH channel processing blocks in both the receive and transmit direction. A detailed description of each block is provided in the following sections. Agere Systems Inc. 185 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) Enhancements This section includes the enhancements added to the TOHP block for the MARS2G5 P-Pro device. The enhancements are K1K2 validation and pass through mode for APSMON and K2MON processing, transposer (OC-48) and divider (OC-3), the TOAC must run at 20.736 MHz clock for all modes, and Rx output to the pointer processor block changes on the falling edge of the clock. APSMON and K2MON Processing (Including K1K2 Validation and Pass Through) Note: The three least significant bits of the K2 byte take on different meaning depending on the linear APS mode or ring status mode. Therefore, the integration is different. The K1 byte will be stored in TOHP_K1DMON[7:0] (Table 85), while the K2 byte will be stored in TOHP_K2DMON[7:0] (Table 85). The updating of these registers depends on mode bit TOHP_K1K2_2OR1 (Table 67), as follows: When TOHP_K1K2_2OR1 = 0, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0] (Table 66) consecutive frames of identical K1[7:0] and K2[7:3], i.e., the 13-bit pattern must be identical for TOHP_CNTDK1K2[3:0] frames prior to updating the K1 and K2 registers. In this mode, the TOHP_K2DMON[2:0] register will be updated after TOHP_CNTDK2[3:0] (Table 66) consecutive frames of identical K2[2:0]. When TOHP_K1K2_2OR1 = 1, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0] consecutive frames of identical K1[7:0] and K2[7:0], i.e., the 16-bit pattern must be identical for TOHP_CNTDK1K2[3:0] frames prior to updating the registers. Whenever the contents of the TOHP_K1DMON[7:0] and TOHP_K2DMON[7:3] (for TOHP_K1K2_2OR1 = 0) or TOHP_K2DMON[7:0] (for TOHP_K1K2_2OR1 = 1) register changes, a delta bit TOHP_K1K2DMOND (Table 62) will be set (TOHP_K1K2DMONM (Table 64)). This event bit is valid in both monitoring modes. The block will monitor the APS bytes (K1[7:0], K2[7:3]) or K2[7:0] (when TOHP_K1K2_2OR1 = 1) in the receive direction and report to the control interface (TOHP_RAPSBABLEE (Table 62), TOHP_RAPSBABLEM (Table 64)) when the K1 bytes are inconsistent. Inconsistent APS bytes are defined as TOHP_CNTDK1K2FRAME[3:0] (Table 66) (default = 0xC) successive frames, starting with the last frame containing previously consistent code, where no TOHP_CNTDK1K2[3:0] (default = 0x3) consecutive frames contain identical APS bytes. Whenever the contents of TOHP_K2DMON[2:0] changes, a delta bit TOHP_K2DMOND (Table 62) will be set (TOHP_K2DMONM (Table 64)). This event bit is only valid when TOHP_K1K2_2OR1 is a logic 0. Whenever the register bit TOHP_RVALIDK_CTL (Table 67) is a logic 1, the received K1K2 bytes will be compared with their reverse bytes for validation. Using the TOHP_CNTDK1K2[3:0] for the K1 byte and TOHP_CNTDK2[3:0] for the K2 byte, the received K1K2 will be written to the output TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0]. Otherwise, TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0] will be updated every frame with new received K1[7:0] and K2[7:0] bytes. (TOHP_K1K2_2OR1 has a higher priority.) All continuous N-times detection counters will be reset to 0, if there are any received B1 errors and the register bit TOHP_CNTDB1SEL (Table 67) is set to 1. 186 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction All monitoring functions supported by TOHP-48 in the receive direction are summarized here: Input clock and loss-of-signal monitoring Frame alignment and short frame B1 BIP-8 check J0/Z0 monitor Descrambler F1 monitor B2 BIP-8xN check APSMON and K2MON processing (including K1K2 validation and pass through) AIS-L and RDI-L detect MS-REI detect Sync status monitor Signal degrade BER algorithm Signal fail BER algorithm Transport overhead access channel (TOAC) drop Insertion of AIS-L (MS-AIS) Whenever the continuous N times detect (CNTD) signals are defined, they require not only that the monitored signal be consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status can be updated. If there are any errors in the framing pattern, then the consecutive N times detection counters will reset to 0. N can range from 1 to 15. Programming a CNTD block with any value less than 1 will set the CNTD to 1 time detect. The receive direction can be programmed into bypass mode bit TOHP_ROH_BYPASS (Table 67), in which all 32-bit input data will be retimed and passed through without any processing. The four output sync signals are forced low in this mode. Loss of Input Clock (LOC) and Loss of Signal (LOS) Monitoring The TOHP-48 block detects and reports loss of input clock (LOC), as determined by stuck high or stuck low for time T. The detection time T is greater than 6.58 s. The state of monitoring is controlled by bits (TOHP_LOC[A-- D] (Table 63), TOHP_LOCD[A--D] (Table 62), and TOHP_LOCM[A--D] (Table 64)). The TOHP-48 block detects and reports loss of signal (LOS) on the input data signal before descrambling, as determined by stuck high or stuck low for time T. The detection time T is user programmable through TOHP_LOSDETCNT[A--D][12:0] (Table 67), in steps of 8 (OC-3, OC-12) or 32 bits (OC-48) at a time with a range of (51.44 ns to 421.4 s) for OC-3 or (12.86 ns to 105.35 s) for OC-12/OC-48, respectively. A value of zero disables the stuck high/low monitoring feature of LOS detection. An LOS is not reported unless a clock is present. To recover from the LOS state, two consecutive frames must be received with the correct framing pattern spaced 125 s apart and, during the intervening time (one frame), no all-zeros/ones pattern indicates an LOS defect. Agere Systems Inc. 187 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) Frame Alignment Specification The framer goes in frame if it finds two consecutive frames with the desired framing bytes and goes out of frame if it finds five consecutive frames with at least one framing bit error in each frame. The following framing bytes indicate frame integrity and are observed every 125 s. Table 49. Framing Bytes Observed for Framing Integrity Interface OC-3 OC-12 OC-48 (32-bit) Sequence F6, 28 F6, F6, 28, 28 F6, F6, 28, 28 OOF is declared after the fifth errored A1A1A2A2 pattern, and reported to the control system (TOHP_OOF (Table 63), TOHP_OOFD (Table 62), and TOHP_OOFM (Table 64)). After 24 continuous frames (3 ms) of OOF, the block will declare a loss of frame defect and report this state (TOHP_LOF (Table 63), TOHP_LOFD (Table 62), and TOHP_LOFM (Table 64)). Once set, the block will clear the LOF state after 24 consecutive frames (3 ms) of no OOF events with correct framing patterns spaced 125 s apart. B1 BIP-8 Check A BIP-8 even parity is computed over the incoming scrambled data, and compared to the B1 byte received in the next frame. The total number of B1 BIP-8 bit errors (raw count), or block errors (as determined by bit TOHP_B1BITBLKCNT (Table 67), is counted. Upon the performance-monitor latch control signal, the value of the counter is presented to the control interface in a 16-bit counter, TOHP_B1ECNT[15:0] (Table 81). In case of overflow, the counter remains at its maximum value until it is cleared. Host microprocessor is expected to clear the counter at least once a second. 188 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) J0/Z0 Monitor J0 (section trace) monitoring has four different monitoring modes controlled by TOHP_J0MONMODE[1:0] (Table 67): J0MONMODE[1:0] = 00: The J0 byte of every frame is captured for 64 consecutive frames for a total of 64 bytes (RJ0DMON[1--64][7:0] (Table 86)). The incoming J0 byte is compared with the next expected-value (the expected value is obtained by cycling through the previous stored 64 received bytes in round-robin fashion) and sets an event bit (J0MISE, J0MISM), if different. J0MONMODE[1:0] = 01: This is the SONET framing mode. A J0 byte pattern of 0x0D followed by 0x0A character indicates that the next byte is the first byte of the path trace message. The J0 byte message is continuously written into RJ0DMON[1--64][7:0] with the first byte residing at the first address. If any received byte does not match the previously received byte for its location, then an event bit (J0MISE, J0MISM) is set. J0MONMODE[1:0] = 10: This is the SDH framing mode. The first J0 byte with the MSB set to one indicates that the next byte is the second byte of the message. The rest of operation is the same as in SONET framing mode. J0MONMODE[1:0] = 11: A new J0 byte (RJ0DMON[1][7:0]) will be detected after CNTDJ0Z0[3:0] consecutive consistent occurrences of a new pattern in the J0 overhead byte. Any changes to this byte is reported by (J0MISE, J0MISM). This event bit acts as a delta bit in this mode indicating a change in state for the RJ0DMON[1][7:0] byte. Note: In OC-48 mode, the device will monitor the first three (2, 3, and 4) Z0 bytes using the CNTD mode of the J0 monitors. Descrambler A frame synchronous descrambler of length 127 and generating polynomial x7 + x6 +1 will descramble the entire STS/STM signals except for the first row of overhead. The framing bytes (A1, A2), the section trace bytes (J0), and the growth bytes (Z0) are not descrambled. The scrambler will be set to 1111111 on the first byte following the last section OH byte in the first row (i.e., after byte J0 for STS-1, after the second Z0 for STS-3, etc.). The descrambler operates in a byte wide mode for OC-3/OC-12 and a 32-bit-word wide mode for OC-48. The frame descrambler can be disabled through TOHP_DSCRINH (Table 67). F1 Monitor The fault location byte TOHP_F1DMON0[7:0] (Table 85) is monitored by the F1 monitor. A new fault location state is detected after TOHP_CNTDF1[3:0] (Table 66) consecutive consistent occurrences of a new pattern in the F1 overhead byte. A history of the previous valid F1 byte, TOHP_F1DMON1[7:0], is also maintained. Any changes to this byte will be reported by bits TOHP_F1DMOND (Table 62) and TOHP_F1DMONM (Table 64). B2 BIP-8xN Check A BIP-8N even parity is computed over the incoming frame (except for rows 1, 2, and 3 of the section OH), and compared to the N B2 bytes received in the next frame, (N = 3, 12, or 48). The total number of B2 BIP-8N bit errors (raw count), or block errors as determined by TOHP_B2BITBLKCNT (Table 67) is counted. Upon a PM latch control signal PM_LATCH, the internal running counter is placed into a holding register TOHP_B2ECNTR (Table 82) and then cleared. In case of overflow, the internal counter will stay at its maximum value until cleared. The checker must output a per-frame error count (B2ECntPerF[7:0]), which is needed in the transmit direction to form M1 byte. The count is truncated at 255 for OC-48. Agere Systems Inc. 189 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) APSMON and K2MON Processing (Including K1K2 Validation and Pass Through) Note: The three least significant bits of the K2 byte take on different meaning depending on the linear APS mode or ring status mode. Therefore, the integration is different. The K1 byte will be stored in TOHP_K1DMON[7:0] (Table 85), while the K2 byte will be stored in TOHP_K2DMON[7:0] (Table 85). The updating of these registers depends on mode bit TOHP_K1K2_2OR1 (Table 67), as follows: When TOHP_K1K2_2OR1 = 0, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0] (Table 66) consecutive frames of identical K1[7:0] and K2[7:3], i.e., the 13-bit pattern must be identical for TOHP_CNTDK1K2[3:0] frames prior to updating the K1 and K2 registers. In this mode, the TOHP_K2DMON[2:0] register will be updated after TOHP_CNTDK2[3:0] (Table 66) consecutive frames of identical K2[2:0]. When TOHP_K1K2_2OR1 = 1, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0] consecutive frames of identical K1[7:0] and K2[7:0], i.e., the 16-bit pattern must be identical for TOHP_CNTDK1K2[3:0] frames prior to updating the registers. Whenever the contents of the TOHP_K1DMON[7:0] and TOHP_K2DMON[7:3] (for TOHP_K1K2_2OR1 = 0) or TOHP_K2DMON[7:0] (for TOHP_K1K2_2OR1 = 1) register changes, a delta bit TOHP_K1K2DMOND (Table 62) will be set (TOHP_K1K2DMONM (Table 64)). This event bit is valid in both monitoring modes. The block will monitor the APS bytes (K1[7:0], K2[7:3]) or K2[7:0] (when TOHP_K1K2_2OR1 = 1) in the receive direction and report to the control interface (TOHP_RAPSBABLEE (Table 62), TOHP_RAPSBABLEM (Table 64)) when the K1 bytes are inconsistent. Inconsistent APS bytes are defined as TOHP_CNTDK1K2FRAME[3:0] (Table 66) (default = 0xC) successive frames, starting with the last frame containing previously consistent code, where no TOHP_CNTDK1K2[3:0] (default = 0x3) consecutive frames contain identical APS bytes. Whenever the contents of TOHP_K2DMON[2:0] changes, a delta bit TOHP_K2DMOND (Table 62) will be set (TOHP_K2DMONM (Table 64)). This event bit is only valid when TOHP_K1K2_2OR1 is a logic 0. Whenever the register bit TOHP_RVALIDK_CTL (Table 67) is a logic 1, the received K1K2 bytes will be compared with their reverse bytes for validation. Using the TOHP_CNTDK1K2[3:0] for the K1 byte and TOHP_CNTDK2[3:0] for the K2 byte, the received K1K2 will be written to the output TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0]. Otherwise, TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0] will be updated every frame with new received K1[7:0] and K2[7:0] bytes. (TOHP_K1K2_2OR1 has a higher priority.) All continuous N-times detection counters will be reset to 0, if there are any received B1 errors and the register bit TOHP_CNTDB1SEL (Table 67) is set to 1. AIS-L and RDI-L Detect The block will monitor for line AIS (AIS-L/MS-AIS) in the K2[2:0] bits. Line AIS will be detected and LAISMON will be set to 1 after TOHP_CNTDK2[3:0] consecutive occurrences of K2[2:0] = 111. Once set, AIS-L will be cleared after TOHP_CNTDK2[3:0] consecutive frames of K2[2:0] = 111. Any change to TOHP_LAISMON (Table 63) will be reported (TOHP_LAISMOND (Table 62), TOHP_LAISMONM (Table 64)). This function is only valid when TOHP_K1K2_2OR1 is a logic 0. The block will also monitor for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits. A line RDI condition will be detected, and TOHP_LRDIMON (Table 63) will be set to 1 after TOHP_CNTDK2[3:0] consecutive occurrences of K2[2:0] = 110. Once set, RDI-L will be cleared after TOHP_CNTDK2[3:0] consecutive frames of K2[2:0] = 110. Any change to TOHP_LRDIMON will be reported (TOHP_LRDIMOND (Table 62), TOHP_LRDIMONM (Table 64)). This function is only valid when TOHP_K1K2_2OR1 is a logic 0. All continuous N times detection counters will be reset to 0 if there are any received B1 errors and the register bit TOHP_CNTDB1SEL (Table 67) is set to 1. 190 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) Multiplex Section Remote Error Indication (MS-REI) Detect One byte (M1) is allocated for use as a MS-REI. For STS/STM signals, this byte conveys the count (in the range of [0, 255]) of interleaved bit blocks that have been detected by the BIP-8xN (B2). For rates of STS-48/STM-16, this value will be truncated to 255. The block will allow access to the MS-REI errored bit count TOHP_M1ECNT[20:0] (Table 83), which is the accumulated error count from the M1 byte. This counter will hold at its maximum value and update when PMRST (pin D7) transitions from a logic 0 to a logic 1. Agere Systems Inc. 191 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) Sync Status Monitor The S1 byte is allocated for synchronization status. S1 bits 3 to 0 are used to convey a 4-bit code of which only six patterns are defined with the remaining codes reserved for quality levels defined by individual administrations. The S1 byte can be monitored in two modes: (1) as an entire 8-bit word or (2) as two 4-bit nibbles as programmed by TOHP_S1MON8OR4CTL (Table 67) control bit. TOHP_S1DMON8OR4CTL = 0 the associated state, delta, and mask registers are TOHP_S1DMON[7:0] (Table 85), TOHP_S1DMON8D (Table 62), TOHP_S1DMON8M (Table 64), respectively. TOHP_S1DMON8OR4CTL = 1 the associated state, delta, and mask registers are TOHP_S1DMON[7:4], TOHP_S1DMON8D, TOHP_S1DMON8M (most significant nibble (MSN)), and TOHP_S1DMON[3:0], TOHP_S1DMON4D (Table 62), TOHP_S1DMON4M (Table 64) (least significant nibble (LSN)), respectively. A new value will be detected after TOHP_CNTDS1[3:0] (Table 66) consecutive occurrences of a consistent new value in the incoming S1 byte. This value is used in both monitoring modes. An event bit TOHP_S1BABLEE (Table 62) will be set (TOHP_S1BABLEM (Table 64)) if TOHP_CNTDS1BABLE[3:0] (Table 66) consecutive frames pass without a validated message occurring. In 8-bit mode, the entire value is monitored for an inconsistent value; while in 4-bit mode, only the LSN is monitored for an inconsistent value. Signal Degrade BER Algorithm A signal degrade state and change of state indication will be provided to the control interface (SD, SDD, and SDM). This bit error rate algorithm can operate on either B1 or B2 errors (TOHP_SDB1B2SEL (Table 67)). Signal degrade is declared when TOHP_SDLSET[6:0] (Table 71) or more bit errors in TOHP_SDNSSET[17:0] (Table 71) frames occur TOHP_SDMSET[7:0] (Table 71) times out of TOHP_SDBSET[15:0] (Table 72) blocks (one block is equal to one measurement period of TOHP_SDNSSET[17:0] frames), and it is removed when less than TOHP_SDLCLEAR[3:0] (Table 73) bit errors in TOHP_SDNSCLEAR[17:0] (Table 71) frames occur TOHP_SDMCLEAR[6:0] (Table 73) times out of TOHP_SDBCLEAR[15:0] (Table 74) blocks. A TOHP_SDSET (Table 65) and TOHP_SDCLEAR (Table 65) one shot signal must be provided to force the BER algorithm into the failed state or normal state, respectively. The set parameters are used when SD = 0, and the clear parameters are used when SD = 1. The above algorithm can detect bit error rates from 1 x 10-3 to 1 x 10-9. Signal Fail BER Algorithm A signal fail state and change of state indication will be provided to the control interface (SF, SFD, and SFM). This bit error rate algorithm can operate on either B1 or B2 errors (TOHP_SFB1B2SEL(Table 67)). Signal fail is declared when TOHP_SFLSET[7 (version 2.2 and version 2.3) 6 (version 2.0):0] (Table 75) or more bit errors in TOHP_SFNSSET[17:0] (Table 75) frames occur TOHP_SFMSET[5 (version 2.2 and version 2.3) 6 (version 2.0):0] (Table 75) times out of TOHP_SFBSET[15:0] (Table 76) blocks (one block is equal to one measurement period of TOHP_SFNSSET[17:0] frames), and it is removed when less than TOHP_SFLCLEAR[3:0] (Table 77) bit errors in TOHP_SFNSCLEAR[17:0] (Table 77) frames occur TOHP_SFMCLEAR[6:0] (Table 77) times out of TOHP_SFBCLEAR[15:0] (Table 78) blocks. A SFSET and SFCLEAR one shot signal must be provided to force the BER algorithm into the failed state or normal state, respectively. The set parameters are used when SF = 0, and the clear parameters are used when SF = 1. The above algorithm can detect bit error rates from 1 x 10-3 to 1 x 10-9. 192 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) TOAC Drop The receive TOAC interface provides four TOAC output signals. Depending on the operation mode, the data rate of TOAC channels is listed as follows: Quad STS-3/STM-1. Four (1) TOAC channels, each at 5.184 Mbits/s. Quad STS-12/STM-4. Four (1) TOAC channels, each at 20.736 Mbits/s. Single STS-48/STM-16. Four (4) TOAC channels, each at 20.736 Mbits/s. To form a higher-level signal STS-N (N = 3M; M = 1, 4, 16), M STS-3s are interleaved one byte at a time. The first byte of the STS-N is the first A1 framing byte from STS-3 number 1 followed sequentially by the first A1 byte from STS-3 number 2 through M. [The lowest bit rate signal for SDH is STM-1, which is equivalent to a SONET OC-3 signal. To form a higher-level STM-M (M = 1, 2, or 16), M administrative unit groups (AUG) are interleaved one byte at a time. An AUG consists of either 1 AU-4 (STS-3c) or 3 AU-3s (STS-1).] Agere Systems Inc. 193 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) The following figure shows the time-slot byte interleaving sequence per STS-1. STS-1 1 STS-1 2 STS-1 3 STS-1 4 STS-1 5 STS-1 6 STS-1 7 STS-1 8 STS-1 9 STS-1 10 STS-1 11 STS-1 12 3:1 STS-3/STM-1 12 11 10 INTERLEAVING ORDER 3:1 STS-3/STM-1 9 8 7 STS-12 12 9 6 3 11 8 5 2 10 7 4 1 4:1 STM-4 10 7 4 1 10 7 4 1 10 7 4 1 3:1 STS-3/STM-1 6 5 4 TIME 3:1 STS-3/STM-1 3 2 1 THE INTERLEAVING ORDER FOR A STS-48/STM-16 IS AS FOLLOWS: STS-48 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 47 44 41 38 35 32 29 26 23 20 17 14 11 8 5 2 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1 STM-16 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1 Figure 27. Time-Slot Assignments 194 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) The time-slot assignment for each TOAC channel is summarized in the following table. Table 50. TOAC Channel Output Versus Time-Slot Assignment Output Rate A STS-3/STM-1 STS-12/STM-4 STS-48/STM-16 321 321 TOAC Channel Outputs vs. Output Time Slot B 321 C 321 D 12 9 6 3 11 8 5 2 10 12 9 6 3 11 8 5 2 10 12 9 6 3 11 8 5 2 10 12 9 6 3 11 8 5 2 10 741 741 741 741 39 27 15 3 38 26 14 42 30 18 6 41 29 17 45 33 21 9 44 32 20 48 36 24 12 47 35 2 37 25 13 1 5 40 28 16 4 8 43 31 19 7 23 11 46 34 22 10 The transport overhead access channel consists of the following signals: Four 5.184/20.736 MHz clock signals, RXTOHCLK[A--D] pins AK5, AL4, AL6, and AL7, respectively. Four 5.184/20.736 Mbits/s data signals, RXTOHD[A--D] pins AL2, AM5, AM6, and AN7, respectively. Four 8 kHz synchronization signals, RXTOHF[A--D] pins AK4, AL3, AN5, and AP6, respectively. An inhibit signal is provided through the control interface to force the clock, sync, and selected data signal to zero (TOHP_RTOACCINH (Table 68), TOHP_RTOACSINH (Table 68), and TOHP_RTOACDINH (Table 68)). The data signal is partitioned into frames of 81 bytes for STS-3 mode and 324 bytes for STS-12 or STS-48 modes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. The remaining 7 bits of this byte are not specified. Bytes shown in Table 51 summarize the access capabilities of the receive TOAC. Bytes indicated in bold type are not specified in the standard, but are labeled here for clarity. Agere Systems Inc. 195 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Receive Direction (continued) Table 51. Transport Overhead Bytes Received Via RxTOAC Interface* Note: Numbers after - indicates byte number. OH Parity A1-[2--12] B1-1 D1-1 H1-1 B2-1 D4-1 D7-1 D10-1 S1 B1-[2--12] D1-[2--12] H1-[2--12] B2-[2--12] D4-[2--12] D7-[2--12] Z1-[2--12] A2-1 E1-1 D2-1 H2-1 K1-1 D5-1 D8-1 Z2-1 A2-[2--12] E1-[2--12] D2-[2--12] H2-[2--12] K1-[2--12] D5-[2--12] D8-[2--12] Z2-2 M1 (Z2-3) Z2-[4--12] J0 F1-1 D3-1 H3-1 K2-1 D6-1 D9-1 E2-1 Z0-[2--12] F1-[2--12] D3-[2--12] H3-[2--12] K2-[2--12] D6-[2--12] D9-[2--12] D12-[2--12] E2-[2--12] D10-[2--12] D11-1 D11-[2--12] D12-1 * Each TOAC output will have the corresponding byte value assigned to the time slot being accessed. This example is for an STS-12 signal for TOAC output. Even or odd parity can be inserted into the first bit of the MSB byte of the TOAC outgoing frame, using register bits (TOHP_RTOAC_OEPINS[A--D] (Table 68)). Insertion of AIS-L (MS-AIS) The TOH-48 block will automatically generate AIS-L (MS-AIS) when TOHP_LOS, TOHP_OOF, or TOHP_LOF state bits (Table 63) are active and the appropriate inhibit signals are inactive or software insert TOHP_LAISINS (Table 67) is active. Failure signal is comprised of LINE_AIS_GENERATE and FRM_ERR value for continuous N-times detect (CNTD) detectors, but only LINE_AIS_GENERATE for error counters. The TOHP-48 block will start/stop generating AIS-L within 125 s of the detection/absence of a failure condition. AIS-L (MS-AIS) is generated as a valid section overhead and an all 1s pattern in the remainder of the signal. 196 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) This block accepts a frame with payload data (SPE), path overhead (POH), and pointer information (H1--H3) bytes inserted. All other overhead bytes are inserted by this block; therefore, the incoming frame may put a fixed stuff value into these time slots. The only other control signal needed by the block along with the data is a frame sync signal active high one clock cycle aligned the A1-1 byte time. A bypass mode is also supported in the transmit direction. When TOHP_TOH_BYPASS (Table 69) is set high, all 32 bits input data will be passed through to output unprocessed and the output sync signal is invalid. This section is broken down into the following functional parts: Transpose (OC-48) and divider (OC-3) TOAC insert Sync status byte (S1) insert REI-L insert: M1 K1 and K2 insert (including validation and pass through) AIS-L insert B2 calculation and insert F1 byte insert B1 generate and error insert Scrambler J0/Z0 insert control A2 error insert All insert control functions that are inhibited will insert all 0s for SONET and all 1s for SDH into the outgoing byte. Agere Systems Inc. 197 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) TOAC Insert One transport overhead access channel (TOAC) is provided on-chip to provision the TOH portion of the outgoing frame. The TOAC consists of the following signals: A 5.184/20.736 MHz clock signal, sourced by the block (TTOACCLKO). One 20.736 Mbits/s data signal received by the block in the transmit direction (TTOACDATAI). An 8 kHz synchronization signal (TTOACSYNCO), sourced by this block. The sync signal is normally low; during the first clock period of each frame coincident with the most significant bit of the first byte, the sync signal will go high. An inhibit signal is provided to place the clock and sync signal in a logic 0 state (TOHP_TTOACINH (Table 69)). TOAC Channel Input Versus Time-Slot Assignments Table 52. TOAC Channel Input Versus Time-Slot Assignments Output Rate TOAC Channel Inputs vs. Input Time Slot 1 741 34 31 28 25 22 19 16 13 10 7 4 1 STS-3/STM-1 STS-12/STM-4 STS-48/STM-16 The data signal is partitioned into frames of 324 bytes (except for OC-3). The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are received most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648(OC-3)/2592(OC-12/OC-48) bits of the previous frame. The remaining 7 bits of this byte are not specified. In mixed/quad STS-3/STS-12 mode, the TOAC input has byte multiplexed data from each output signal (see Table 53, Table 54, and Table 55). Table 53. TTOAC OC-3 Signal Definition* OC-3 Mode Signal Format (Letters Indicate Port Designations) OH Pty E1-A D1-A D3-B D4-A/ K1-A D6-B D8-C D10-D S1-A X E1-B D1-B D3-C D4-B/ K2-A D6-C D8-D D11-A S1-B K1-A E1-C D1-C D3-D D4-C/ K1-B D6-D D9-A D11-B S1-C K2-A E1-D D1-D K1-B J0-A F1-A D2-A K2-B D5-A/ K1-C D7-B D9-C D11-D E2-A J0-B F1-B J0-C F1-C J0-D F1-D X X D3-A K2-D D6-A D8-B D10-C D12-D X D2-B K1-C D5-B/ K2-C D7-C D9-D D12-A E2-B D2-C K2-C D5-C/ K1-D D7-D D10-A D12-B E2-C D2-D K1-D D5-D/ K2-D D8-A D10-B D12-C E2-D D4-D/ K2-B D7-A D9-B D11-C S1-D * X = reserved bytes (4 bytes). Inserted via TOAC or TOHP registers. 198 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) Table 54. TTOAC OC-12 Signal Definition OC-12 Mode Signal Format (Letters Indicate Port Designations) ABCD OH Pty X D1 X X D4 D7 X X D1 X X D4 D7 X X D1 X X D4 D7 X X D1 X X D4 D7 A X X D1-2 X X D4-2 D7-2 B X X D1-2 X X D4-2 D7-2 C X X D1-2 X X D4-2 D7-2 D X X D1-2 X X D4-2 D7-2 A X X D1-3 X X D4-3 D7-3 B X X D1-3 X X D4-3 D7-3 C X X D1-3 X X D4-3 D7-3 D X X D1-3 X X D4-3 D7-3 ABCD A X E1 D2 X K1 D5 D8 X E1 D2 X K1 D5 D8 X E1 D2 X K1 D5 D8 X E1 D2 X K1 D5 D8 X E1-2 D2-2 X K2 D5-2 D6-2 B X E1-2 D2-2 X K2 D5-2 D6-2 C X E1-2 D2-2 X K2 D5-2 D6-2 D X E1-2 D2-2 X K2 D5-2 D6-2 A X E1-3 D2-3 X X D5-3 D6-3 B X E1-3 D2-3 X X D5-3 D6-3 C X E1-3 D2-3 X X D5-3 D6-3 D X E1-3 D2-3 X X D5-3 D6-3 ABCD J0 F1 D3 X K2 D6 D9 J0 F1 D3 X K2 D6 D9 J0 F1 D3 X K2 D6 D9 J0 F1 D3 X K2 D6 D9 A X F1-2 D3-2 X K1 D6-2 D9-3 B X F1-2 D3-2 X K1 D6-2 D9-3 C X F1-2 D3-2 X K1 D6-2 D9-3 D X F1-2 D3-2 X K1 D6-2 D9-3 A X F1-3 D3-3 X X D6-3 D9-3 B X F1-3 D3-3 X X D6-3 D9-3 C X F1-3 D3-3 X X D6-3 D9-3 D X F1-3 D3-3 X X D6-3 D9-3 D10 D10 D10 D10 D10-2 D10-2 D10-2 D10-2 D10-3 D10-3 D10-3 D10-3 D11 D11 D11 D11 D11-2 D11-2 D11-2 D11-2 D11-3 D11-3 D11-3 D11-3 D12 D12 D12 D12 D12-2 D12-2 D12-2 D12-2 D12-3 D12-3 D12-3 D12-3 S1 S1 S1 S1 Z1 -2 Z1 -2 Z1 -2 Z1 -2 Z1-3 Z1-3 Z1-3 Z1-3 Z2 Z2 Z2 Z2 Z2-2 Z2-2 Z2-2 Z2-2 Z2-4 Z2-4 Z2-4 Z2-4 E2 E2 E2 E2 E2-2 E2-2 E2-2 E2-2 E2-3 E2-3 E2-3 E2-3 Note: X = reserved bytes (99 bytes). Agere Systems Inc. 199 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) Table 55. TTOAC OC-48 Signal Definition OC-48 Mode Signal Format (Letters Indicate Port Designations) OH Pty X D1 X X D4 D7 D10 S1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X E1 D2 X K1 D5 D8 D11 Z2 Z2-2 X X K2 X X X X X X X X X X X X X X X X X J0 F1 D3 X X X X X X X X X K2 D6 D9 D12 E2 X X X X X X K1 X X X X X X X X X X X X E1-2 to 12 D2-2 to 12 X X X X X X F1-2 to 12 D3-2 to 12 X X XX XX X X X X X X X X D1-2 to 12 D4-2 to 12 D7-2 to 12 D10-2 to 12 Z1-2 to 12 D5-2 to 12 D8 -2 to 12 D11-2 to 12 Z2-4 to 12 D6-2 to 12 D9-2 to 12 D12-2 to 12 E2-2 to 12 Note: X = reserved bytes (115 bytes). 200 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) In STS-48 mode, each TOAC input has access to those columns of overhead bytes as defined in Table 52. An event indication is provided to indicate parity errors on the TOAC input channel. Odd (logic 0)/even (logic 1) parity is checked (TOHP_TTOAC_OEPMON (Table 69), TOHP_TTOAC_PERRM (Table 64), TOHP_TTOAC_PERRE (Table 62)). Table 56 summarizes the insertion options for the specified overhead bytes for the transmit TOAC. A predefined stuff value (all 0s for SONET and all 1s for SDH) or the corresponding TOAC value is inserted as shown in Table 56. Table 56. TTOAC Control Bits Overhead Bytes OC-3 OC-12 J0 E1 F1 D1--D3 K1, K2[7:3] K2[2:0]* D4--D12 S1 E2 D1-[2-3] to D3, D3-[2-3] D1-2, . . ., N to D3-2, . . ., N OC-48 Control Bits (Table 69) TOHP_TTOAC_J0[A--D] TOHP_TTOAC_E1[A--D] TOHP_TTOAC_F1[A--D] TOHP_TTOAC_D1TO3[A--D] TOHP_TTOAC_K1K2[A--D] TOHP_TK2SINS[A--D][1:0] TOHP_TTOAC_D4TO12[A--D] TOHP_TTOAC_S1[A--D] TOHP_TTOAC_E2[A--D] TOHP_TTOAC_INS SONET/SDH (00000000/ 11111111) TTOAC Data Values 0 (Default Value) SONET/SDH (00000000/ 11111111) 1 TTOAC Data D4-[2-3] D4-2, . . ., N to D12-2, . . ., N to D12, D12-[2-3] E1-[2-3] F1-[2-3] E2-[2-3] Z1-2, Z1-3 Z2-[2-3] E1-2, . . ., E1-N F1-2, . . ., F1-N E2-2, . . ., E2-N Z1-2, . . ., Z1-N Z2-1, Z2-2 Z2-4, . . ., Z2-N * When TOHP_TK2SINS[A--D][1:0] = 11 TOAC data is inserted into the outgoing k2[2:0] value; otherwise, the source of this value can come from hardware, software, or raw K value. Agere Systems Inc. 201 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) Sync Status Byte Insert Via microprocessor control of TOHP_TS1INS (active-high) (Table 69) and TOHP_TS1DINS[7:0] (Table 84), data information may be inserted into the outgoing S1 byte [9, 1, 1]. Direct microprocessor insert has higher priority than the TOAC insert control bit (TOHP_TTOAC_S1(Table 69)). REI-L (MS-REI): M1 One byte is allocated for use as an MS-REI. For STS-N/STM-M levels, this byte conveys the count (in the range of [0, 255]) of interleaved bit blocks that have been detected in error by the BIP-24xM (B2) detector on the received signal (B2ECntPerF[7:0]). For STS-48/STM-16 signals, this value is held at 255 if the received signal has more than 255 BIP errors. This function can be inhibited (TOHP_TM1_REIL_INH (Table 69)) and the default value inserted (STUFFBYTE[7:0]) via microprocessor control. A continuous error in the M1 byte can be inserted under user control (TOHP_TM1_ERR_INS (Table 69)). A value of 0x03 is inserted when the TOHP_TM1_ERR_INS signal is active. REI-L (MS-REI) is inserted into M1 byte as defined in the following figure. 23 (MSB) Z2-1 Z2-2 M1 0 (LSB) 7 (MSB) REI-L (MS-REI) [9, 2, 3] 0 (LSB) 5-8497(F)r.1 Figure 28. REI-L (MS-REI) Location For STS-3/STM-1 signals, the M1 value is in the range of 0 to 24. For STS-12/STM-4 signals, the M1 value is in the range of 0 to 96. For STS-48/STM-16 signals, the M1 value is in the range of 0 to 255 (truncated). K1 and K2 Insert Control Parameters Via microprocessor control (TOHP_TAPSINS = 1 (Table 70)) the K1 [5, 2, 1] and K2 [5, 3, 1] outgoing bytes are written from TK1DINS[7:0] (Table 84) and TK2DINS[7:3] (Table 84), respectively. When TOHP_TAPSINS is logic 0, K1[7:0] and K2[7:3] outgoing bytes are written from TX_RAWK[15:3]. Since TX_RAWK[15:0] is a multibyte register, both values must be valid at the same time. When TOHP_TK2SINS[1] = 1 (Table 70), data from the TOHP_TK2DINS[2:0] register is written into K2[2:0] (transmit K2 software insertion). For hardware insertion of RDIL (110) to be written to K2[2:0], set TOHP_TK2SINS[1:0] = 01. Otherwise, when TOHP_TK2SINS[1:0] = 00, TX_RAWK[2:0] is written to K2[2:0]. When TOHP_TVALIDK_CTL (Table 70) is a logic 1, reversed K1 byte is written to K1 ([5, 2, 2] for OC-3/OC-12, [5, 2, 5] for OC-48) and reversed K2 byte is written to K2 ([5, 3, 2] for OC-3/OC-12, [5, 3, 5] for OC-48). Otherwise, K1 and K2 reverse bytes are written with default values (all 0s for SONET and all 1s for SDH). APS babbling test control: Setting the TOHP_TAPSBABLEINS bit (Table 69), via microprocessor control, forces the K1[7:0], K2[7:3) to an inconsistent state; no three consecutive values are the same continuously. 202 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) Line RDI is inserted into the data signal when one or more of the following occurs and the corresponding inhibit bit is not set: Input loss of clock (LOC) Loss-of-signal (LOS) Out-of-frame (OOF) Loss-of-frame (LOF) Line AIS (LAISMON) Signal fail (BER algorithm) (SF) When a failure condition exists that will cause RDI-L to be generated, the generation of RDI-L will last for at least 20 frames before clearing; even if the original failure cause has cleared in less than 20 frames. This function can be inhibited by setting TOHP_TIMER_LRDIINH (Table 69) to a logic 1. AIS Line/MS-AIS Generation Line AIS/MS-AIS is specified as all 1s in the entire STS/STM signal before scrambling, excluding the section overhead (RSOH). Line AIS can be generated via microprocessor control on a per STS-1 basis (TOHP_TAISLINS[48:1] (Table 70)). For a concatenated or STM type signal, the user must determine which time slots should be provisioned to generate a valid AIS signal. B2 BIP 8XN Calculation and Insert The B2 bytes are allocated for a line overhead (multiplex section) error monitoring function. This function will be a bit interleaved parity N X 8 code (BIP-N X 8) using even parity. The BIP-N X 8 is computed over all bits of the previous STS-N/STM-M frame except the first three rows of SOH (RSOH) and is placed in bytes B2 of the current frame before scrambling. N = 3M and M = 1, 4, and 16. Via microprocessor control all B2 bytes can be inverted (TOHP_TB2ERRINS (Table 69)). F1 Byte Insert Via microprocessor control of TOHP_TF1INS (Table 69) and TOHP_TF1DINS[7:0] (Table 84), data information may be inserted into the outgoing F1 byte[2, 3, 1]. Direct microprocessor insert has higher priority than the TOAC insert control bit (TOHP_TTOAC_F1 (Table 69)). When TOHP_TF1INS is a logic 1, insert the value in register TOHP_TF1DINS[7:0]; otherwise, insert the associated TOAC value when TOHP_TTOAC_F1 is a logic 1 or insert the default value of all zeros for SONET and all ones for SDH when TOHP_TTOAC_F1 is logic 0. B1 Generate and Error Insert The section bit interleaved parity code (BIP-8) byte--this is a parity code (even parity), used to check for transmission errors over a section. Its value is calculated over all bits in the previous frame after scrambling, and then placed in the B1 byte of time slot 1 before scrambling. Via microprocessor control the B1 byte can be inverted (TOHP_TB1ERRINS (Table 69)). Agere Systems Inc. 203 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) Transmit Direction (to SONET/SDH line) (continued) Scrambler The outgoing frame will be scrambled with the frame synchronous scrambler of length 127 and generating polynomial x7 + x6 + 1. The entire STS/STM signal will be scrambled except for the first row of overhead. The scrambler will be set to 1111111 on the first byte following the last overhead byte in the first row. For test purposes, the scrambler will be disabled when TOHP_SCRINH (Table 69) is a logic 1. J0/Z0 Insert Control A 16-byte sequence stored in registers TOHP_TJ0DINS[1--16][7:0] (Table 87) will be inserted into the outgoing J0 byte if TOHP_TJ0INS (Table 69) is set to logic 1; otherwise, the associated TOAC value is inserted when TOHP_TTOAC_J0 (Table 69) is a logic 1 or the default value is inserted when TOHP_TTOAC_J0 is logic 0. A programmable value is inserted into each Z0 byte. The values are stored in registers TOHP_TZ0DINS[A--D][3-- 2][7:0] (Table 88) for OC-3 mode and TOHP_TZ0DINS[A--D][12--2][7:0] for OC-12 mode. In OC-48 mode, there are 47 Z0 bytes that are stored in {TOHP_TZ0DINS[D][12--2], TOHP_TJ0INS[D][1], TOHP_TZ0DINS[C][12--2], TOHP_TJ0INS[C][1], TOHP_TZ0DINS[B][12--2], TOHP_TJ0INS[B][1], and TOHP_TZ0DINS[A][12--2]}. A2 Error Insert From 1 to 32 continuous outgoing (TOHP_TA1A2ERRINS[4:0] (Table 69), TOHP_TA1A2ERREN (Table 65)) frames can have inverted A2-1 (0x28 to 0xD7) pattern. The value in the TOHP_TA1A2ERRINS[4:0] register specifies the number of frames to insert errors into, while the TOHP_TA1A2ERREN one-shot register starts the error insertion process. Receive/Transmit TOHP-48 Interface All receive transport overhead bytes are output on the RTOH interface for external processing needs. All transmit transport overhead bytes can optionally be inserted from the TTOH interface for external needs. Table 57. Rx/Tx TOHP-48 Interface Rates Rate Selection R/T (TOHP_RX_MODE[1:0]/ TOHP_TX_MODE[1:0] 0x0800 (Table 60)) 1X 01 00 Mode Rx/Tx TOHP-48 Interface Rate OC-48 OC-12 OC-3 20,736,000* baud 20,736,000 bits/s 5,184,000 bits/s * This OC-48 interface is a four-line interface resulting in an effective interface rate of 82,944,000 bits/s. 204 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) Receive/Transmit TOHP-48 Interface (continued) RXTOHCLK[A--D] RXTOHF[A--D] E2#34[0] OH PARITY[7] X[6] OC-48 MODE RXTOHD[A--D] E2--3D[0] OH PARITY[7] X[6] OC-12 MODE E2--3[0] OH PARITY[7] X[6] OC-3 MODE 5-7419(F)r.5U Note: Numbers in brackets denote bits. X[number] indicates a reserved bit. Figure 29. RTOH Interface TXTOHCLK TXTOHF E2#34[0] OH PARITY[7] X[6] OC-48 MODE TXTOHD E2--3D[0] OH PARITY[7] X[6] OC-12 MODE X[0] OH PARITY[7] X[6] OC-3 MODE 5-7420(F)r.4U Note: Numbers in brackets denote bits. X[number] indicates a reserved bit. Figure 30. TTOH Interface Agere Systems Inc. 205 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) Transport Overhead Access Channel (TOAC) Interface Timing Transport overhead access channel (TOAC) interface timing specifications are given for the transmit direction in Figure 31 and in Table 58, and for the receive direction in Figure 32 and in Table 59. 33% OUTPUT--TXTOHCLK DUTY CYCLE CLOCK 5.184 MHz (STS-3/STM-1) 20.736 MHz (STS-12/STM-4) (STS-48/STM-16) 67% 50% 50% 50% 50% 50% 50% 33% 67% 0.75tCP* tCP tTTSDU tTTDH INPUT--TXTOHD tTTFSPD OUTPUT--TXTOHF 8 kHz 0151(F)r.4 Note: Duty cycles shown are nominal. * tCP = x/y where y is the clock frequency in MHz on the TXCLKP/N pins and x = 32 for OC-3 and OC-12. For OC-48, x = 8. Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing Table 58. Transmit TOAC Interface Timing Specifications Symbol tTTDSU tTTDH tTTFSPD Test Conditions -- -- CL = 50 pF Setup (Min) 10 -- -- Hold (Min) -- 10 -- Propagation Delay (Min) -- -- 0 (Max) -- -- 10 ns ns ns Unit 33% OUTPUT--RXTOHCLK[D--A] DUTY CYCLE CLOCK 20.736 MHz (STS-12/STM-4) (STS-48/STM-16) 67% 50% 50% 50% 50% 50% 50% 33% 67% 0.75tCP* tCP tRTDPD RXTOHD[D--A] OUTPUTS tRTFSPD RXTOHF[D--A] 8 kHz 0152(F)r.2 Note: Duty cycles shown are nominal. * tCP = x/y where y is the clock frequency in MHz on the TXCLKP/N pins and x = 32 for OC-3 and OC-12. For OC-48, x = 8. Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing 206 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) Transport Overhead Access Channel (TOAC) Interface Timing (continued) 33% OUTPUT--RXTOCLK[D--A] DUTY CYCLE CLOCK 5.184 MHz (STS-3/STM-1) tCP tRTDPD RXTOHD[D--A] OUTPUTS 67% 50% 50% 50% 50% 50% 50% 33% 67% 0.75tCP* tRTFSPD RXTOHF[D--A] 8 kHz 0153(F)r.4 Note: Duty cycles shown are nominal. * tCP = x/y where y is the clock frequency in MHz on the TXCLKP/N pins and x = 32 for OC-3 and OC-12. For OC-48, x = 8. Figure 33. STS-3/STM-1 Receive TOAC Interface Timing Table 59. Receive TOAC Interface Timing Specifications Symbol tRTDPD tRTFSPD Test Conditions CL = 50 pF CL = 50 pF Propagation Delay (Min) 0 0 (Max) 10 10 ns ns Unit Agere Systems Inc. 207 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions To access (read and write) registers RXCLK[A--D][P/N] (see Pin Descriptions--Line Interface Signals, Table 7 on page 97) must always be present for a given application. Note:Parameters of more than 16 bits are made up of 32-bit register pairs (Table 75, Table 77). Each pair gets written at the same time. Two consecutive writes are needed to complete a write to these registers. For example, when writing address 0x0852, the data is held in a shadow register; when writing address 0x0853, the data gets written in 0x0853 and at the same time, the data in the shadow register is transferred to address 0x0852. When reading, the registers are accessed without using the shadow register and are read one at a time. Table 60. TOHP_MODE_VERR, Mode (R/W) and Block Version (RO) Address 0x0800 Bit 15:13 Name Function Reset Default 011 TOHP_RX_MODE[2:0] Receive Direction Mode. TOHP_RX_MODE[2], bit 15, has two functions: default value for the registers and the number of errored frames required before declaring and OOF condition in the framer. [2] 1 = SDH, 0 = SONET [1] 1= OC-48, 0 = OC-3/12 [0] 1 = OC-12, 0 = OC-3 12:10 TOHP_TX_MODE[2:0] Transmit Direction Mode. TOHP_TX_MODE[2], bit 12, has two functions: default value for the registers and the number of errored frames required before declaring and OOF condition in the framer. [2] 1 = SDH, 0 = SONET [1] 1 = OC-48, 0 = OC-3/12 [0] 1 = OC-12, 0 = OC-3 011 9:0 TOHP_VER[9:0] Block Version Number. Block version register will change each time the device is changed. 0000000 001 Table 61. TOHP_CH_INT, Channel Interrupt (R/W, RO) Address 0x0801 Bit 15 14:12 11:8 Name TOHP_CORWN -- Function Clear on Read/(Not) Write. 1 = COR, 0 = COW. Reserved. Reset Default 0 0x0 0x0 TOHP_INTH[D--A] High Interrupt (RO). Active-high interrupt bits for channel D to A. Each bit is the ORing of all event and delta signals of OOF, LOF, LOS, and LOC of that channel (Table 62). -- TOHP_INTL[D--A] Reserved. Low Interrupt (RO). Active-high interrupt bits for channel D to A. Each bit is the ORing of all event and delta of all monitoring features, i.e., TOHP_K2DMON (Table 85), of that channel. 7:4 3:0 0x0 0x0 208 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 62. TOHP_DLT_EVT[A--D][1--2], 0x0802--0x0809, Delta/Event Registers (COR/COW-RO) Address 0x0802, 0x0804, 0x0806, 0x0808 Bit 15 Name Function Reset Default TOHP_LRDIMOND Line/Multiplex RDI Delta. Delta bit indicates a change of state 1, 1, 1, 1 [A--D] for the line/multiplex RDI state bits, TOHP_LRDIMON[A--D]. The delta bits clear when read. Their mask bits are TOHP_LRDIMONM[A--D]. In STS-48 mode, only TOHP_LRDIMOND[A] is valid. TOHP_LAISMOND [A--D] 1, 1, 1, Line/Multiplex AIS Delta. Delta bit indicates a change of 1 states for the line/multiplex AIS state bits TOHP_LAISMON[A--D]. The delta bits clear when read. Their mask bits are TOHP_LAISMONM[A--D]. In STS-48 mode, only TOHP_LAISMOND[A] is valid. APS Babble Event Bit. Each bit is active-high to indicate the inconsistence in K1 byte of that channel. Their mask bits are TOHP_RAPSBABLEM[A--D]. In STS-48 mode, only TOHP_RAPSBABLEE[A] is valid. 0, 0, 0, 0 14 13 TOHP_ RAPSBABLEE [A--D] 12 TOHP_S1DMON4D Delta Register for S1DMON[3:0] When S1MON8or4CTL = 1. 0, 0, 0, [A--D] Each delta bit indicates a change of state for 0 TOHP_S1DMON[3:0] in its channel. The delta bit clears when read. Their mask bits are TOHP_S1DMON4M[A--D]. In STS-48 mode, only TOHP_S1DMON4D[A] is valid. TOHP_S1DMON8D Delta Register for S1DMON[7:4] When S1MON8or4CTL = 1 0, 0, 0, 0 [A--D] or S1DMON[7:0] When S1MON8or4CTL = 0. Each delta bit indicates a change of state for TOHP_S1DMON[7:4]/ TOHP_S1DMON[7:0] in its channel. The delta bit clears when read. Their mask bits are TOHP_S1DMON8M[A--D]. In STS-48 mode, only S1DMON8D[A] is valid. TOHP_K2DMOND [A--D] K2[2:0] Data Monitor Delta Bit. Each bit is active-high to indi- 0, 0, 0, 0 cate a change in TOHP_K2DMON[A--D] for that channel. These bits will clear when read or write. Their mask bits are TOHP_K2DMONM[A--D]. In STS-48 mode, only TOHP_K2DMONE[A] is valid. 11 10 9 0, 0, 0, TOHP_K1K2DMOND K1K2 Data Monitor Delta Bit. Each bit is active-high to indi0 [A--D] cate a change in (K1[7:0] and K2[7:3]) or (K1[7:0] and K2[7:0]) for that channel depending on K1K2_2OR1. Their mask bits are TOHP_K1K2DMONM[A--D]. In STS-48 mode, only TOHP_K1K2DMONE[A] is valid. TOHP_F1DMOND [A--D] TOHP_ TTOAC_PERRE F1 Data Monitor Delta Bit. Their mask bits are TOHP_F1DMONM[A--D]. In STS-48 mode, only TOHP_F1DMOND[A] is valid. 0, 0, 0, 0 8 0x0802 7 Transmit TOAC Parity Error Event. Event register indicates a 1, 0, 0, parity error was detected on the incoming TOAC. 0 Agere Systems Inc. 209 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 62. TOHP_DLT_EVT[A--D][1--2], 0x0802--0x0809, Delta/Event Registers (COR/COW-RO) (continued) Address 0x0802, 0x0804, 0x0806, 0x0808 Bit 6 Name TOHP_ S1BABLEE[A--D] TOHP_SFD[A--D] Function Receive S1 Byte Babbling Event. This event register will be set if TOHP_CNTDS1BABLE[A--D][3:0] consecutive frames pass without a validated S1 byte. Signal Fail BER Algorithm Delta. Delta bit indicates a change of state for the signal fail BER algorithm state bits TOHP_SF[A--D]. The delta bits clear when read. Their mask bits are TOHP_SFM[A--D]. In STS-48 mode, only TOHP_SFD[A] is valid. Reset Default 0, 0, 0, 0 1, 1, 1, 1 5 0x0802, 0x0804, 0x0806, 0x0808 4 TOHP_SDD[A--D] Signal Degrade BER Algorithm Delta. Delta bit indicates a change of states for the signal degrade BER algorithm state bits TOHP_SD[A--D]. The delta bits clear when read. Their mask bits are TOHP_SDM[A--D]. In STS-48 mode, only TOHP_SDD[A] is valid. TOHP_OOFD [A--D] Receive Out of Frame Delta. Delta bit indicates change of state for the out-of-frame TOHP_OOF[A--D]. The delta bits clear when read. Their mask bits are TOHP_OOFM[A--D]. In STS-48 mode, only TOHP_OOFD[A] is valid. Receive Loss of Frame Delta. Delta bit indicates change of state for the loss-of-frame TOHP_LOF[A--D]. The delta bits clear when read. Their mask bits are TOHP_LOFM[A--D]. In STS-48 mode, only TOHP_LOFD[A] is valid. Receive Loss of Signal Delta. Delta bit indicates change of state for the loss-of-signal TOHP_LOS[A--D]. The delta bits clear when read. Their mask bits are TOHP_LOSM[A--D]. In STS-48 mode, only TOHP_LOSD[A] is valid. Receive Loss of Clock Delta. Delta bit indicates change of states for the loss-of-clock TOHP_LOC[A--D]. The delta bits clear when read. Their mask bits are TOHP_LOCM[A--D]. In STS-48 mode, only TOHP_LOCD[A] is valid. Reserved. 1, 1, 1, 1 3 1, 0, 0, 0 2 TOHP_LOFD [A--D] 1, 0, 0, 0 1 TOHP_LOSD [A--D] 1, 1, 1, 1 0 TOHP_LOCD [A--D] 1, 1, 1, 1 0x0803, 0x0805, 0x0807, 0x0809 15:2 -- 000 0000 0000 000 0 1 TOHP_TTOAC_ K1K2ERRE[A--D] Transmit TOAC K1and K2 Error Event. Event bits indicate when an error is detected between the true and complement K1/K2 values. Their mask bits are TOHP_TTOAC_K1K2ERRM[A--D]. In STS-48 mode, only TOHP_TTOAC_K1K2ERRE[A] is valid. J0 Mismatch Event Bits. Their mask bits are TOHP_J0MISM[A--D]. In STS-48 mode, only TOHP_J0MISE[A] is valid for J0 byte while TOHP_J0MISE[D--B] are used for Z0 bytes as TOHP_Z0DMOND[D--B][1]. 0 TOHP_J0MISE [A--D] 1 210 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 63. TOHP_RX_TX_STATE[A--D], 0x080A--0x080D, Receive/Transmit State Registers (RO) Address 0x080A-- 0x080D Bit 15 14 13:7 6 Name TOHP_LRDIMON[A--D] TOHP_LAISMON[A--D] -- TOHP_TLRDIINT[A--D] Function Line/Multiplex RDI State Bit. In STS-48 mode, only TOHP_LRDIMON[A] is valid. Line/Multiplex AIS State Bit. In STS-48 mode, only TOHP_LAISMON[A] is valid. Reserved. Transmit Line RDI Insert State Bit. State bit for inserting line RDI value into the K2[2:0] bits. In STS-48 mode, only TOHP_TLRDIINT[A] is valid. Signal Fail State Bit. In STS-48 mode, only TOHP_SF[A] is valid. Signal Degrade State Bit. In STS-48 mode, only TOHP_SD[A] is valid. Out-of-Frame. Active-high out-of-frame state bit. In STS-48 mode, only TOHP_OOF[A] is valid. Loss-of-Frame. Active-high loss-of-frame state bit. In STS-48 mode, only TOHP_LOF[A] is valid. Loss-of-Signal. Active-high loss-of-signal state bit. In STS-48 mode, only TOHP_LOS[A] is valid. Loss-of-Clock. Active-high loss-of-clock state bit. In STS-48 mode, only TOHP_LOC[A] is valid. When a loss-of-clock is detected for a line interface, associated status registers for that line interface may not be updated. Reset Default 0 0 0 0 5 4 3 TOHP_SF[A--D] TOHP_SD[A--D] TOHP_OOF[A--D] 0 0 0 2 1 TOHP_LOF[A--D] TOHP_LOS[A--D] 0 0 0 TOHP_LOC[A--D] 0 Agere Systems Inc. 211 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 64. TOHP_MSK[A--D][1--2], 0x080E--0x0815, Mask Bit Registers (R/W) Address 0x080E, 0x0810, 0x0812, 0x0814 Bit 15 Name TOHP_LRDIMONM [A--D] TOHP_LAISMONM [A--D] TOHP_RAPSBABLEM [A--D] TOHP_S1DMON4M [A--D] Function Line/Multiplex RDI Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_LRDIMONM[A] is valid. Line/Multiplex AIS Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_LAISMONM[A] is valid. APS Babble Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_RAPSBABLEM[A] is valid. Mask Bit for S1DMON4D When S1MON8or4CTL = 1. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_S1DMON4LSNM[A] is valid. Mask Bit for S1DMON8D. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_S1DMON8M[A] is valid. Reset Default 1 14 1 13 1 12 1 11 TOHP_S1DMON8M [A--D] 1 10 TOHP_K2DMONM[A--D] K2[2:0] Data Monitor Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_K2DMONM[A] is valid. TOHP_K1K2DMONM [A--D] K1K2 Data Monitor Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_K1K2DMONM[A] is valid. 1 9 1 8 TOHP_F1DMONM[A--D] F1 Data Monitor Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_F1DMONM[A] is valid. TOHP_TTOAC_PERRM Transmit TOAC Parity Error Mask. A 1 masks the corresponding occurrence of the alarm to the interrupt. All 4 bits are valid in every mode. TOHP_S1BABLEM [A--D] TOHP_SFM[A--D] TOHP_SDM[A--D] TOHP_OOFM[A--D] TOHP_LOFM[A--D] TOHP_LOSM[A--D] TOHP_LOCM[A--D] S1 Babbling Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48 mode, only TOHP_S1BABLEM[A] is valid. Signal Fail Mask Bit. Active-high signal fail mask bit. In STS-48 mode, only TOHP_SFM[A] is valid. Signal Degrade Mask Bit. Active-high signal degrade mask bit. In STS-48 mode, only TOHP_SDM[A] is valid. Out-of-Frame Mask Bit. Active-high out-of-frame mask bit. In STS-48 mode, only TOHP_OOFM[A] is valid. Loss-of-Frame Mask Bit. Active-high loss-of-frame mask bit. In STS-48 mode, only TOHP_LOFM[A] is valid. Loss-of-Signal Mask Bit. Active-high loss-of-signal mask bit. In STS-48 mode, only TOHP_LOSM[A] is valid. Loss-of-Clock Mask Bit. Active-high loss-of-clock mask bit. In STS-48 mode, only TOHP_LOCM[A] is valid. 1 0x080E 7 1 0x080E, 0x0810, 0x0812, 0x0814 6 1 5 4 3 2 1 0 1 1 1 1 1 1 212 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 64. TOHP_MSK[A--D][1--2], 0x080E--0x0815, Mask Bit Registers (R/W) (continued) Address 0x080F, 0x0811, 0x0813, 0x0815 Bit 15 14:2 Name TOHP_INTM[A--D] -- Function Interrupt Mask Bit. A 1 masks the alarm to the interrupt. Reserved. Reset Default 1 00 0000 0000 000 1 1 TOHP_TTOAC_ K1K2ERRM[A--D] Transmit TOAC K1 and K2 Error Mask Bits. Activehigh. Transmit TOAC K1 and K2 error mask bits. In STS-48 mode, only TOHP_TTOAC_K1K2ERRM[A] is valid. J0 Mismatch Mask Bit. A 1 masks the alarm to the TOHP_INTL[D--A] (Table 61) interrupt. 0 TOHP_J0MISM[A--D] 1 Table 65. TOHP_TRG[A--D], 0x0816--0x0819, Trigger Register 0 1 (R/W) Address 0x0816-- 0x0819 Bit 15:12 Name TOHP_RST_SWRS [A--D][3:0] Function Software Reset. For channels A to D, to enable software reset, write TOHP_RST_SWRS [A--D][3:0] to 1100 (0xC) and then write it to 0 to release the reset. Reserved. Transmit A1/A2 Error Enable. Enable signal to start the insertion of A2 errors in the outgoing frame. The number of consecutive errors is controlled by TOHP_TA1A2ERRINS[4:0]. TOHP_TA1A2ERREN[A] is valid in STS-48 mode. Signal Fail Clear. Allows the signal fail algorithm to be forced into the normal state. Signal Fail Set. Allows the signal fail algorithm to be forced into the failed state. Signal Degrade Clear. Allows the signal degrade algorithm to be forced into the normal state. Signal Degrade Set. Allows the signal degrade algorithm to be forced into the degraded state. Reset Default 0x0 11:5 4 -- TOHP_TA1A2ERREN [A--D] 0000 000 0 3 2 1 0 TOHP_SFCLEAR[A--D] TOHP_SFSET[A--D] TOHP_SDCLEAR[A--D] TOHP_SDSET[A--D] 0 0 0 0 Agere Systems Inc. 213 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 66. TOHP_CNTD[A--D][1--2], 0x081A--0x0821, Continuous N-Times Detect (CNTD) Values (R/W) Address 0x081A, 0x081C, 0x081E, 0x0820 Bit 15:12 Name TOHP_CNTDK2 [A--D][3:0] Function Continuous N-Times Detect for K2[2:0] Byte. The valid range for this register is 0x3-0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDK2[A] is valid. Continuous N-Times Detect for APS (K1, K2[7:3]) Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDK1K2[A] is valid. Reset Default 0x3 11:8 TOHP_CNTDK1K2 [A--D][3:0] 0x3 7:4 TOHP_CNTDF1[A--D][3:0] Continuous N-Times Detect for F1 Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDF1[A] is valid. TOHP_CNTDJ0Z0 [A--D][3:0] Continuous N-Times Detect for J0Z0 Bytes. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDJ0Z0[A] is valid. Reserved. Applies for version 2.2 and 2.3 only. APS Babble. Applies for version 2.2 and 2.3 only. 0 = Use either K1 and K2[7:3] or K1 and K2[7:0] 1 = K1 only 0x3 3:0 0x3 0x081B, 0x081D, 0x081F, 0x0821 15:13 12 -- -- 0x0 15:12 11:8 -- TOHP_CNTDS1BABLE [A--D][3:0] Reserved. Applies for version 2.0 only. Continuous N-Times Detect for S1 Byte Babbling. The valid range for this register is 0x3-- 0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, TOHP_CNTDS1BABLE[A] is valid. Continuous N-Times Detect for S1 Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, TOHP_CNTDS1[A] is valid. 0x0 0x5 7:4 TOHP_CNTDS1 [A--D][3:0] 0x3 3:0 TOHP_CNTDK1K2FRAME Continuous N-Times Detect for APS Frame. [A--D][3:0] The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, TOHP_CNTDK1K2FRAME[A] is valid. 0xC 214 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 67. TOHP_RCTL[A--D][1--2], 0x0822--0x0829, Receive Control [1--2] (R/W) Address 0x0822, 0x0824, 0x0826, 0x0828 Bit 15:14 Name TOHP_J0MONMODE [A--D][1:0] Function J0 Monitoring Mode. There are four modes as defined in the document. All four parameters TOHP_J0MONMODE[A--D] need to be set in STS-48 mode. 00 = The TOHP-48 will latch the value of the J0 byte every frame for a total of 16 bytes. The TOHP-48 will compare the incoming J0 byte with the next expected value (the expected value is obtained by cycling through the previously stored 16 received bytes in round-robin fashion) and set the event bit if different. 01 = This is the SONET-framing mode. The hardware looks for 0x0D followed by 0x0A to indicate that the next byte is the first byte of the path trace message. The J0 byte is continuously written into TOHP_RJ0DMON (Table 86) with the first byte residing at the first address. If any received byte does not match the previously received byte for its location, then the event bit is set. 10 = This is the SDH-framing mode. The hardware looks for the byte with the MSB set to 1, which indicates that the next byte is the second byte of the message. The rest of the operation is the same as the SONET framing mode. 11 = A new J0 byte TOHP_RJ0DMON[1][7:0] will be detected after TOHP_CNTDJ0Z0[3:0] (Table 66) consecutive consistent occurrences of a new pattern in the J0 overhead byte. Any changes to this byte are reported to TOHP_J0MISE[A--D] (Table 62) and TOHP_J0MISM[A--D] (Table 64). These event bits will act as delta bits indicating a change of state for the TOHP_RJ0DMON[1][7:0]. 13 TOHP_M1B7IGNORE [A--D] Bit 7 of M1 Byte Ignore. Bit 7 of M1 byte will be ignored if TOHP_M1B7IGNORE is set to 1 for that channel. Only TOHP_M1B7IGNORE[A] is valid for STS-48. Line AIS Software Insertion. Active-high for AIS insertion. In STS-48 mode, only TOHP_LAISINS[A] is valid. 0 Reset Default 00 12 TOHP_LAISINS[A--D] 0 Agere Systems Inc. 215 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 67. TOHP_RCTL[A--D][1--2], 0x0822--0x0829, Receive Control [1--2] (R/W) (continued) Address 0x0822, 0x0824, 0x0826, 0x0828 Bit 11 Name Function Reset Default 0 TOHP_LOF_AISINH[A--D] Loss-of-Frame AIS Inhibit. When set to logic 1, the AIS insertion will be inhibited in case of lossof-frame. TOHP_OOF_AISINH [A--D] Out-of-Frame AIS Inhibit. When set to logic 1, the AIS insertion will be inhibited in case of outof-frame. 10 0 9 TOHP_LOS_AISINH[A--D] Loss-of-Signal AIS Inhibit. When set to logic 1, the AIS insertion will be inhibited in case of lossof-signal. TOHP_SFB1B2SEL[A--D] Signal Fail B1/B2 Error Count Select. When set to logic 0, the B1 errors will be used by the signal fail error rate algorithm; otherwise, B2 errors are used. TOHP_SDB1B2SEL[A--D] Signal Degrade B1/B2 Error Count Select. When set to logic 0, the B1 errors will be used by the signal degrade error rate algorithm; otherwise, B2 errors are used. TOHP_CNTDB1SEL[A--D] Reset CNTD Counters on B1 Error. Active-high control bit to reset continuous N-times detect counters upon received B1 errors. Only TOHP_CNTDB1SEL[A] is valid for STS-48. TOHP_S1MON8OR4CTL [A--D] S1 Byte or Nibble. When set to logic 1, the S1 byte will be monitored as two nibbles. Otherwise, it is treated as a byte. Only TOHP_S1MON8OR4CTL[A] is valid for STS-48. 0 8 0 7 0 6 0 5 0 4 TOHP_K1K2_2OR1[A--D] K1 and K2 Treated as 2 Registers or 1. When set to 1, the K1 and K2 bytes will be treated as one 16-bit register. When K1 and K2 are treated as one 16-bit register, AIS-L detection is disabled. Both AIS-L and RDI-L monitoring will not be performed. When set to 0, the K1 and K2 bytes will be treated as 2 registers of size 13 bits (K1[7:0], K2[7:3]) and 3 bits (K2[2:0]). Only TOHP_K1K2_2OR1[A] is valid for STS-48. 0 216 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 67. TOHP_RCTL[A--D][1--2], 0x0822--0x0829, Receive Control [1--2] (R/W) (continued) Address 0x0822, 0x0824, 0x0826, 0x0828 Bit 3 Name TOHP_B2BITBLKCNT [A--D] Function B2 Error Count in Bit or Block. When set to 0, B2 check logic will count bit errors; otherwise, it counts block errors. Only TOHP_B2BITBLKCNT[A] is valid for STS-48. Descramble Inhibit Control. When a bit is set to 1, the descrambler for that is disabled. In STS-48 mode, all 4 bits need to be set to same value. B1 Error Count in Bit or Block. When set to 0, B1 check logic will count bit errors; otherwise, it counts block errors. Only TOHP_B1BITBLKCNT[A] is valid for STS-48. Receive Overhead Bypass. Control bit, when set to 1, causes the received data to pass through the block retimed. In STS-48 mode, all 4 bits need to be set to same value. M1 Error Count in Bit or Block. When set to 0, M1 check logic will count bit errors; otherwise, it counts block errors. Only TOHP_M1BITBLKCNT[C] is valid for STS-48. Reserved. Receive Validated K Bytes Control. When set to 1, received K1[5, 2, 1] and K2 [5, 3, 1] bytes are used to compare with received reversed K1[5, 2, 2] and K2 [5, 3, 2] bytes, respectively. Loss-of-Signal Detection Count. Set the number of consecutive all-zeros/ones pattern detected to declare receive LOS state for each channel. The time scale is in steps of 8 bits (for STS-3 and STS-12) or 32 (STS-48) at a time. Only TOHP_LOSDETCNT[A][12:0] is valid for STS-48. Reset Default 0 2 TOHP_DSCRINH[A--D] 0 1 TOHP_B1BITBLKCNT [A--D] 0 0 TOHP_ROH_BYPASS [A--D] 0 0x0823, 0x0825, 0x0827, 0x0829 15 TOHP_M1BITBLKCNT [A--D] 0 14 13 -- TOHP_RVALIDK_CTL [A--D] 0 0 12:0 TOHP_LOSDETCNT [A--D][12:0] 0x0000 Agere Systems Inc. 217 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 68. TOHP_RCTL[A--D][3], 0x082A--0x082D, Receive Control 3 (R/W) Address 0x082A Bit 15:14 Name TOHP_RREFSEL[1:0] Function Receive Reference Sync Select. Select reference output from channel A (00), B (01), C (10), and D (11). Receive Reference Sync Enable. Enables or disables output from the RXREF pin AK3 (Table 8). When set to 1, the receive 8 kHz 50% duty cycle sync output is high impedance. Receive Reference Sync Inhibit. When set to logic 0, the receive 8 kHz 50% duty cycle sync output. When set to 1, the RXREF (pin AK3 Table 8) output is forced to 0 during LOS, OOF, and LOF conditions. Reserved. Reserved. Reset Default 0 13 TOHP_RREF_EN 0 12 TOHP_RREF_INH 0 11:4 0x082B-- 0x082D 0x082A-- 0x082D 15:4 3 -- -- 000 00000 0x000 0 TOHP_RTOACSINH[A--D] Receive TOAC Sync Inhibit. When set to logic 1, the TOAC sync output, RXTOHF[A--D] is forced to high impedance. TOHP_RTOACCINH[A--D] Receive TOAC Clock Inhibit. When set to logic 1, the TOAC clock output is forced to high impedance. TOHP_RTOACDINH[A--D] Receive TOAC Data Inhibit. When set to logic 1, the TOAC data output is high impedance. TOHP_RTOAC_OEPINS [A--D] Receive TOAC Odd or Even Parity Insert. When set to logic 1, the output TOAC parity bit is even; otherwise, the parity is odd. 2 0 1 0 0 0 218 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 69. TOHP_TCTL[A--D][1--2], 0x082E--0x0835, Transmit Control [1--2] (R/W) Address 0x082E Bit 15 Name TOHP_TTOACINH Function Transmit TOAC Clock and Sync Inhibit. When set to 1, the transmit TOAC clock and sync are high impedance. Transmit TOAC K1K2 Byte Control. Control bits, when set to logic 0, the value in registers TOHP_TK1DINS[7:0] and TOHP_TK2DINS[7:3] will be inserted into the K1K2 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the K1K2 byte. TOHP_TTOAC_K1K2[A] is valid for STS-48 mode only. Transmit TOAC Validated K1K2 Byte Control. Control bit, when set to 1, the reversed K1 K2 bytes are compared to the received K1 K2 bytes (all 16 bits) before the insertion; otherwise, TTOAC received K1K2 bytes are inserted. Reset Default 0 0x0830 15 TOHP_TTOAC_K1K2[A] 0 0x0832 15 TOHP_TTOAC_ VALIDK_CTL 0 0x0834 15 TOHP_TK2SWHWINS_INH Transmit K2 Byte Software and Hardware Control. Control bit, when set to 1, K2[2:0] = TTOAC_K1K2[2:0] or TK2SINS[2:0]. When TK2SWHW_INT clear to 0 and LRDIINT = 1, the K2[2:0] is set to 110 (RDI-L). TOHP_TJ0INS[A--D] Transmit J0 Insert Control. Control bit, when set to a logic 1, inserts the value in TOHP_TJ0DINS[A--D][64:1][7:0] into the outgoing J0 bytes; otherwise, the insert value depends on TOHP_TTOAC_J0[A--D] registers. TJ0INS[A] is valid in STS-48 mode.* Transmit TOAC J0 Byte Control. Control bits, when set to logic 0, cause the default value 00000000 for SONET or 11111111 for SDH to be inserted into the J0 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the J0 byte. TOHP_TTOAC_J0[A] is valid for STS-48 mode.* Transmit TOAC K1K2 Byte Control. Control bits, when set to logic 0, the value in registers TOHP_TK1DINS[7:0] and TOHP_TK2DINS[7:3] will be inserted into the K1K2 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the K1K2 byte. TOHP_TTOAC_K1K2[A] is valid for STS-48 mode. 0 0x082E, 0x0830, 0x0832, 0x0834 14 0 13 TOHP_TTOAC_J0[A--D] 0 0x0830, 0x0832, 0x0834 12 TOHP_TTOAC_ K1K2[B--D] 0 0x082E TOHP_TTOAC_OEPMON Transmit TOAC Odd or Even Parity Monitor. When set to 1, even parity is checked for transmit TOAC channels; otherwise, odd parity is checked. 0 * TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0. Agere Systems Inc. 219 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 69. TOHP_TCTL[A--D][1--2], 0x082E--0x0835, Transmit Control [1--2] (R/W) (continued) Address 0x082E, 0x0830, 0x0832, 0x0834 Bit 11 Name Function Reset Default 0 TOHP_TTOAC_INS[A--D] Transmit TOAC Byte Control. Control bits, when set to logic 0, cause the default value 00000000 for SONET or 11111111 for SDH to be inserted into all overhead bytes without specific insert control bits in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into all overhead bytes without specific insert control bits. TOHP_TTOAC_INS[A] is valid for STS-48 mode. TOHP_TTOAC_E2[A--D] Transmit TOAC E2 Byte Control. Control bits, when set to logic 0, cause the default value to be inserted into the E2 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the E2 byte. TOHP_TTOAC_E2[A] is valid for STS-48 mode. 10 0 9 TOHP_TTOAC_S1[A--D] Transmit TOAC S1 Byte Control. Control bits, when set to logic 0, cause the default value to be inserted into the S1 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the S1 byte. TOHP_TTOAC_S1[A] is valid for STS-48 mode. TOHP_TTOAC_D4TO12 [A--D] Transmit TOAC D4 to D12 Byte Control. Control bits, when set to logic 0, cause the default value to be inserted into the D4 to D12 bytes in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the D4 to D12 bytes. TOHP_TTOAC_D4TO12[A] is valid for STS-48 mode. Note: When TOHP_TTOAC_K1K2 = 1 and TOHP_TTOAC_VALIDK_CTL = 1, TOHP_TTOAC_D4TO12[A--D] has 0 8 0 * TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0. 220 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 69. TOHP_TCTL[A--D][1--2], 0x082E--0x0835, Transmit Control [1--2] (R/W) (continued) Address 0x082E, 0x0830, 0x0832, 0x0834 Bit 7 Name TOHP_TTOAC_D1TO3 [A--D] Function Transmit TOAC D1 to D3 Byte Control. Control bits, when set to logic 0, cause the default value to be inserted into the D1 to D3 bytes in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the D1 to D3 bytes. TOHP_TTOAC_D1TO3[A] is valid for STS-48 mode. Transmit TOAC F1 Byte Control. Control bits, when set to logic 0, cause the default value to be inserted into the F1 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the F1 byte. TOHP_TTOAC_F1[A] is valid for STS-48 mode. Reset Default 0 6 TOHP_TTOAC_F1[A--D] 0 5 TOHP_TTOAC_E1[A--D] Transmit TOAC E1 Byte Control. Control bits, when set to logic 0, cause the default value to be inserted into the E1 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value to be inserted into the E1 byte. TOHP_TTOAC_E1[A] is valid for STS-48 mode. TOHP_TAPSBABLEINS [A--D] Transmit APS Babble Insert. Control bit, when set to 1, causes an inconsistent APS byte (K1[7:0], K2[7:3]) to be inserted into the outgoing STS-M frame until this register is reset to 0. Transmit M1 Error Insert. Once this register is set to 1, an error will be inserted continuously into the outgoing M1 byte until this register is reset to 0. In STS-48 mode, only TOHP_TM1_ERR_INS[C] is valid. Transmit M1 REI-L Inhibit. Active high to inhibit automatic insertion of REI-L (MS-REI). In STS-48 mode, only TOHP_TM1_REIL_INH[C] is valid. Transmit F1 Insert Control. Control bit, when set to a logic 1, inserts the value in TOHP_TF1DINS[7:0] into the outgoing F1 byte in the STS-M frame; otherwise, the insert value depends on TTOAC_F1 register. TOHP_TF1INS[A] is valid in STS-48 mode. Transmit S1 Insert Control. Control bit, when set to a logic 1, inserts the value in TOHP_TS1DINS[7:0] into the outgoing S1 byte in the STS-M frame; otherwise, the insert value depends on TOHP_TTOAC_S1 bit. TOHP_TS1INS[A] is valid in STS-48 mode. 0 4 0 3 TOHP_TM1_ERR_INS [A--D] 0 2 TOHP_TM1_REIL_INH [A--D] 0 1 TOHP_TF1INS[A--D] 1 0 TOHP_TS1INS[A--D] 1 * TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0. Agere Systems Inc. 221 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 69. TOHP_TCTL[A--D][1--2], 0x082E--0x0835, Transmit Control [1--2] (R/W) (continued) Address 0x082F, 0x0831, 0x0833, 0x0835 Bit 15:11 Name TOHP_TA1A2ERRINS [A--D][4:0] Function Number of Consecutive Frames with A2 Error Insertion. These bits specify the number of consecutive frames to be inserted with a frame error of A2. Reset Default 0x00 10 TOHP_TOH_BYPASS[A--D] Transmit Overhead Bypass. Control bit, when set to 1, causes the frame from PT pass through untouched. In STS-48 mode, all 4 bits need to be set to same value. TOHP_SCRINH[A--D] Scramble Inhibit. When set to high, the scrambling is inhibited. In STS-48 mode, all 4 bits need to be set to same value. Transmit B1 Error Insertion. When set to high, the B1 output will be inverted. For STS-48, only TOHP_TB1ERRINS[A] is valid. Transmit B2 Error Insertion. When set to high, all B2 bytes in that channel will be inverted. All 4 bits are valid in STS-48 mode. Transmit 20-Frame Line RDI Inhibit. Control bits, when set to high, inhibit the requirement of minimum 20 frame RDI insertion. 0 9 0 8 TOHP_TB1ERRINS[A--D] 0 7 TOHP_TB2ERRINS[A--D] 0 6 TOHP_TIMER_LRDIINH [A--D] 0 5 4 3 2 1 0 TOHP_TSF_LRDIINH[A--D] Transmit Signal Fail Line RDI Inhibit. Activehigh. TOHP_TLAISMON_LRDIINH Transmit Line-AIS-Monitored Line RDI [A--D] Inhibit. Active-high. TOHP_TLOF_LRDIINH [A--D] TOHP_TOOF_LRDIINH [A--D] TOHP_TLOS_LRDIINH [A--D] TOHP_TLOC_LRDIINH [A--D] Transmit Loss-of-Frame Line RDI Inhibit. Active-high. Transmit Out-of-Frame Line RDI Inhibit. Active-high. Transmit Loss-of-Signal Line RDI Inhibit. Active-high. Transmit Loss-of-Clock Line RDI Inhibit. Control bits, when set to a logic 1, cause the associated failure not to contribute to the automatic insertion of RDI-L; otherwise, the associated alarm contributes to the generation of RDI-L. 0 0 0 0 0 0 * TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0. 222 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 70. TOHP_TCTL[A--D][3], 0x0836--0x0839, Transmit Control 3 (R/W) Address 0x0836-- 0x0839 Bit 15 Name TOHP_TAPSINS[A--D] Function Transmit APS Software Insert. When set to logic 1, the value in registers TOHP_TK1DINS[7:0] and TOHP_TK2DINS[7:3], or TTOAC value controlled by TOHP_TTOAC_K1K2, will be inserted into K1[7:0] and K2[7:3] in the transmit frame; otherwise, data from TX_RAWK[15:3] will be inserted. Transmit K2 Software Insert. 11 = TTOAC_K1K2[2:0]. 10 = TK2DINS[2:0]. 01 = Hardware insert is enabled for RDI-L (110). 00 = The value in TX_RAWK[2:0] will be inserted into K2[2:0] in the transmit frame. Transmit Validated K Bytes Control. When set to 1, reversed K1[5, 2, 1] and K2 [5, 3, 1] bytes will be inserted into K1[5, 2, 2] and K2 [5, 3, 2] bytes, respectively; otherwise, default value (all 1s for SDH and all 0s for SONET) will be inserted at this location. Force Line AIS in the Selected Output Time Slot. Active-high. For OC-3, the index [0:2] corresponds to time slot 1-2-3; for OC-12, the index[0:11] corresponds to time slot 1-4-7-10-2-58-11-3-6-9-12; and for OC-48, the index [A][0:11] is for time slot 1-13-25-37-2-14-26-38-3-15-2739, [B][0:11] for 4-16-28-40-5-17-29-41-6-18-3042, [C][0:11] for 7-19-31-43-8-20-32-44-9-21-3345, and [D][0:11] for 10-22-34-46-11-23-35-4712-24-36-48. 0 Reset Default 1 14:13 TOHP_TK2SINS [A--D][1:0] 0x0 12 TOHP_TVALIDK_CTL [A--D] 11:0 TOHP_TAISLINS [A--D][11:0] 0x000 Agere Systems Inc. 223 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 71. TOHP_SD_SETR[A--D][1--2], 0x083A--0x0841, Signal Degrade BER Algorithm Set Control Registers [1--2] (R/W) Address 0x083A, 0x083C, 0x083E, 0x0840 0x083B, 0x083D, 0x083F, 0x0841 0x083B, 0x083D, 0x083F, 0x0841 Bit 15:0 Name TOHP_SDNSSET [A--D][17:2] Function Signal Degrade Ns Set. Number of frames in a monitoring block for signal degrade (SD) of slice [A--D] is equal to TOHP_SDNSSET[A--D][17:0], respectively. Reset Default 0x00000 1:0 TOHP_SDNSSET [A--D][1:0] 15:9 TOHP_SDMSET [A--D][6:0] Signal Degrade M Set. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is above this threshold, then signal degrade is set. 0x00 8:2 TOHP_SDLSET[A--D][6:0] Signal Degrade L Set. Error threshold for determining if a monitoring block is bad. 0x00 Table 72. TOHP_SD_SETR[A--D][3], 0x0842--0x0845, Signal Degrade BER Algorithm Set Control Register [3] (R/W) Address 0x0842-- 0x0845 Bit 15:0 Name TOHP_SDBSET [A--D][15:0] Function Signal Degrade B Set. Number of monitoring blocks. Reset Default 0x0000 224 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 73. TOHP_SD_CLEARR[A--D][1--2], 0x0846--0x084D, Signal Degrade BER Algorithm Clear Control Registers [1--2] (R/W) Address 0x0846, 0x0848, 0x084A, 0x084C 0x0847, 0x0849, 0x084B, 0x084D 0x0847, 0x0849, 0x084B, 0x084D Bit 15:0 Name TOHP_SDNSCLEAR [A--D][17:2] Function Signal Degrade Ns Clear. Number of frames in a monitoring block for SD of slice[A--D] is equal to TOHP_SDNSCLEAR[A--D][17:0], respectively. Reset Default 0x00000 1:0 TOHP_SDNSCLEAR [A--D][1:0] 15:9 TOHP_SDMCLEAR [A--D][6:0] Signal Degrade M Clear. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is below this threshold, then SD is cleared. Signal Degrade L Clear. Error threshold for determining if a monitoring block is bad. 0x00 8:2 TOHP_SDLCLEAR [A--D][6:0] 0x0 Table 74. TOHP_SD_CLEARR[A--D][3], 0x084E--0x0851, Signal Degrade BER Algorithm Clear Control Register [3] (R/W) Address 0x084E-- 0x0851 Bit 15:0 Name TOHP_SDBCLEAR [A--D][15:0] Function Signal Degrade B Clear. Number of monitoring blocks. Reset Default 0x0000 Agere Systems Inc. 225 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 75. TOHP_SF_SETR[A--D][1--2], 0x0852--0x0859, Signal Fail Set BER Algorithm Control Registers [1--2] (R/W)* Address 0x0852, 0x0854, 0x0856, 0x0858 0x0853, 0x0855, 0x0857, 0x0859 0x0853, 0x0855, 0x0857, 0x0859 Bit 15:0 Name TOHP_SFNSSET [A--D][17:2] Function Signal Fail Ns Set. Number of frames in a monitoring block for signal fail (SF) of slice[A--D] is equal to TOHP_SFNSSET[A--D][17:0], respectively. Reset Default 0x00000 1:0 TOHP_SFNSSET [A--D][1:0] 15:10 TOHP_SFMSET [A--D][5:0] Applies for version 2.2 and 2.3 only. Signal Fail M Set. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is above this threshold, then signal fail is set. 0x00 9:2 TOHP_SFLSET[A--D][7:0] Signal Fail L Set. Error threshold for determinApplies for version 2.2 ing if a monitoring block is bad. and 2.3 only. TOHP_SFMSET [A--D][6:0] Applies for version 2.0 only. Signal Fail M Set. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is above this threshold, then signal fail is set. 0x00 15:9 0x00 8:2 TOHP_SFLSET[A--D][6:0] Signal Fail L Set. Error threshold for determinApplies for version 2.0 ing if a monitoring block is bad. only. 0x00 * See page 208 for the description of reading and writing parameters of more than 16 bits. Table 76. TOHP_SF_SETR[A--D][3], 0x085A--0x085D, Signal Fail BER Algorithm Set Control Register [3] (R/W) Address 0x085A-- 0x085D Bit 15:0 Name TOHP_SFBSET [A--D][15:0] Function Signal Fail B Set. Number of monitoring blocks. Reset Default 0x0000 226 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 77. TOHP_SF_CLEARR[A--D][1--2], 0x085E--0x0865, Signal Fail BER Algorithm Clear Control Registers [1--2] (R/W)* Address 0x085E, 0x0860, 0x0862, 0x0864 0x085F, 0x0861, 0x0863, 0x0865 0x085F, 0x0861, 0x0863, 0x0865 Bit 15:0 Name TOHP_SFNSCLEAR [A--D][17:2] Function Signal Fail Ns Clear. Number of frames in a monitoring block for SD of slice[A--D] is equal to TOHP_SFNSCLEAR[A--D][17:0], respectively. Reset Default 0x00000 1:0 TOHP_SFNSCLEAR [A--D][1:0] 15:9 TOHP_SFMCLEAR [A--D][6:0] Signal Fail M Clear. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is below this threshold, then SF is cleared. Signal Fail L Clear. Error threshold for determining if a monitoring block is bad. 0x00 8:2 TOHP_SFLCLEAR [A--D][6:0] 0x0 * See page 208 for the description of reading and writing parameters of more than 16 bits. Table 78. TOHP_SF_CLEARR[A--D][3], 0x0866--0x0869, Signal Fail BER Algorithm Clear Control Register [3] (R/W) Address 0x0866-- 0x0869 Bit 15:0 Name TOHP_SFBCLEAR [A--D][15:0] Function Signal Fail B Clear. Number of monitoring blocks. Reset Default 0x0000 Agere Systems Inc. 227 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Figure 34 illustrates the parameters used in determining the bit error detection rate. NUMBER OF MONITORING BLOCKS SFBSET[A--D] OR SDBSET[A--D] (IN THIS CASE, 3) NUMBER OF FRAMES IN A MONITORING BLOCK SFNSSET[A--D] OR SDNSSET[A--D], SFNSCLEAR[A--D] OR SDNSCLEAR[A--D] (IN THIS CASE, 7) FRAME BOUNDARY BLOCK BOUNDARY SFLSET[A--D] OR SDLSET[A--D] SFLCLEAR[A--D] OR SDLCLEAR[A--D] SFMSET[A--D] OR SDMSET[A--D] SFMCLEAR[A--D] OR SDMCLEAR[A--D] ACCUMULATED BIP ERROR COUNT: B1 OR B2 FOR LINE B3 FOR PATH BLOCK GOOD/BAD COUNT 5-7934(F) Figure 34. Signal Degrade and Failure Parameters for BER MARS2G5 P-Pro provides a method to monitor the BER at the line and path layers. The following explains the algorithm for this method to set and clear the BER. The algorithm for this method is the same for setting and clearing the BER; the only difference is the programmed values. MARS2G5 P-Pro includes two complete sets of identical counters, one used to determine signal fail (SF) and one used to determine signal degrade (SD). The only difference between SF and SD is the provisioned values. The same algorithm is used for both the line and path layers of SONET. The algorithm uses four sets of counters: labeled Ns (number of frames), L (number of errors), M (number of errored blocks), and B (total number of blocks). Each of these counters has different values that are provisioned to either set the BER high or clear the BER indication. The algorithm works by counting blocks, i.e., a preset number of SONET/SDH frames (Ns). If the number of errors in the block exceeds the provisioned level (L), then the errored block counter is incremented by 1; otherwise, the number of blocks in error stays at its current level. At this point, the frame counter and the error counter are reset back to 0 and counting is started again. At the end of a preset number of blocks (B), the count in the errored block counter is compared against a provisioned threshold (M). If the total number of blocks in error equals or exceeds the provisioned threshold (M), then the BER alarm is raised. If the total number of blocks in error is less than the provisioned amount (M), then the BER alarm is cleared. In other words: given the error distribution as defined by the GR-253 standard, the probability of getting L BIP errors out of 8 * N BIP bits in M out of B blocks. The values used by the counters are determined by the state of the algorithm. If the BER state is low, then the set parameters are used. If the BER state is high, then the clear parameters are used. 228 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 79 and Table 80 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to set and clear the BER indicator. SF registers are 0x852--0x0869 (Table 75--Table 78) and SD registers are 0x083A--0x0851 (Table 71--Table 74). All SF/SD set and clear values are hexadecimal. Table 79. Ns, L, M, and B Values to Set the BER Indicator Note: The Ns, L, M, and B values shown are the numbers to be provisioned in the MARS2G5 P-Pro. The actual values of Ns, M, and B of the BER algorithm are 1 greater than the values shown, excluding L. Mode BER SF/SD Set Values Actual Number of Frames B 3D 7 7 7 9 9 F -- 62 48 384 3840 47250 465000 4160000 -- Probability of Detecting L Errors (%) @BER 99.96 72.70 71.34 71.34 69.74 68.07 56.90 -- @BER/2 85.13 7.28 10.08 10.09 9.44 8.82 11.25 -- Probability of Declaring SF/SD (%) @BER 97.68 96.06 95.19 95.19 95.07 98.47 96.52 -- @BER/2 0.00 0.16 0.52 0.52 0.13 0.82 0.60 -- IntegraMaximum tion Time Number of Frames (s) 0.008 0.013 0.1 1 10 83 667 -- 64 104 800 8000 80000 664000 5336000 -- Ns STS-3/ STM-1 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 0 5 2F 1DF 1274 B5A3 3F79F -- L 7 A 8 8 8 8 5 -- M 3D 3 3 3 4 3 5 -- STS-12/ STM-4 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 0 1 C 7F 4FA 31CD 1F20B -- 20 C 9 9 9 9 9 -- 3F 6 3 3 3 3 3 -- 3F A 8 8 8 8 8 -- 64 22 117 1152 11475 114750 1147500 -- 100.00 84.92 67.93 66.19 65.75 65.75 65.75 -- 88.43 9.64 7.17 6.66 6.53 6.53 6.53 -- 100.00 98.38 96.48 95.46 95.16 95.16 95.16 -- 0.04 0.00 0.25 0.19 0.18 0.18 0.18 -- 0.008 0.008 0.025 0.25 2.5 21 167 -- 64 64 200 2000 20000 168000 1336000 -- STS-48/ STM-16 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 0 0 4 1F 139 C1B 765B -- 4B F B 8 8 8 7 -- 3F 3F 35 8 8 7 6 -- 3F 3F 3F E E E A -- 64 64 320 480 4710 46500 333300 -- 100.00 99.95 90.60 77.55 75.80 74.58 82.92 -- 100.00 58.97 16.25 13.09 12.15 11.54 19.71 -- 100.00 96.89 96.47 96.69 95.17 98.09 97.29 -- 100.00 0.00 0.00 0.00 0.00 0.01 0.18 -- 0.008 0.008 0.008 0.0625 0.625 5.2 42 -- 64 64 64 500 5000 41600 336000 -- Agere Systems Inc. 229 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 80. Ns, L, M, and B Values to Clear the BER Indicator Note: The Ns, L, M, and B values shown are the numbers to be provisioned in the MARS2G5 P-Pro. The actual values of Ns, M, and B of the BER algorithm are 1 greater than the values shown, excluding L. Mode BER SF/SD Set Values Actual Probability of Number Detecting L Errors of Frames (%) B -- 7 7 7 7 9 9 F -- 8 48 384 3840 47250 465000 4160000 @BER * 5 -- 85.13 93.01 84.42 84.42 83.66 82.86 46.31 Probability of Clearing SF/SD (%) IntegraMaximum tion Time Number of Frames (s) -- 0.013 0.1 1 10 83 667 6670 -- 104 800 8000 80000 664000 5336000 53360000 Ns STS-3/ STM-1 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 -- 0 5 2F 1DF 1274 B5A3 3F79F L -- 7 3 3 3 3 3 3 M -- 3 3 3 3 4 3 2 @BER @BER * 5 @BER -- 0.39 11.33 6.84 6.84 6.59 6.35 1.48 -- 0.27 0.01 0.34 0.34 0.22 0.03 0.50 -- 100.00 99.21 99.88 99.88 99.98 99.75 99.84 STS-12/ STM-4 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 -- 0 1 C 7F 4FA 31CD 1F20B -- 8 3 3 3 3 3 3 -- 6 8 3 3 3 3 3 -- 6 A 8 8 8 8 8 -- 7 22 117 1152 11475 114750 1147500 -- 100.00 98.36 87.99 87.34 87.17 87.17 87.17 -- 51.54 20.51 8.23 7.94 7.87 7.87 7.87 -- 0.00 0.07 0.02 0.02 0.03 0.03 0.03 -- 99.03 100.00 99.59 99.64 99.65 99.65 99.65 -- 0.008 0.025 0.25 2.5 21 167 1670 -- 64 200 2000 20000 168000 1336000 13360000 STS-48/ STM-16 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 -- 0 0 4 1F 139 C1B 765B -- 20 3 4 3 3 3 3 -- 27 D D 6 6 6 4 -- 3F E 3F 13 13 13 A -- 64 15 320 640 6280 62000 333300 -- 100.00 100.00 95.07 87.34 86.52 85.95 84.89 -- 45.99 60.11 7.28 7.94 7.61 7.38 7.00 -- 0.00 0.00 0.00 0.00 0.00 0.00 0.03 -- 99.42 99.47 99.98 99.94 99.95 99.96 99.95 -- 0.008 0.008 0.0625 0.625 5.2 42 420 -- 64 64 500 5000 41600 336000 3360000 230 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 81. TOHP_B1ECNTR[A--D], 0x086A--0x086D, B1 Error Count (RO) Address 0x086A-- 0x086D Bit 15:0 Name TOHP_B1ECNT [A--D][15:0] Function B1 Error Count. The value of internal running counter is transferred into this holding register at the 0-to-1 transition of PMRST (pin D7) (Table 10) signal. Reset Default 0x0000 Table 82. TOHP_B2ECNTR[A--D][1--2], 0x086E--0x0875, B2 Error Count (RO) Address 0x086E, 0x0870, 0x0872, 0x0874 0x086F, 0x0871, 0x0873, 0x0875 Bit 5:0 15:0 Name TOHP_B2ECNT [A--D][21:16] TOHP_B2ECNT [A--D][15:0] Function B2 Error Count. The value of internal running counter is transferred into this holding register at the 0-to-1 transition of PMRST (pin D7) (Table 10) signal. Reset Default 0x000000 Table 83. TOHP_M1ECNTR[A--D][1--2], 0x0876--0x087D, M1 Error Count (RO) Note:Stream C of the M1 error count registers 0x087A[4:0] and 0x087B[15:0] must be used for OC-48 mode. Address 0x0876, 0x0878, 0x087A, 0x087C 0x0877, 0x0879, 0x087B, 0x087D Bit 4:0 15:0 Name TOHP_M1ECNT [A--D][20:16] TOHP_M1ECNT [A--D][15:0] Function M1 Error Count. The value of internal running counter is transferred into this holding register at the 0-to-1 transition of PMRST (pin D7) (Table 10) signal. Reset Default 0x000000 Agere Systems Inc. 231 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 84. TOHP_TOH_INSR[A--D][1--2], 0x087E--0x0885, Transmit OH Insert Value (R/W) Address 0x087E, 0x0880, 0x0882, 0x0884 Bit 15:8 7:0 0x087F, 0x0881, 0x0883, 0x0885 15:8 7:0 Name TOHP_TF1DINS [A--D][7:0] TOHP_TS1DINS [A--D][7:0] TOHP_TK2DINS [A--D][7:0] TOHP_TK1DINS [A--D][7:0] Function Transmit F1 Byte Value. Register value is inserted into the transmit F1 byte. Transmit S1 Byte Value. Register value is inserted into the transmit S1 byte. Transmit K2 Byte Value. Register value is inserted into the transmit K2 byte. Transmit K1 Byte Value. Register value is inserted into the transmit K1 byte. Reset Default 0x00 0x00 0x00 0x00 Table 85. TOHP_RMONR[A--D][1--3], 0x0886--0x0891, Receive Monitor Value (RO) Address 0x0886, 0x0889, 0x088C, 0x088F Bit 15:8 7:0 0x0887, 0x088A, 0x088D, 0x0890 15:8 7:0 0x0888, 0x088B, 0x088E, 0x0891 7:0 Name TOHP_F1DMON1 [A--D][7:0] TOHP_F1DMON0 [A--D][7:0] TOHP_K2DMON [A--D[7:0] TOHP_K1DMON [A--D][7:0] TOHP_S1DMON [A--D][7:0] Function Receive F1 Previous Monitor Value. Receive F1 Current Monitor Value. Receive K2 Monitor Value. Receive K1 Monitor Value. Receive S1 Monitor Value. Reset Default 0x00 0x00 0x00 0x00 0x00 232 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 86. TOHP_RJ0DMONR[A--D][1--32], 0x0892--0x0911, Receive J0/Z0 Monitor Value Registers (RO) Address 0x0892-- 0x08B1 Bit 15:8 7:0 Name TOHP_RJ0DMON [A][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON [A][1, 3, 5, . . ., 63][7:0] Function Reset Default Receive J0 Monitor Value. These registers cap- 0x0000 ture a 64-byte sequence from the J0 byte of each channel. In STS-48 mode, TOHP_RJ0DMON[A] [1--64][7:0] is valid for J0 bytes while TOHP_RJ0DMON[B--D][1][7:0] are used for TOHP_Z0DMON[B--D][1][7:0] (see TOHP-48 register map (Table 93)). Receive J0 Monitor Value. See functional description above. 0x0000 0x08B2-- 0x08D1 15:8 7:0 TOHP_RJ0DMON [B][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON [B][1, 3, 5, . . ., 63][7:0] TOHP_RJ0DMON [C][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON [C][1, 3, 5, . . ., 63][7:0] TOHP_RJ0DMON [D][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON [D][1, 3, 5, . . ., 63][7:0] 0x08D2-- 0x08F1 15:8 7:0 Receive J0 Monitor Value. See functional description above. 0x0000 0x08F2-- 0x0911 15:8 7:0 Receive J0 Monitor Value. See functional description above. 0x0000 Agere Systems Inc. 233 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 87. TOHP_TJ0DINSR[A--D][1--32], 0x0912--0x09A9, Transmit J0/Z0 Insert Value Registers (R/W) Address 0x0912-- 0x0931 Bit 15:8 7:0 Name TOHP_TJ0DINS [A][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS [A][1, 3, 5, . . ., 63][7:0] Function Reset Default Transmit J0 Insert Value. These registers allow 0x0000 a 64-byte sequence to be inserted into the J0 byte of each channel. In STS-48 mode, TOHP_TJ0DINS[A][1--64][7:0] is valid for J0 bytes while TOHP_TJ0DINS[B-- D][1][7:0] are used for TOHP_TZ0DINS[B--D][1, 2, 3][7:0] (see TOHP-48 register map (Table 93)). Transmit J0 Insert Value. See functional description above. 0x0000 0x0932-- 0x0951 15:8 7:0 TOHP_TJ0DINS [B][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS [B][1, 3, 5, . . ., 63][7:0] TOHP_TJ0DINS [C][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS [C][1, 3, 5, . . ., 63][7:0] TOHP_TJ0DINS [D][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS [D][1, 3, 5, . . ., 63][7:0] 0x0952-- 0x0971 15:8 7:0 Transmit J0 Insert Value. See functional description above. 0x0000 0x0972-- 0x09A9 15:8 7:0 Transmit J0 Insert Value. See functional description above. 0x0000 234 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 88. TOHP_TZ0DINSR[A--D][1--6], 0x09AA--0x09C1, Transmit Z0 Insert Value Registers (R/W) Address 0x09AA Bit 15:8 Name Function Reset Default -- TOHP_TZ0DINS[A][2][7:0] Transmit Z0 Insert Value. Register values are inserted into the transmit Z0 bytes. In STS-3 mode, TOHP_TZ0DINS[A--D][2--3] are valid; in STS-12 mode, TOHP_TZ0DINS[A--D][2-- 12][7:0] are valid; and in STS-48 mode, all 44 TOHP_TZ0DINS bytes plus TOHP_TJ0DINS[B-- D][1][7:0] (Table 87) are used for 47 Z0 byte values (see Table 89 for Z0 byte ordering in these registers). 7:0 0x09AB-- 0x09AF 15:8 7:0 0x09B0 0x09B1-- 0x09B5 15:8 7:0 15:8 7:0 0x09B6 0x09B7-- 0x09BB 15:8 7:0 15:8 7:0 0x09BC 0x09BD-- 0x09C1 15:8 7:0 15:8 7:0 -- TOHP_TZ0DINS[A] [4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[A] [3, 5, 7, 9, 11][7:0] TOHP_TZ0DINS[B][2][7:0] -- TOHP_TZ0DINS[B] [4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[B] [3, 5, 7, 9, 11][7:0] TOHP_TZ0DINS[C][2][7:0] -- TOHP_TZ0DINS[C] [4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[C] [3, 5, 7, 9, 11][7:0] TOHP_TZ0DINS[D][2][7:0] -- TOHP_TZ0DINS[D] [4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[D] [3, 5, 7, 9, 11][7:0] Reserved. Transmit Z0 Insert Value. See functional description above. -- 0x0 0x0 -- Reserved. Transmit Z0 Insert Value. See functional description above. 0x0 0x0 0x0 0x0 Reserved. Transmit Z0 Insert Value. See functional description above. -- 0x0 0x0 0x0 Reserved. Transmit Z0 Insert Value. See functional description above. -- 0x0 0x0 Agere Systems Inc. 235 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Descriptions (continued) Table 89. Z0 Byte Ordering STS-48 Mode for Z0-1--Z0-47 Channel 1 A B C D J0 Z0-3 Z0-6 Z0-9 2 Z0-12 Z0-15 Z0-18 Z0-21 3 Z0-24 Z0-27 Z0-30 Z0-33 4 Z0-36 Z0-39 Z0-42 Z0-45 5 Z0-1 Z0-4 Z0-7 Z0-10 Time Slots [1--12] 6 Z0-13 Z0-16 Z0-19 Z0-22 7 Z0-25 Z0-28 Z0-31 Z0-34 8 Z0-37 Z0-40 Z0-43 Z0-46 9 Z0-2 Z0-5 Z0-8 Z0-11 10 Z0-14 Z0-17 Z0-20 Z0-23 11 Z0-26 Z0-29 Z0-32 Z0-35 12 Z0-38 Z0-41 Z0-44 Z0-47 Table 90. Z0 Byte Ordering STS-12 Mode for Z0-1--Z0-11 Channel 1 A B C D J0 J0 J0 J0 2 Z0-3 Z0-3 Z0-3 Z0-3 3 Z0-6 Z0-6 Z0-6 Z0-6 4 Z0-9 Z0-9 Z0-9 Z0-9 5 Z0-1 Z0-1 Z0-1 Z0-1 Time Slots [1--12] 6 Z0-4 Z0-4 Z0-4 Z0-4 7 Z0-7 Z0-7 Z0-7 Z0-7 8 Z0-10 Z0-10 Z0-10 Z0-10 9 Z0-2 Z0-2 Z0-2 Z0-2 10 Z0-5 Z0-5 Z0-5 Z0-5 11 Z0-8 Z0-8 Z0-8 Z0-8 12 Z0-11 Z0-11 Z0-11 Z0-11 Table 91. Z0 Byte Ordering STS-3 Mode for Z0-1--Z0-2 Channel A B C D Time Slots [1--3] 1 J0 J0 J0 J0 2 Z0-1 Z0-1 Z0-1 Z0-1 3 Z0-2 Z0-2 Z0-2 Z0-2 Table 92. TOHP_SCRATCHR, 0x09C2, TOHP-48 Scratch Register (R/W) Address 0x09C2 Bit 15:0 Name TOHP_SCRATCH[15:0] Function TOHP-48 Scratch Register. Allows the control system to verify read and write operations to the device without affecting device operation. Reset Default 0x0000 236 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map Table 93. TOHP-48 Register Map Note: Shading denotes reserved bits. Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOHP-48 MODE--R/W and Block Version--RO 0x0800 TOHP_MODE _VERR TOHP_RX_MODE[2:0] TOHP_TX_MODE[2:0] Channel Interrupts--RO 0x0801 TOHP_CH_ INT TOHP_ CORWN TOHP_ INTH[D] TOHP_ INTH[C] TOHP_ INTH[B] TOHP_ INTH[A] TOHP_ INTL[D] TOHP_ INTL[C] TOHP_ INTL[B] TOHP_ INTL[A] TOHP_VER[9:0] TOHP-48 Delta and Event Parameters--COR/COW--RO 0x0802 TOHP_DLT_ EVTA1 TOHP_DLT_ EVTA2 TOHP_DLT_ EVTB1 TOHP_DLT_ EVTB2 TOHP_DLT_ EVTC1 TOHP_DLT_ EVTC2 TOHP_DLT_ EVTD1 TOHP_DLT_ EVTD2 TOHP-48 Receive/Transmit State and Value Parameters--RO 0x080A 0x080B 0x080C 0x080D TOHP_RX_ TX_STATEA TOHP_RX_ TX_STATEB TOHP_RX_ TX_STATEC TOHP_RX_ TX_STATED TOHP_LRD TOHP_LAIS IMON[A] MON[A] TOHP_LRD TOHP_LAIS IMON[B] MON[B] TOHP_LRD TOHP_LAIS IMON[C] MON[C] TOHP_LRD TOHP_LAIS IMON[D] MON[D] TOHP_TLR DIINT[A] TOHP_TLR DIINT[B] TOHP_TLR DIINT[C] TOHP_TLR DIINT[D] TOHP_ SF[A] TOHP_ SF[B] TOHP_ SF[C] TOHP_ SF[D] TOHP_ SD[A] TOHP_ SD[B] TOHP_ SD[C] TOHP_ SD[D] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[ [A] [A] [A] A] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[ [B] [B] [B] B] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[ [C] [C] [C] C] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[ [D] [D] [D] D] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D IMOND[D] MOND[D] SBABLEE MON4D[D] MON8D[D] MOND[D] 2DMOND MOND[D] [D] [D] TOHP_S1B TOHP_SFD TOHP_SDD ABLEE[D] [D] [D] TOHP_ OOFD[D] TOHP_ LOFD[D] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D IMOND[C] MOND[C] SBABLEE MON4D[C] MON8D[C] MOND[C] 2DMOND MOND[C] [C] [C] TOHP_S1B TOHP_SFD TOHP_SDD ABLEE[C] [C] [C] TOHP_ OOFD[C] TOHP_ LOFD[C] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D IMOND[B] MOND[B] SBABLEE MON4D[B] MON8D[B] MOND[B] 2DMOND MOND[B] [B] [B] TOHP_S1B TOHP_SFD TOHP_SDD ABLEE[B] [B] [B] TOHP_ OOFD[B] TOHP_ LOFD[B] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D TOHP_TTO TOHP_S1B IMOND[A] MOND[A] SBABLEE MON4D[A] MON8D[A] MOND[A] 2DMOND MOND[A] AC_PERRE ABLEE[A] [A] [A] [A] TOHP_ SFD[A] TOHP_ SDD[A] TOHP_ OOFD[A] TOHP_ LOFD[A] TOHP_ LOSD[A] TOHP_ LOCD[A] 0x0803 TOHP_ TOHP_J0MI TTOAC_K1 SE[A] K2ERRE[A] TOHP_ LOSD[B] TOHP_ LOCD[B] 0x0804 0x0805 TOHP_ TOHP_J0MI TTOAC_K1 SE[B] K2ERRE[B] TOHP_ LOSD[C] TOHP_ LOCD[C] 0x0806 0x0807 TOHP_ TOHP_J0MI TTOAC_K1 SE[C] K2ERRE[C] TOHP_ LOSD[D] TOHP_ TTOAC_K1 K2ERRE[D] TOHP_ LOCD[D] TOHP_ J0MISE[D] 0x0808 0x0809 Agere Systems Inc. 237 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Mask Parameters--R/W 0x080E TOHP_ MSKA1 TOHP_ MSKA2 TOHP_ MSKB1 TOHP_ MSKB2 TOHP_ MSKC1 TOHP_ MSKC2 TOHP_ MSKD1 TOHP_ MSKD2 TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D TOHP_TTO TOHP_S1B TOHP_SFM IMONM[A] MONM[A] SBABLEM MON4M[A] MON8M[A] MONM 2DMONM MONM[A] ABLEM[A] [A] AC_PERR [A] [A] [A] M[A] TOHP_INT M[A] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D IMONM[B] MONM[B] SBABLEM MON4M[B] MON8M[B] MONM[B] 2DMONM MONM[B] [B] [B] TOHP_INT M[B] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D IMONM[C] MONM[C] SBABLEM MON4M[C] MON8M[C] MONM[C] 2DMONM MONM[C] [C] [C] TOHP_INT M[C] TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D IMONM[D] MONM[D] SBABLEM MON4M[D] MON8M[D] MONM[D] 2DMONM MONM[D] [D] [D] TOHP_INT M[D] Triggers--R/W 0x0816 TOHP_TRGA TOHP_RSTN_SW[A][15:12] TOHP_TA1 TOHP_SFC LEAR[A] A2ERREN [A] TOHP_TA1 TOHP_SFC LEAR[B] A2ERREN [B] TOHP_TA1 TOHP_SFC LEAR[C] A2ERREN [C] TOHP_TA1 TOHP_SFC LEAR[D] A2ERREN [D] TOHP_ SFSET[A] TOHP_ SFSET[B] TOHP_ SFSET[C] TOHP_ SFSET[D] TOHP_SDC LEAR[A] TOHP_SDC LEAR[B] TOHP_SDC LEAR[C] TOHP_SDC LEAR[D] TOHP_ SDSET[A] TOHP_ SDSET[B] TOHP_ SDSET[C] TOHP_ SDSET[D] TOHP_S1B TOHP_SFM ABLEM[D] [D] TOHP_SD M[D] TOHP_S1B TOHP_SFM ABLEM[C] [C] TOHP_SD M[C] TOHP_S1B TOHP_SFM ABLEM[B] [B] TOHP_SD M[B] TOHP_SD M[A] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC M[A] M[A] M[A] M[A] TOHP_ TOHP_J0MI TTOAC_K1 SM[A] K2ERRM[A] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC M[B] M[B] M[B] M[B] TOHP_ TTOAC_K1 K2ERRM[B] J0MISM[B] 0x080F 0x0810 0x0811 0x0812 TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC M[C] M[C] M[C] M[C] TOHP_ TOHP_J0MI TTOAC_K1 SM[C] K2ERRM[C] TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC M[D] M[D] M[D] M[D] TOHP_ TOHP_J0MI TTOAC_K1 SM[D] K2ERRM[D] 0x0813 0x0814 0x0815 0x0817 TOHP_TRGB TOHP_RSTN_SW[B][15:12] 0x0818 TOHP_TRGC TOHP_RSTN_SW[C][[15:12] 0x0819 TOHP_TRGD TOHP_RSTN_SW[D][15:12] 238 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x081A 0x081B Symbol TOHP_ CNTDA1 TOHP_ CNTDA2 TOHP_ CNTDB1 TOHP_ CNTDB2 TOHP_ CNTDC1 TOHP_ CNTDC2 TOHP_ CNTDD1 TOHP_ CNTDD2 TOHP_CNTDK2[D][3:0] -- (Version 2.2 and 2.3) Reserved (Version 2.0) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Continuous N-Times Detect Values--R/W TOHP_CNTDK2[A][3:0] -- (Version 2.2 and 2.3) Reserved (Version 2.0) TOHP_CNTDK1K2[A][3:0] TOHP_CNTDS1BABLE[A][3:0] TOHP_CNTDF1[A][3:0] TOHP_CNTDS1[A][3:0] TOHP_CNTDJ0Z0[A][3:0] TOHP_CNTDK1K2FRAME[A][3:0] 0x081C 0x081D TOHP_CNTDK2[B][3:0] -- (Version 2.2 and 2.3) Reserved (Version 2.0) TOHP_CNTDK1K2[B][3:0] TOHP_CNTDS1BABLE[B][3:0] TOHP_CNTDF1[B][3:0] TOHP_CNTDS1[B]3:0] TOHP_CNTDJ0Z0[B][3:0] TOHP_CNTDK1K2FRAME[B][3:0] 0x081E 0x081F TOHP_CNTDK2[C][3:0] -- (Version 2.2 and 2.3) Reserved (Version 2.0) TOHP_CNTDK1K2[C][3:0] TOHP_CNTDS1BABLE[C][3:0] TOHP_CNTDF1[C][3:0] TOHP_CNTDS1[C]3:0] TOHP_CNTDJ0Z0[C][3:0] TOHP_CNTDK1K2FRAME[C][3:0] 0x0820 0x0821 TOHP_CNTDK1K2[D][3:0] TOHP_CNTDS1BABLE[D][3:0] TOHP_CNTDF1[D][3:0] TOHP_CNTDS1[D]3:0] TOHP_CNTDJ0Z0[D][3:0] TOHP_CNTDK1K2FRAME[D][3:0] Receive Control Parameters--R/W 0x0822 TOHP_ RCTLA1 TOHP_ RCTLA2 TOHP_ RCTLB1 TOHP_ RCTLB2 TOHP_ RCTLC1 TOHP_ RCTLC2 TOHP_ RCTLD1 TOHP_ RCTLD2 TOHP_ RCTLA3 TOHP_ RCTLB3 TOHP_J0MONMODE [A][1:0] TOHP_M1B ITBLKCNT [A] TOHP_J0MONMODE [B][1:0] TOHP_M1B ITBLKCNT [B] TOHP_J0MONMODE [C][1:0] TOHP_M1B ITBLKCNT [C] TOHP_J0MONMODE [D][1:0] TOHP_M1B ITBLKCNT [D] TOHP_RREFSEL[1:0] TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH INS[A] _AISINH[A] _AISINH[A] _AISINH[A] 1B2SEL[A] 1B2SEL[A] DB1SEL[A] ON8OR4CT 2_2OR1[A] TBLKCNT RINH[A] TBLKCNT _BYPASS 7IGNORE L[A] [A] [A] [A] [A] TOHP_RVA LIDK_CTL [A] TOHP_LOSDETCNT[A][12:0] 0x0823 0x0824 TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH INS[B] _AISINH[B] _AISINH[B] _AISINH[B] 1B2SEL[B] 1B2SEL[B] DB1SEL[B] ON8OR4CT 2_2OR1[B] TBLKCNT RINH[B] TBLKCNT _BYPASS 7IGNOR[B] L[B] [B] [B] [B] TOHP_RVA LIDK_CTL [B] TOHP_LOSDETCNT[B][12:0] 0x0825 0x0826 TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH INS[C] _AISINH[C] _AISINH[C] _AISINH[C] 1B2SEL[C] 1B2SEL[C] DB1SEL[C] ON8OR4CT 2_2OR1[C] TBLKCNT RINH[C] TBLKCNT _BYPASS 7IGNORE L[C] [C] [C] [C] [C] TOHP_RVA LIDK_CTL [C] TOHP_LOSDETCNT[C][12:0] 0x0827 0x0828 TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH INS[D] _AISINH[D] _AISINH[D] _AISINH[D] 1B2SEL[D] 1B2SEL[D] DB1SEL[D] ON8OR4CT 2_2OR1[D] TBLKCNT RINH[D] TBLKCNT _BYPASS 7IGNORE L[D] [D] [D] [D] [D] TOHP_RVA LIDK_CTL [D] TOHP_ RREF_EN TOHP_ RREF_INH TOHP_LOSDETCNT[D][12:0] 0x0829 0x082A TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO ACSINH[A] ACCINH[A] ACDINH[A] AC_OEPIN S[A] TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO ACSINH[B] ACCINH[B] ACDINH[B] AC_OEPIN S[B] 0x082B Agere Systems Inc. 239 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x082C Symbol TOHP_ RCTLC3 TOHP_ RCTLD3 Transmit Control Parameters--R/W 0x082E TOHP_ TCTLA1 TOHP_ TCTLA2 TOHP_ TCTLB1 TOHP_ TCTLB2 TOHP_ TCTLC1 TOHP_ TCTLC2 TOHP_ TCTLD1 TOHP_ TCTLD2 TOHP_ TCTLA3 TOHP_ TCTLB3 TOHP_ TCTLC3 TOHP_ TCTLD3 TOHP_ TAPSINS[A] TOHP_ TAPSINS[B] TOHP_ TAPSINS [C] TOHP_ TAPSINS [D] TOHP_ TTOAC_ K1K2[A] TOHP_TTO TOHP_TJ0I TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1 ACINH NS[A] AC_J0[A] AC_OEPM AC_INS[A] AC_E2[A] AC_S1[A] AC_D4TO1 AC_D1TO3 AC_F1[A] AC_E1[A] SBABLEIN _ERR_INS _REIL_INH ON[A] 2[A] [A] S[A] [A] [A] TOHP_TA1A2ERRINS[A][4:0] TOHP_TOH TOHP_SCR TOHP_TB1 _BYPASS INH[A] ERRINS[A] [A] TOHP_ TF1INS[A] TOHP_ TS1INS[A] TOHP_TLO C_LRDIINH [A] TOHP_ TS1INS[B] TOHP_TLO C_LRDIINH [B] TOHP_ TS1INS[C] TOHP_TLO C_LRDIINH [C] TOHP_ TS1INS[D] TOHP_TLO C_LRDIINH [D] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO ACSINH[C] ACCINH[C] ACDINH[C] AC_OEPIN S[C] TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO ACSINH[D] ACCINH[D] ACDINH[D] AC_OEPIN S[D] 0x082D 0x082F TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO ERRINS[A] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH H[A] [A] DIINH[A] [A] [A] [A] TOHP_ TF1INS[B] 0x0830 TOHP_TJ0I TOHP_TTO NS[B] AC_J0[B] TOHP_ TTOAC_ K1K2[B] TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1 AC_INS[B] AC_E2[B] AC_S1[B] AC_D4TO1 AC_D1TO3 AC_F1[B] AC_E1[B] SBABLEIN _ERR_INS _REIL_INH 2[B] [B] S[B] [B] [B] TOHP_TOH TOHP_SCR TOHP_TB1 _BYPASS[B INH[B] ERRINS[B] ] 0x0831 TOHP_TA1A2ERRINS[B][4:0] TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO ERRINS[B] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH H[B] [B] DIINH[B] [B] [B] [B] TOHP_ TF1INS[C] 0x0832 TOHP_ TOHP_TJ0I TOHP_TTO TTOAC_VA NS[C] AC_J0[C] LIDK_CTL TOHP_ TTOAC_ K1K2[C] TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1 AC_INS[C] AC_E2[C] AC_S1[C] AC_D4TO1 AC_D1TO3 AC_F1[C] AC_E1[C] SBABLEIN _ERR_INS _REIL_INH 2[C] [C] S[C] [C] [C] TOHP_TOH TOHP_SCR TOHP_TB1 _BYPASS INH[C] ERRINS[C] [C] 0x0833 TOHP_TA1A2ERRINS[C][4:0] TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO ERRINS[C] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH H[C] [C] DIINH[C] [C] [C] [C] TOHP_ TF1INS[D] 0x0834 TOHP_ TOHP_TJ0I TOHP_TTO TK2SWHWI NS[D] AC_J0[D] NS_INH TOHP_ TTOAC_ K1K2[D] TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1 AC_INS[D] AC_E2[D] AC_S1[D] AC_D4TO1 AC_D1TO3 AC_F1[D] AC_E1[D] SBABLEIN _ERR_INS _REIL_INH 2[D] [D] S[D] [D] [D] TOHP_TOH TOHP_SCR TOHP_TB1 _BYPASS INH[D] ERRINS[D] [D] 0x0835 TOHP_TA1A2ERRINS[D][4:0] TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO ERRINS[D] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH H[D] [D] DIINH[D] [D] [D] [D] TOHP_TAISLINS[A][11:0] 0x0836 TOHP_TK2SINS[A][1:0] TOHP_TVA LIDK_ CTL[A] TOHP_TVA LIDK_ CTL[B] TOHP_TVA LIDK_ CTL[C] TOHP_TVA LIDK_ CTL[D] 0x0837 TOHP_TK2SINS[B][1:0] TOHP_TAISLINS[B][11:0] 0x0838 TOHP_TK2SINS[C][1:0] TOHP_TAISLINS[C][11:0] 0x0839 TOHP_TK2SINS[D][1:0] TOHP_TAISLINS[D][11:0] 240 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Signal Degrade Set/Clear Control Registers--R/W 0x083A 0x083B 0x083C 0x083D 0x083E 0x083F 0x0840 0x0841 0x0842 0x0843 0x0844 0x0845 0x0846 0x0847 0x0848 0x0849 0x084A 0x084B 0x084C 0x084D TOHP_SD_ SETRA1 TOHP_SD_ SETRA2 TOHP_SD_ SETRB1 TOHP_SD_ SETRB2 TOHP_SD_ SETRC1 TOHP_SD_ SETRC2 TOHP_SD_ SETRD1 TOHP_SD_ SETRD2 TOHP_SD_ SETRA3 TOHP_SD_ SETRB3 TOHP_SD_ SETRC3 TOHP_SD_ SETRD3 TOHP_SD_ CLEARRA1 TOHP_SD_ CLEARRA2 TOHP_SD_ CLEARRB1 TOHP_SD_ CLEARRB2 TOHP_SD_ CLEARRC1 TOHP_SD_ CLEARRC2 TOHP_SD_ CLEARRD1 TOHP_SD_ CLEARRD2 TOHP_SDMCLEAR[D][6:0] TOHP_SDMCLEAR[C][6:0] TOHP_SDNSCLEAR[D][17:2] TOHP_SDLCLEAR[D][6:0] TOHP_SDNSCLEAR [D][1:0] TOHP_SDMCLEAR[B][6:0] TOHP_SDNSCLEAR[C][17:2] TOHP_SDLCLEAR[C][6:0] TOHP_SDNSCLEAR [C][1:0] TOHP_SDMCLEAR[A][6:0] TOHP_SDNSCLEAR[B][17:2] TOHP_SDLCLEAR[B][6:0] TOHP_SDNSCLEAR [B][1:0] TOHP_SDMSET[D][6:0] TOHP_SDBSET[A][15:0] TOHP_SDBSET[B][15:0] TOHP_SDBSET[C][15:0] TOHP_SDBSET[D][15:0] TOHP_SDNSCLEAR[A][17:2] TOHP_SDLCLEAR[A][6:0] TOHP_SDNSCLEAR [A][1:0] TOHP_SDMSET[C][6:0] TOHP_SDNSSET[D][17:2] TOHP_SDLSET[D][6:0] TOHP_SDNSSET[D][1:0] TOHP_SDMSET[B][6:0] TOHP_SDNSSET[C][17:2] TOHP_SDLSET[C][6:0] TOHP_SDNSSET[C][1:0] TOHP_SDMSET[A][6:0] TOHP_SDNSSET[B][17:2] TOHP_SDLSET[B][6:0] TOHP_SDNSSET[B][1:0] TOHP_SDNSSET[A][17:2] TOHP_SDLSET[A][6:0] TOHP_SDNSSET[A][1:0] Agere Systems Inc. 241 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x084E 0x084F 0x0850 0x0851 Symbol TOHP_SD_ CLEARRA3 TOHP_SD_ CLEARRB3 TOHP_SD_ CLEARRC3 TOHP_SD_ CLEARRD3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOHP_SDBCLEAR[A][15:0] TOHP_SDBCLEAR[B][15:0] TOHP_SDBCLEAR[C][15:0] TOHP_SDBCLEAR[D][15:0] Signal Fail Set/Clear Control Registers--R/W 0x0852 0x0853 0x0854 0x0855 0x0856 0x0857 0x0858 0x0859 0x085A 0x085B 0x085C 0x085D 0x085E 0x085F 0x0860 0x0861 0x0862 0x0863 TOHP_SF_ SETRA1 TOHP_SF_ SETRA2 TOHP_SF_ SETRB1 TOHP_SF_ SETRB2 TOHP_SF_ SETRC1 TOHP_SF_ SETRC2 TOHP_SF_ SETRD1 TOHP_SF_ SETRD2 TOHP_SF_ SETRA3 TOHP_SF_ SETRB3 TOHP_SF_ SETRC3 TOHP_SF_ SETRD3 TOHP_SF_ CLEARRA1 TOHP_SF_ CLEARRA2 TOHP_SF_ CLEARRB1 TOHP_SF_ CLEARRB2 TOHP_SF_ CLEARRC1 TOHP_SF_ CLEARRC2 TOHP_SFMCLEAR[C][6:0] TOHP_SFMCLEAR[B][6:0] TOHP_SFNSCLEAR[C][17:2] TOHP_SFLCLEAR[C][6:0] OHP_SFNSCLEAR [C][1:0] TOHP_SFMCLEAR[A][6:0] TOHP_SFNSCLEAR[B][17:2] TOHP_SFLCLEAR[B][6:0] OHP_SFNSCLEAR [B][1:0] TOHP_SFMSET[D][5:0] Applies for version 2.2 and 2.3 only. TOHP_SFMSET[D][6:0] Applies for version 2.0 only. TOHP_SFMSET[C][5:0] Applies for version 2.2 and 2.3 only. TOHP_SFMSET[C][6:0] Applies for version 2.0 only. TOHP_SFMSET[B][5:0] Applies for version 2.2 and 2.3 only. TOHP_SFMSET[B][6:0] Applies for version 2.0 only. TOHP_SFMSET[A][5:0] Applies for version 2.2 and 2.3 only. TOHP_SFMSET[A][6:0] Applies for version 2.0 only. TOHP_SFNSSET[A][17:2] TOHP_SFLSET[A][7:0] Applies for version 2.2 and 2.3 only. TOHP_SFLSET[A][6:0] Applies for version 2.0 only. TOHP_SFNSSET[B][17:2] TOHP_SFLSET[B][7:0] Applies for version 2.2 and 2.3 only. TOHP_SFLSET[B][6:0] Applies for version 2.0 only. TOHP_SFNSSET[C][17:2] TOHP_SFLSET[C][7:0] Applies for version 2.2 and 2.3 only. TOHP_SFLSET[C][6:0] Applies for version 2.0 only. TOHP_SFNSSET[D][17:2] TOHP_SFLSET[D][7:0] Applies for version 2.2 and 2.3 only. TOHP_SFLSET[D][6:0] Applies for version 2.0 only. TOHP_SFBSET[A][15:0] TOHP_SFBSET[B][15:0] TOHP_SFBSET[C][15:0] TOHP_SFBSET[D][15:0] TOHP_SFNSCLEAR[A][17:2] TOHP_SFLCLEAR[A][6:0] TOHP_SFNSCLEAR [A][1:0] TOHP_SFNSSET[D][1:0] TOHP_SFNSSET[C][1:0] TOHP_SFNSSET[B][1:0] TOHP_SFNSSET[A][1:0] 242 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x0864 0x0865 0x0866 0x0867 0x0868 0x0869 Symbol TOHP_SF_ CLEARRD1 TOHP_SF_ CLEARRD2 TOHP_SF_ CLEARRA3 TOHP_SF_ CLEARRB3 TOHP_SF_ CLEARRC3 TOHP_SF_ CLEARRD3 TOHP_SFMCLEAR[D][6:0] TOHP_SFBCLEAR[A][15:0] TOHP_SFBCLEAR[B][15:0] TOHP_SFBCLEAR[C][15:0] TOHP_SFBCLEAR[D][15:0] B1, B2, and M1 Error Counts--RO 0x086A 0x086B 0x086C 0x086D 0x086E 0x086F 0x0870 0x0871 0x0872 0x0873 0x0874 0x0875 0x0876 0x0877 TOHP_ B1ECNTRA TOHP_ B1ECNTRB TOHP_ B1ECNTRC TOHP_ B1ECNTRD TOHP_ B2ECNTRA1 TOHP_ B2ECNTRA2 TOHP_ B2ECNTRB1 TOHP_ B2ECNTRB2 TOHP_ B2ECNTRC1 TOHP_ B2ECNTRC2 TOHP_ B2ECNTRD1 TOHP_ B2ECNTRD2 TOHP_ M1ECNTRA1 TOHP_ M1ECNTRA2 TOHP_M1ECNT[A][15:0] TOHP_B2ECNT[D][15:0] TOHP_M1ECNT[A][20:16] TOHP_B2ECNT[C][15:0] TOHP_B2ECNT[D][21:16] TOHP_B2ECNT[B][15:0] TOHP_B2ECNT[C][21:16] TOHP_B2ECNT[A][15:0] TOHP_B2ECNT[B][21:16] TOHP_B1ECNT[A][15:0] TOHP_B1ECNT[B][15:0] TOHP_B1ECNT[C][15:0] TOHP_B1ECNT[D][15:0] TOHP_B2ECNT[A][21:16] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOHP_SFNSCLEAR[D][17:2] TOHP_SFLCLEAR[D][6:0] OHP_SFNSCLEAR [D][1:0] Agere Systems Inc. 243 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x0878 0x0879 0x087A 0x087B 0x087C 0x087D Symbol TOHP_ M1ECNTRB1 TOHP_ M1ECNTRB2 TOHP_ M1ECNTRC1 TOHP_ M1ECNTRC2 TOHP_ M1ECNTRD1 TOHP_ M1ECNTRD2 TOHP_M1ECNT[D][15:0] Transmit OH Insert Value--R/W 0x087E 0x087F 0x0880 0x0881 0x0882 0x0883 0x0884 0x0885 TOHP_TOH_ INSRA1 TOHP_TOH_ INSRA2 TOHP_TOH_ INSRB1 TOHP_TOH_ INSRB2 TOHP_TOH_ INSRC1 TOHP_TOH_ INSRC2 TOHP_TOH_ INSRD1 TOHP_TOH_ INSRD2 TOHP_TF1DINS[A][7:0] TOHP_TK2DINS[A][7:0] TOHP_TF1DINS[B][7:0] TOHP_TK2DINS[B][7:0] TOHP_TF1DINS[C][7:0] TOHP_TK2DINS[C][7:0] TOHP_TF1DINS[D][7:0] TOHP_TK2DINS[D][7:0] Receive Monitor Values--RO 0x0886 0x0887 0x0888 0x0889 0x088A 0x088B 0x088C TOHP_ RMONRA1 TOHP_ RMONRA2 TOHP_ RMONRA3 TOHP_ RMONRB1 TOHP_ RMONRB2 TOHP_ RMONRB3 TOHP_ RMONRC1 TOHP_F1DMON1[C][7:0] TOHP_F1DMON1[B][7:0] TOHP_K2DMON[B][7:0] TOHP_F1DMON1[A][7:0] TOHP_K2DMON[A][7:0] TOHP_F1DMON0[A][7:0] TOHP_K1DMON[A][7:0] TOHP_S1DMON[A][7:0] TOHP_F1DMON0[B][7:0] TOHP_K1DMON[B][7:0] TOHP_S1DMON[B][7:0] TOHP_F1DMON0[C][7:0] TOHP_TS1DINS[A][7:0] TOHP_TK1DINS[A][7:0] TOHP_TS1DINS[B][7:0] TOHP_TK1DINS[B][7:0] TOHP_TS1DINS[C][7:0] TOHP_TK1DINS[C][7:0] TOHP_TS1DINS[D][7:0] TOHP_TK1DINS[D][7:0] TOHP_M1ECNT[C][15:0] TOHP_M1ECNT[D][20:16] TOHP_M1ECNT[B][15:0] TOHP_M1ECNT[C][20:16] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOHP_M1ECNT[B][20:16] 244 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x088D 0x088E 0x088F 0x0890 0x0891 Symbol TOHP_ RMONRC2 TOHP_ RMONRC3 TOHP_ RMONRD1 TOHP_ RMONRD2 TOHP_ RMONRD3 J0 Byte Receive Monitor (64 bytes)--RO 0x0892-- 0x08B1 0x08B2-- 0x08D1 0x08D2-- 0x08F1 0x08F2-- 0x0911 TOHP_RJ0DM ONR[A][1--32] TOHP_RJ0DM ONR[B][1--32] TOHP_RJ0DM ONR[C][1--32] TOHP_RJ0DM ONR[D][1--32] TOHP_RJ0DMON[A][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON[B][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON[C][2, 4, 6, . . ., 64][7:0] TOHP_RJ0DMON[D][2, 4, 6, . . ., 64][7:0] J0 Byte Transmit Insert (64 bytes)--R/W 0x0912-- 0x0931 0x0932-- 0x0951 0x0952-- 0x0971 0x0972-- 0x09A9 TOHP_TJ0DIN SR[A][1--32] TOHP_TJ0DIN SR[B][1--32] TOHP_TJ0DIN SR[C][1--32] TOHP_TJ0DIN SR[D][1--32] TOHP_TJ0DINS[A][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS[B][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS[C][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS[D][2, 4, 6, . . ., 64][7:0] TOHP_TJ0DINS[A][1, 3, 5, . . ., 63][7:0] TOHP_TJ0DINS[B][1, 3, 5, . . ., 63][7:0] TOHP_TJ0DINS[C][1, 3, 5, . . ., 63][7:0] TOHP_TJ0DINS[D][1, 3, 5, . . ., 63][7:0] TOHP_RJ0DMON[A][1, 3, 5, . . ., 63][7:0] TOHP_RJ0DMON[B][1, 3, 5, . . ., 63][7:0] TOHP_RJ0DMON[C][1, 3, 5, . . ., 63][7:0] TOHP_RJ0DMON[D][1, 3, 5, . . ., 63][7:0] TOHP_F1DMON1[D][7:0] TOHP_K2DMON[D][7:0] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOHP_K2DMON[C][7:0] TOHP_K1DMON[C][7:0] TOHP_S1DMON[C][7:0] TOHP_F1DMON0[D][7:0] TOHP_K1DMON[D][7:0] TOHP_S1DMON[D][7:0] Agere Systems Inc. 245 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Transport Overhead Processor (TOHP-48) Block (continued) TOHP-48 Register Map (continued) Table 93. TOHP-48 Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z0 Byte Transmit Insert--R/W 0x09AA 0x09AB-- 0x09AF 0x09B0 0x09B1-- 0x09B5 0x09B6 0x09B7-- 0x09BB 0x09BC 0x09BD-- 0x09C1 TOHP_TZ0DIN SR[A][1] TOHP_TZ0DIN SR[A][2--6] TOHP_TZ0DIN SR[B][1] TOHP_TZ0DIN SR[B][2--6] TOHP_TZ0DIN SR[C][1] TOHP_TZ0DIN SR[C][2--6] TOHP_TZ0DIN SR[D][1] TOHP_TZ0DIN SR[D][2--6] TOHP_TZ0DINS[A][2][7:0] TOHP_TZ0DINS[A][4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[B][2][7:0] TOHP_TZ0DINS[B][4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[C][2][7:0] TOHP_TZ0DINS[C][4, 6, 8, 10, 12][7:0] TOHP_TZ0DINS[D][2][7:0] TOHP_TZ0DINS[D][4, 6, 8, 10, 12][7:0] Scratch Register--R/W 0x09C2 0x09C3-- 0x09FF TOHP_ SCRATCHR TOHP_SCRATCH[15:0] TOHP_TZ0DINS[D][3, 5, 7, 9, 11][7:0] TOHP_TZ0DINS[C][3, 5, 7, 9, 11][7:0] TOHP_TZ0DINS[B][3, 5, 7, 9, 11][7:0] TOHP_TZ0DINS[A][3, 5, 7, 9, 11][7:0] 246 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) Introduction The pointer processor block handles one STS-48 stream (single-channel mode) or four STS-12 or STS-3 streams (quad-channel mode). The pointer processor performs pointer interpretation, path overhead (POH) monitoring, and generates a new STS frame aligned to the system frame pulse. The pointer interpreter block interprets the incoming H1/H2 pointer of each incoming STS channel. The pointer interpreter supports up to 48 channels and performs path overhead monitoring on each channel. Each channel may be either an STS-1, STS-3c, STS-6c, STS-9c, . . . , STS-45c, STS48c. An STS-3nc channel must start at time slots 1, 4, 7, 10, . . . , or 46 (assuming that it can fit). For example, an STS-36c must start in time slots 1, 4, 7, 10, or 13; an STS-45c must start at time slot 1 or 4. The pointer is validated according to Telcordia and ITU specifications. The H1/H2 pointer is used to determine the location of the first path overhead (POH) byte (J1). The pointer interpreter consists of a finite state machine (FSM) with four steady states. These states are defined as: Normal state Loss of pointer (LOP) Alarm indication signal (AIS) Concatenation The transition between states will require several consecutive events to protect against transient conditions caused by bit errors during high BER conditions. This pointer processor block monitors for the following conditions and takes appropriate actions: Pointer increment Pointer decrement Loss of pointer AIS-P New pointer Invalid pointer Receive Path Trace The path trace message is extracted and stored in a 64-byte memory that can be accessed through the microprocessor interface. The first byte of the message can be provisioned to be either: the byte with the most significant bit (MSB) set high, or the byte following a carriage return (0x0D) and line feed (0x0A) sequence. This frame synchronization can be disabled. Agere Systems Inc. 247 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) Introduction (continued) Receive Error Monitor The PBIP block counts path BIP-8 errors. A theoretical maximum of 64,000 (x concatenation level) errors may be detected per second. A practical average of 32,000 errors per second will be detected under the worst error conditions. The PBIP block accumulates these errors in a 16-bit saturating counter. This counter is operated in latch and clear mode to ensure Telcordia and ITU compliance with regard to not missing any events (bit errors). It is intended that this counter be polled at least once per second to ensure that no error events are missed. The REI_P block counts remote error indication (formally known as FEBE) block errors. Receive Signal Label The C2 block will extract and validate the signal label byte (C2) and store it in registers PP_TSC2R[1--24], Time Slots 1--48 Path C2 Status (RO), Table 247, addresses 0x1930--0x1947. Receive Path Status The G1 block extracts the path remote error indication (REI-P) bits of G1 and accumulates the REI-P errors in a 16bit saturating counter. This counter is operated in latch and clear mode to ensure Telcordia and ITU compliance. It is intended that this counter be polled at least once per second to ensure that no error events are missed. This block will also validate the path remote defect indication (RDI-P) bits and store the result in registers PP_TSRDIPR[1--48], Time Slots 1--48 Path RDI Status (RO), Table 246, addresses 0x1900--0x192F. Elastic Store For each STS channel, the SPE is placed into an elastic store buffer. The system (transmit) clock and 8 kHz frame is used to generate a new STS frame with the SPE extracted from the elastic store. The level of the elastic store is monitored and positive/negative stuffs are performed on the new STS frame in order to prevent elastic store overflows/underflows. 248 Agere Systems Inc. Data Sheet August 19, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) Introduction (continued) Z5/N1, Z4/K4, Z3/F3, H4, and F2 Monitoring Also monitored are the F2 user channel byte, the H4 VT multiframe indicator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte. These bytes are stored in software registers. These registers are updated when a provisionable number of detections of new values occurs on the associated incoming byte. Note that there are four circuits--1 per STS-12 channel, each monitoring the Z5/N1, Z4/K4, Z3/F3, H4, and F2 bytes of their selected STS-1 stream. SS Bits Monitoring Although the SS bits are not defined at the STS-N level in GR-253, SDH-based equipment supports the SS bits monitoring feature. Therefore, for SDH conformance the SS bits, contained in the H1 byte, are stored in software registers. These registers are updated when a provisionable number of mismatches occurs in the provisioned mode. The same registers are updated when a provisionable number of detections of new values of the SS bits occurs while in the validation mode. In both the provisioned and validation mode, the processor is interrupted when a mismatch or a validation takes place. In SDH, only 16 channels need to be monitored (1 per STS-3 stream) and the register space is extended to cover 48 STS-1s. SS bits monitoring is enabled only when the J1 message type is set to SDH (register 0x1339, Table 181). E1 and F1 Path Status Bytes Each STS-1 time slot will contain an independent E1/F1 value. For each STS-1 time slot, the E1 and F1 bytes will be identical (E1 = F1) and will contain a code indicating the status of that time slot. The following values are defined for E1/F1. This is a priority encoder, only one status condition can be communicated at once, the higher conditions in the following table having higher priority. Note that the PDI code received (if one is received) will not be considered unless the PDI validate enable is set. Table 94. E1/F1 Path Status Definition E1/F1 Value 0011 1111 1111 1111 0011 1110 0001 1100 0011 1101 0011 1100 to 0010 0001 Definition Loss of Pointer (LOP-P) repass AIS. Concatenation Mismatch or Software Insertion of AIS. Unequipped Signal Label (UNEQ-P). Trace Identifier (J1) Mismatch (TIM-P). Signal Fail (SF). PDI code 28 to PDI code 1 (This E1/F1 value will only occur if the corresponding bit in the PDI VALIDATE ENABLE register is high). 0001 1111 0001 1110 0000 0000 Signal Degrade (SD). Payload Label Mismatch (PLM-P). No Alarms. This value can be overwritten by software by setting the E1/F1_INSERT_CONTROL register for those individual Sets one wishes to override and placing the desired byte in the corresponding E1/F1 INSERT register. Agere Systems Inc. 249 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) Detailed Description The pointer processor is used to transfer input stream(s) to the system timing of the device. It can accept one STS48 or 4 STS-12 or STS-3 streams. In single-channel mode, the input stream is converted to four STS-12 signals, all on system timing. In quad-channel mode, the same output is produced from four asynchronous input streams of either STS-12 or STS-3 capacities. The four outgoing streams are synchronized to the system clock and system frame sync. A block diagram is shown in Figure 36 on page 251. The main blocks of this block are the time-slot interchange (TSI), four STS-12 pointer processor modules, and the microprocessor interface. The TSI is required because the pointer processor operates at an STS-12 granularity. The TSI is only used in the STS-48 mode. In OC-3 mode, the pointer processor still operates at an STS-12 rate and data bytes are replicated four times to achieve this as shown in Figure 35. STS-3 #1 STS-1 #2 STS-1 #3 STS-1 #1 STS-1 STS-12 1111222233331111 #1 STS-1s #2 STS-1s #3 STS-1s 5-8151(F)r.2 Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor The pointer processor block requires a frame pulse for each input stream. In the MARS2G5 P-Pro device, these four signals are provided from the transport overhead processor block. The pointer processor block performs intermediate performance monitoring of the input stream(s), and can interrupt the host microprocessor with alarms and make available the collected results through a register set. The pointer processor is SONET and SDH compliant. 250 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) Detailed Description (continued) ADDRESS_BUS[7:0] RX_LTE_STS_DATA[31:0] FRAME_PULSE_PP_1 RX_CLK_1 RX_RST_N1 TSI (TIME-SLOT INTERCHANGE) MICROPROCESSOR INTERFACE BUS CONTROL SIGNALS WRITE_DATA_BUS[15:0] READ_DATA_BUS[15:0] INTERRUPTS PP_STS_DATA_1[7:0] RX_LTE_STS_DATA[31:24] FRAME_PULSE_RX_LTE1 RX_CLK_1 RX_RST_N1 POINTER INTERPRETER ELASTIC STORE POINTER GENERATOR FRAME_PULSE_PP_1 RX_CLK_1 TIMING SYSTEM TIMING PP_STS_DATA_2[7:0] RX_LTE_STS_DATA[23:16] FRAME_PULSE_RX_LTE2 RX_CLK_2 RX_RST_N2 POINTER INTERPRETER ELASTIC STORE POINTER GENERATOR FRAME_PULSE_PP_2 RX_CLK_2 TIMING SYSTEM TIMING PP_STS_DATA_3[7:0] RX_LTE_STS_DATA[15:8] FRAME_PULSE_RX_LTE3 RX_CLK_3 RX_RST_N3 POINTER INTERPRETER ELASTIC STORE POINTER GENERATOR FRAME_PULSE_PP_3 RX_CLK_3 TIMING SYSTEM TIMING PP_STS_DATA_4[7:0] RX_LTE_STS_DATA[7:0] FRAME_PULSE_RX_LTE4 RX_CLK_4 RX_RST_N4 POINTER INTERPRETER ELASTIC STORE POINTER GENERATOR FRAME_PULSE_PP_4 RX_CLK_4 TIMING SYSTEM TIMING 5-8152(F)r.1 Figure 36. Top Level Block Diagram of the Pointer Processor Block The STS pointer processor is used for phase absorption and frequency synchronization of SONET payload from one clock domain (the receive or line timing) to another (the transmit or system timing). This is accomplished in three basic functions: pointer interpreter, elastic store, and pointer generator. The pointer interpreter extracts the SONET synchronous payload envelope (SPE) from the incoming data by interpreting the H1 and H2 pointer bytes of the line overhead. The SPE is then written to the elastic store. The pointer generator reads the SPE from the elastic store and regenerates the H1 and H2 pointer bytes. Since the pointer processor does not terminate the path, intermediate performance monitoring is performed (i.e., the path overhead is not modified). A block diagram of the pointer processor is shown in Figure 36, above. Agere Systems Inc. 251 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) Detailed Description (continued) Performance Monitoring This block accepts the payload mapping information, status, and timing from the Rx pointer interpreter and extracts the path overhead from up to 12 STS channels. The extracted overhead is then either stored internally or provided externally on a serial output, and may also be further processed for alarm or performance-monitoring purposes. While an STS channel is in AIS or LOP status, all path overhead processing for the channel is inhibited. The definition and associated storage or processing of each byte is detailed below. Path Trace (J1). The path trace byte carries a repeating message that is defined in SONET as 64 bytes (ASCII, 252 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) Detailed Description (continued) Signal Fail Alarms. Each of the 48 STS-1s entering the PP can be automatically monitored for B3 errors against a programmable threshold. Concatenated payloads are supported by programming the threshold values for the head STS-1. Each STS-1 or head of an STS-NC has a select to choose which threshold group's parameters to compare against. There are eight threshold groups available, each group consisting of: Set Threshold. If the B3 errors is equal or greater than this value in the given time window, the signal fail alarm for this STS-1 is set. The B3 count in subsequent window times must be less than the clear threshold listed below to clear this error condition. Set Threshold Window Select. There are four time windows available between the eight groups. The set threshold window select can be set to one of these window sizes. Clear Threshold. If the signal fail alarm has been previously set, it will be cleared if an entire clear window time goes past with the B3 error count less than this value. Clear Threshold Window Select. If the signal fail alarm has been previously set, this window size will be used to measure B3 errors. Each STS-1 has a 9-bit B3 counter, which is incremented every time a B3 error appears. If STSs are part of an STS-Nc, there is one 14-bit counter for the entire concatenation. This counter is cleared at the end of the window selected for the threshold group for which this STS-1 or STS-Nc is set to. This counter (9 or 14 bits) can be incremented by 0 (if no B3 errors occurred) or up to 8 counts (if all the bits in the B3's BIP-8 calculation are opposite from expected). Note there are no bit/block issues with the signal fail counters; only bit errors are counted. Bit/ block is only an option for the B3 counters in the path monitoring (PM). The signal fail alarm is set if the number of B3 errors for an STS-1 or STS-Nc is above the set threshold within this window time. The B3 error counter for each STS-1 or STS-Nc is cleared at the end of each window and counts up again in the next window. One can set an individual STS-1/STS-Nc to set an alarm on one BER and clear this alarm on another. For this, a threshold count value and timing window is provided for both set and clear. For each STS-1 or STS-Nc, its B3 counter is running for either the time set by the set threshold window or the time set by the clear threshold window. If this STS-1/STS-Nc is in the clear state (the alarm bit is clear), then the signal fail circuitry will be looking for the case when the number of B3 errors equals or exceeds the set threshold. The counter will be running for the duration of the set threshold window. If this condition is reached, the alarm will be set immediately and the system will switch to watching the desired clear window. It will wait until the clear window has completed its current cycle and will start counting B3 errors again in the next cycle. The B3 counter will be cleared, and B3 errors will be added; at the end of this window time (now the clear window time), the decision will be made to clear the alarm condition or not. If the number of B3 errors in the counter is less than the clear threshold, the alarm will be cleared and, during the next window of length = set threshold window size, the counter will be compared to the set threshold. Otherwise, this error condition will remain set and another window of duration = clear threshold window size will commence. Agere Systems Inc. 253 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) Detailed Description (continued) The signal fail alarm can be set anywhere during the window, but can only be cleared at the end of a window time. The PP is either checking for the set or clear condition for an STS-1/STS-Nc at a given time. One implication of this is that if the clear threshold was set for a BER higher than the set threshold and an incoming signal of a constant BER between the two was present, the signal fail alarm would oscillate, set, and clear with a period of zero to one times the set window threshold window time plus one to two times the period of the clear window threshold window time. There are eight threshold groups available (see Table 197--Table 200); two are labelled as being used for STS-1s (group 0 and 1) and six (groups 2--7) are labelled for use as STS-Ncs. Group 0 and 1 have set and clear thresholds of 9 bits (0--511) whereas groups 2--7 have set and clear thresholds of up to 14 bits (0--16383). This is to accommodate the higher data rate of a concatenated payload and thus the higher number of bit errors one would see in the same time window for the same BER. However, one could point an STS-1 to group 2--7 as long as the thresholds are set to 511 or less to stay within the 9-bit size of an individual STS-1s counter. There are four threshold window size registers, each 16 bits, in increments of 0.5 ms (for a maximum of window size of 32 seconds). Table 324 on page 403 shows the recommended set/clear threshold and window values for the BER they are intended for. 254 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) Detailed Description (continued) Path Signal Label (C2). The path signal label byte is used to indicate either the type of payload carried in the STS SPE or the status of the payload. Of the 256 possible values, only the codes 0x01 to 0x04 and 0x12 to 0x15 are currently defined to identify payload types, while the codes E1 to FC are defined to indicate payload defects. The code 0xFF is a special reserved code due to its appearance in an STS AIS and is treated as a don't care during any defect detection or clearing. The C2 byte is extracted each frame and stored in the receive signal label registers. If the locally provisioned value, configured in the expected signal label registers, is any equipped value (i.e., not 00), the extracted signal label is also processed for the following defects: Payload Label Mismatch (PLM)--Detected if the extracted signal label is a valid payload-specific code and does not match the locally provisioned value in the expected signal label registers for five consecutive frames. Cleared if the extracted signal label matches the locally provisioned value, the equipped nonspecific code (0x01), or a valid PDI code for five consecutive frames. If the locally provisioned value is the equipped nonspecific code, then it matches any valid equipped code (including PDI). The valid payload specific codes are by default 0x02 to 0xE0, 0xFD and 0xFE, with the codes 0xE1 to 0xFB also included if the locally provisioned payload is VT structured (0x02 or 0x03). If payload defect indication detection is disabled, 0xE1 to 0xFC are always included. Detection of a PLM defect is indicated by a latched alarm status bit in the memory map. Path Unequipped (UNEQ)--Detected if the extracted signal label matches the unequipped code (0x00) for five consecutive frames. Cleared if the extracted signal label does not match the unequipped code for five consecutive frames. Detection of an UNEQ defect is indicated by a latched alarm status bit and a one second PM in the memory map. Update--The C2 value is dumped into an MPU register. Each time the captured value changes, a delta bit is set. Payload Defect Indication (PDI)--Detected if the extracted signal label matches a valid PDI code for five consecutive frames. Cleared if the extracted signal label does not match a valid PDI code for five consecutive frames. Valid PDI codes are 0xE1 to 0xFC when the locally provisioned payload label is 0x01, 0x02, or 0x03 (VT-structured STS) or just 0xFC otherwise. PDI detection can be disabled per STS through the microprocessor interface. Path Status (G1). The path status byte is used to convey the path termination status and performance back to the originating STS PTE. This allows the performance of the full-duplex path to be monitored from any single point along the path. Bits 1 to 4 are used as a remote error indication (formerly far-end block error or FEBE), while bits 5 to 7 are used as a remote defect indication. The G1 byte is extracted each frame and processed for these functions as described below. Remote Error Indication (REI-P)--Indicates the count of bit errors detected at the far-end STS PTE using the path BIP-8. The error count is a binary number from 0 to 8 (values above 8 are invalid and interpreted as 0) and is accumulated in an internal 16-bit counter based on either bit or block errors as provisioned per channel through the microprocessor interface. If bit error mode is enabled for the channel, the counter is incremented by the actual error count. If block error mode is enabled for the channel the counter is only incremented by one, when the error count is not 0, regardless of the actual value. The value in the counter accumulates until it is transferred to the REI-P registers on the positive edge of the performance-monitoring strobe (PMSTB input) at which point the counter is cleared. Remote Defect Indication (RDI-P)--Indicates the detection of a defect at the far-end STS PTE. Initially RDI-P was defined as a one bit value in bit 5, but has since been expanded to a 3-bit enhanced value (ERDI-P). Table 95 on page 256 shows the valid codes and interpretation for both the one bit and enhanced RDI schemes. As can be seen, bits 6 and 7 are always set to opposite values for ERDI while they are set to the same value for 1-bit RDI. The POH uses this fact to determine which RDI scheme is being used on a per STS basis. An RDI-P defect is then detected if a valid defect code for one of the RDI schemes is received for ten consecutive frames. The RDI-P defect is cleared when the no defects code for that scheme is received for ten consecutive frames. The value of the last validated 3-bit RDI code is stored in the ERDI-P registers in the memory map. In addition, detection of a 1-bit RDI defect or each of the three ERDI defects is indicated by a one second PM bit in the memory map. Agere Systems Inc. 255 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) Detailed Description (continued) Table 95. RDI-P Codes and Interpretation G1[5:7] 0xx* 1xx* 001 010 101 110 Priority of Enhanced RDI-P Codes Not applicable Not applicable 4 3 1 2 Trigger No defects AIS-P, LOP-P No defects PLM-P, LCD-P AIS-P, LOP-P Interpretation No RDI-P defect. 1-bit RDI-P defect. NO ERDI-P defects. ERDI-P payload defect. ERDI-P server defect. UNEQ-P, TIM-P ERDI-P connectivity defect. * These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 2 and 1 must be set to the same value, and should be set to 00. These codes are transmitted by STS PTE that support enhanced RDI-P. 256 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map Overview 0x1000 ID REGISTER 0x100F INTERRUPTS 0x120F MASKS 0x1300 0x1382 PERSISTENCY 0x13C2 STATE 0x1400 SF DETECT/CLEAR PATH TRACE 0x1502 CONCATENATION MAP 0x1542 AIS-P GENERAL CONTROL 0x1580 PP CONTROL 0x1600 PATH PROVISIONING 0x1690 PATH MAINTENANCE 0x1702 INTER INC/DEC (PM) 0x1742 GEN INC/DEC (PM) RESERVED 0x1780 POH PM 0x1800 0x1880 REI COUNT PM 0x1900 RDI, C2, PDI 5-8156(F).ar.1 CV COUNT PM Figure 37. Overview of Pointer Processor Register Map Agere Systems Inc. 257 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions To access (read and write) registers RXCLK[A--D][P/N] (see Pin Descriptions--Line Interface Signals, Table 7, on page 97) must always be present for a given application. Table 96. PP_IDR, PP Identification Register (RO, Fixed Value) Address 0x1000 Bit 15:0 Name PP_ID[15:0] Function Pointer Processor Identification Register. Reset Default 0001 Table 97. PP_CORWR, PP Clear on Read/Write Register (R/W, Control) Address 0x1001 Bit 15:1 0 Name -- PP_CORW Reserved. PP Clear On Read/Write. Sets the mode for clearing alarm bit in the PP block. 0 = Clear interrupt bits with writing 1 to that bit in the alarm register. 1 = Clear all alarm bits in an interrupt alarm register by reading that register. Note:This affects only the pointer processor interrupt alarms, i.e., only the ones listed in this section (pointer processor) of the data sheet. Function Reset Default 0 0 258 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Interrupts Table 98. PP_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) Address Bit Name -- -- Reserved. SS Mismatch Alarm. 0 = SS mismatch alarm has not been detected for any STS1 in any bytestream. 1 = SS mismatch alarm has been detected for one or more STS-1s in one or more bytestreams. 8 -- SS Validated Alarm. 0 = SS validated alarm has not been detected for any STS1 in any bytestream. 1 = SS validated alarm has been detected for one or more STS-1s in one or more bytestreams. 7 -- F2 Validated Alarm. 0 = F2 validated alarm has not been detected for the selected STS-1 in any bytestream. 1 = F2 validated alarm has been detected for the selected STS-1 in one or more bytestreams. 6 -- H4 Validated Alarm. 0 = H4 validated alarm has not been detected for the selected STS-1 in any bytestream. 1 = H4 validated alarm has been detected for the selected STS-1 in one or more bytestreams. 5 -- Z3 Validated Alarm. 0 = Z3 validated alarm has not been detected for the selected STS-1 in any bytestream. 1 = Z3 validated alarm has been detected for the selected STS-1 in one or more bytestreams. 4 -- Z4 Validated Alarm. 0 = Z4 validated alarm has not been detected for the selected STS-1 in any bytestream. 1 = Z4 validated alarm has been detected for the selected STS-1 in one or more bytestreams. 3 -- Z5 Validated Alarm. 0 = Z5 validated alarm has not been detected for the selected STS-1 in any bytestream. 1 = Z5 validated alarm has been detected for the selected STS-1 in one or more bytestreams. 0 0 0 0 0 0 Function Reset Default 0 0 0x100F 15:10 9 Agere Systems Inc. 259 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 98. PP_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) (continued) Address 0x100F Bit 2 Name PP_PDI_ALMDBN Function Payload Defect Indicator (PDI) Alarm Delta Binning. 0 = PDI alarm delta has not been detected for any STS-1 in any bytestream. 1 = PDI alarm delta has been detected for one or more STS-1s in one or more bytestreams. 1 PP_PDI_ALMBN Payload Defect Indicator (PDI) Alarm Binning. 0 = PDI alarm has not been detected for any STS-1 in any bytestream. 1 = PDI alarm has been detected for one or more STS-1s in one or more bytestreams. 0 PP_J1ACCMP_ALMBN J1 Access Complete Alarm Binning. 0 = J1 access complete alarm has not been detected for any STS-1 in any bytestream. 1 = J1 access complete alarm has been detected for one or more STS-1s in one or more bytestreams. 0 0 Reset Default 0 260 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 98. PP_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) (continued) Address 0x1010 Bit 15 Name PP_RDI_ALMDBN Function Remote Defect Indicator Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 14 PP_PLM_ALMDBN Payload Label Mismatch Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 13 PP_UNEQR_ ALMDBN Unequipped Received Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. Alarm Indicator Signal Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 11 PP_LOP_ALMDBN Loss of Pointer Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 10 PP_J1MM_ALMBN J1 Mismatch Alarm Binning. 0 = No J1 mismatch alarm has been detected in any bytestream. 1 = J1 mismatch alarm has been detected in one or more bytestreams. 9 PP_J1VLD_ALMBN J1 Validated Alarm Binning. 0 = No new validated J1 has been detected in any bytestream. 1 = New validated J1 has been detected in one or more bytestreams. 8 PP_USCNCT_ ALMBN Unsupported Concatenation Alarm Binning. 0 = None of the four bytestreams has an unsupported concatenation. 1 = One of the four bytestreams has an unsupported concatenation. 0 0 0 0 0 0 0 Reset Default 0 12 PP_AIS_ALMDBN Agere Systems Inc. 261 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 98. PP_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) (continued) Address 0x1010 Bit 7 Name PP_CNCTMM_ ALMBN Function Concatenation Mismatch Alarm Binning. 0 = None of the four bytestreams has a concatenation mismatch. 1 = One of the four bytestreams has a concatenation mismatch. Elastic Store Overrun/Underrun Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 5 PP_SF_ALMBN Signal Fail Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 4 PP_RDI_ALMBN Remote Defect Indicator Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 3 PP_PLM_ALMBN Payload Label Mismatch Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 2 PP_UNEQR_ ALMBN Unequipped Received Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. Alarm Indicator Signal Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 PP_LOP_ALMBN Loss of Pointer Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 0 0 0 0 0 0 Reset Default 0 6 PP_ES_ALMBN 1 PP_AIS_ALMBN 262 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 99. PP_ES_ALMBNBSR, Elastic Store Overrun/Underrun Alarm Status Binning Bytestream A--D (RO) Address 0x1021 Bit 15:4 3:0 Name -- Reserved. Function Reset Default 0 0 PP_ES_ALMBNBS[A--D] Elastic Store Overrun/Underrun Binning Bytestream A--D. 0 = Elastic store overrun/underrun has not been detected for any STS-1s in bytestream A--D. 1 = Elastic store overrun/underrun has been detected for one or more STS-1s in bytestream A--D. Table 100. PP_TSES_ALMBSR[A--D], Time Slots 1--12 Elastic Store Overrun/Underrun Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSES_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Elastic Store Overrun/ Underrun Bytestream A--D. 0 = Elastic store overrun/underrun has not been detected. 1 = Elastic store overrun/underrun has been detected. Table 101. PP_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A--D (RO) Address 0x1031 Bit 15:4 3:0 Name -- Reserved. 0 = Signal fail has not been detected for any STS-1s in bytestream A--D. 1 = Signal fail has been detected for one or more STS-1s in bytestream A--D. Table 102. PP_TSSF_ALMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Bytestream A--D (RO, COR/ COW) Address Bit Name -- PP_TSSF_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Signal Fail Bytestream A--D. 0 = Signal fail has not been detected. 1 = Signal fail has been detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 1 0x1022, 15:12 0x1023, 11:0 0x1024, 0x1025 PP_SF_ALMBNBS[A--D] Signal Fail Binning Bytestream A--D. 0x1032, 15:12 0x1033, 11:0 0x1034, 0x1035 Agere Systems Inc. 263 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 103. PP_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A--D (RO) Address 0x1041 Bit 15:4 3:0 Name -- PP_RDI_ ALMBNBS[A--D] Reserved. Remote Defect Indicator Binning Bytestream A--D. 0 = Remote defect indicator has not been detected for any STS-1s in bytestream A--D. 1 = Remote defect indicator has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 104. PP_TSRDI_ALMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSRDI_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Bytestream A--D. 0 = Remote defect indicator has not been detected. 1 = Remote defect indicator has been detected. Table 105. PP_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A--D (RO) Address 0x1051 Bit 15:4 3:0 Name -- PP_PLM_ ALMBNBS[A--D] Reserved. Payload Label Mismatch Binning Bytestream A--D. 0 = Payload label mismatch has not been detected for any STS-1s in bytestream A--D. 1 = Payload label mismatch has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x1042, 15:12 0x1043, 11:0 0x1044, 0x1045 Table 106. PP_TSPLM_ALMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSPLM_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Bytestream A--D. 0 = Payload label mismatch has not been detected. 1 = Payload label mismatch has been detected. Function Reset Default 0 0 0x1052, 15:12 0x1053, 11:0 0x1054, 0x1055 264 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 107. PP_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A--D (RO) Address 0x1061 Bit 15:4 3:0 Name -- PP_UNEQR_ ALMBNBS[A--D] Reserved. Unequipped Received Binning Bytestream A--D. 0 = Unequipped received has not been detected for any STS-1s in bytestream A--D. 1 = Unequipped received has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 108. PP_TSUNEQR_ALMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSUNEQR_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Unequipped Received Bytestream A--D. 0 = Unequipped received has not been detected. 1 = Unequipped received has been detected. Table 109. PP_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A--D (RO) Address 0x1071 Bit 15:4 3:0 Name -- Reserved. 0 = Alarms indicator signal has not been detected for any STS-1s in bytestream A--D. 1 = Alarms indicator signal has been detected for one or more STS-1s in bytestream A--D. Table 110. PP_TSAIS_ALMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSAIS_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarms Indicator Signal Bytestream A--D. 0 = Alarms indicator signal has not been detected. 1 = Alarms indicator signal has been detected. Function Reset Default 0 1 Function Reset Default 0 0 Function Reset Default 0 0 0x1062, 15:12 0x1063, 11:0 0x1064, 0x1065 PP_AIS_ALMBNBS[A--D] Alarms Indicator Signal Binning Bytestream A--D. 0x1072, 15:12 0x1073, 11:0 0x1074, 0x1075 Agere Systems Inc. 265 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 111. PP_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A--D (RO) Address 0x1081 Bit 15:4 3:0 Name -- PP_LOP_ ALMBNBS[A--D] Reserved. Loss of Pointer Binning Bytestream A--D. 0 = Loss of pointer has not been detected for any STS-1s in bytestream A--D. 1 = Loss of pointer has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 112. PP_TSLOP_ALMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSLOP_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Bytestream A--D. 0 = Loss of pointer has not been detected. 1 = Loss of pointer has been detected. Function Reset Default 0 1 0x1082, 15:12 0x1083, 11:0 0x1084, 0x1085 266 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 113. PP_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW) Address 0x1091 Bit 15:4 3:0 Name -- PP_CNCTMM_ ALMBNBS[A--D] Reserved. Concatenation Map Mismatch Binning Bytestream A--D. 0 = No expected/received concatenation state mismatches on any time slot. 1 = Expected/received concatenation state mismatch in at least one time slot. Table 114. PP_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning Bytestream A--D (RO, COR/COW) Address 0x10A1 Bit 15:4 3:0 Name -- PP_USCNCTM_ ALMBNBS[A--D] Reserved. Unsupported Concatenation Map Binning Bytestream A--D. 0 = No path alarm. 1 = Alarm detected. Table 115. PP_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning Bytestream A--D (RO, COR/COW) Address 0x10C1 Bit 15:4 3:0 Name -- PP_J1NVLDMSG_ ALMBNBS[A--D] Reserved. J1 New Validated Message Binning Bytestream A--D. 0 = No path alarm. 1 = Alarm detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 Table 116. PP_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW) Address 0x10D1 Bit 15:4 3:0 Name -- PP_J1MSGMM_ ALMBNBS[A--D] Reserved. J1 Message Mismatch Binning Bytestream A--D. 0 = No path alarm. 1 = Alarm detected. Function Reset Default 0 0 Agere Systems Inc. 267 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 117. PP_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A--D (RO) Address 0x1101 Bit 15:4 3:0 Name -- Reserved. 0 = Payload defect indicator has not been detected for any STS-1s in bytestream A--D. 1 = Payload defect indicator has been detected for one or more STS-1s in bytestream A--D. Table 118. PP_TSPDI_ALMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSPDI_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Bytestream A--D. 0 = Payload defect indicator has not been detected. 1 = Payload defect indicator has been detected. Table 119. PP_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) Address 0x1111 Bit 15:4 3:0 Name -- PP_RDI_ ALMDBNBS[A--D] Reserved. Remote Defect Indicator Delta Binning Bytestream A--D. 0 = Remote defect indicator delta has not been detected for any STS-1s in bytestream A--D. 1 = Remote defect indicator delta has been detected for one or more STS-1s in bytestream A--D. Table 120. PP_TSRDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSRDI_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Delta Bytestream A--D. 0 = Remote defect indicator delta has not been detected. 1 = Remote defect indicator delta has been detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 PP_PDI_ALMBNBS[A--D] Payload Defect Indicator Binning Bytestream A--D. 0x1102, 15:12 0x1103, 11:0 0x1104, 0x1105 0x1112, 15:12 0x1113, 11:0 0x1114, 0x1115 268 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 121. PP_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Bytestream A--D (RO) Address 0x1121 Bit 15:4 3:0 Name -- PP_PLM_ ALMDBNBS[A--D] Reserved. Payload Label Mismatch Delta Binning Bytestream A--D. 0 = Payload label mismatch delta has not been detected for any STS-1s in bytestream A--D. 1 = Payload label mismatch delta has been detected for one or more STS-1s in bytestream A--D. Table 122. PP_TSPLM_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSPLM_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Delta Bytestream A--D. 0 = Payload label mismatch delta has not been detected. 1 = Payload label mismatch delta has been detected. Table 123. PP_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Bytestream A--D (RO) Address 0x1131 Bit 15:4 3:0 Name -- PP_UNEQR_ ALMDBNBS[A--D] Reserved. Unequipped Received Delta Binning Bytestream A--D. 0 = Unequipped received delta has not been detected for any STS-1s in bytestream A--D. 1 = Unequipped received delta has been detected for one or more STS-1s in bytestream A--D. Table 124. PP_TSUNEQR_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 6 0x1122, 15:12 0x1123, 11:0 0x1124, 0x1125 -- Reserved. 0x1132, 15:12 0x1133, 11:0 PP_TSUNEQR_ALMDBS Time Slot 1--Time Slot 12 Unequipped Received Delta 0x1134, [A--D][1--12] Bytestream A--D. 0x1135 0 = Unequipped received delta has not been detected. 1 = Unequipped received delta has been detected. Agere Systems Inc. 269 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 125. PP_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Bytestream A--D (RO) Address 0x1141 Bit 15:4 3:0 Name -- PP_AIS_ ALMDBNBS[A--D] Reserved. Alarm Indicator Signal Delta Binning Bytestream A--D. 0 = Alarm indicator signal delta has not been detected for any STS-1s in bytestream A--D. 1 = Alarm indicator signal delta has been detected for one or more STS-1s in bytestream A--D. Table 126. PP_TSAIS_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSAIS_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarm Indicator Signal Delta Bytestream A--D. 0 = Alarm indicator signal delta has not been detected. 1 = Alarm indicator signal delta has been detected. Table 127. PP_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Bytestream A--D (RO) Address 0x1151 Bit 15:4 3:0 Name -- PP_LOP_ ALMDBNBS[A--D] Reserved. Loss of Pointer Delta Binning Bytestream A--D. 0 = Loss of pointer delta has not been detected for any STS-1s in bytestream A--D. 1 = Loss of pointer delta has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 1 Function Reset Default 0 0 0x1142, 15:12 0x1143, 11:0 0x1144, 0x1145 Table 128. PP_TSLOP_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSLOP_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Delta Bytestream A--D. 0 = Loss of pointer delta has not been detected. 1 = Loss of pointer delta has been detected. Function Reset Default 0 1 0x1152, 15:12 0x1153, 11:0 0x1154, 0x1155 270 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 129. PP_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW) Address 0x1160 Bit 15:1 0 Name -- PP_J1BFACCMPI Reserved. J1 Buffer Access Complete Interrupt. 0 = No alarm. 1 = Alarm detected. Table 130. PP_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) Address 0x1171 Bit 15:4 3:0 Name -- PP_PDI_ ALMDBNBS[A--D] Reserved. Payload Defect Indicator Delta Binning Bytestream A--D. 0 = Payload defect indicator delta has not been detected for any STS-1s in bytestream A--D. 1 = Payload defect indicator delta has been detected for one or more STS-1s in bytestream A--D. Table 131. PP_TSPDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSPDI_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Delta Bytestream A--D. 0 = Payload defect indicator delta has not been detected. 1 = Payload defect indicator delta has been detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 0x1172, 15:12 0x1173, 11:0 0x1174, 0x1175 Agere Systems Inc. 271 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 132. STS-1 #12 Channel Path Alarm Binning Status Registers (RO) Address 0x1177 Bit 15:4 3 2 1 0 0x1179 15:4 3 2 1 0 0x117B 15:4 3 2 1 0 0x117D 15:4 3 2 1 0 0x117F 15:4 3 2 1 0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Z5 New Validated Bytestream A. Z5 New Validated Bytestream B. Z5 New Validated Bytestream C. Z5 New Validated Bytestream D. Reserved. Z4 New Validated Bytestream A. Z4 New Validated Bytestream B. Z4 New Validated Bytestream C. Z4 New Validated Bytestream D. Reserved. Z3 New Validated Bytestream A. Z3 New Validated Bytestream B. Z3 New Validated Bytestream C. Z3 New Validated Bytestream D. Reserved. H4 New Validated Bytestream A. H4 New Validated Bytestream B. H4 New Validated Bytestream C. H4 New Validated Bytestream D. Reserved. F2 New Validated Bytestream A. F2 New Validated Bytestream B. F2 New Validated Bytestream C. F2 New Validated Bytestream D. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 272 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 133. STS-1 Channel Path SS New Validated Bits Alarm Status Binning Bytestream A--D (RO) Address 0x1181 Bits 15:4 3:0 Name -- -- Reserved. SS New Validated Bits Bytestream A--D. 0 = SS new validated bits has not been detected for any STS-1s in bytestream A--D. 1 = SS new validated bits has been detected for one or more STS-1s in bytestream A--D. Table 134. STS-1 Channel Path Time Slots 1--12 SS New Validated Bits Alarm Status Bytestream A--D (RO, COR/COW) Address 0x1182, 0x1183, 0x1184, 0x1185 Bits 15:12 11:0 Name -- -- Reserved. Time Slot 1--Time Slot 12 SS New Validated Bits Bytestream A--D. Description Reset Default 0 0 Description Reset Default 0 0 Table 135. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Bytestream A--D (RO) Address 0x1187 Bits 15:4 3:0 Name -- -- Reserved. SS Bits Mismatch Bytestream A--D. 0 = SS bits mismatch has not been detected for any STS-1s in bytestream A--D. 1 = SS bits mismatch has been detected for one or more STS-1s in bytestream A--D. Table 136. STS-1 Channel Path Time Slots 1--12 SS Bits Mismatch Alarm Status Bytestream A--D (RO, COR/COW) Address 0x1188, 0x1189, 0x118A, 0x118B Bits 15:12 11:0 Name -- -- Reserved. Time Slot 1--Time Slot 12 SS Bits Mismatch Bytestream A--D. Description Reset Default 0 0 Description Reset Default 0 0 Agere Systems Inc. 273 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Masks Table 137. PP_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) Address Bit Name -- -- Reserved. SS Mismatch Alarm Mask. 0 = SS mismatch alarm is passed through. 1 = SS mismatch alarm masked. 8 -- SS Validated Alarm Mask. 0 = SS validated alarm is passed through. 1 = SS validated alarm masked. 7 -- F2 Validated Alarm Mask. 0 = F2 validated alarm is passed through. 1 = F2 validated alarm masked. 6 -- H4 Validated Alarm Mask. 0 = H4 validated alarm is passed through. 1 = H4 validated alarm masked. 5 -- Z3 Validated Alarm Mask. 0 = Z3 validated alarm is passed through. 1 = Z3 validated alarm masked. 4 -- Z4 Validated Alarm Mask. 0 = Z4 validated is passed through. 1 = Z4 validated alarm masked. 3 -- Z5 Validated Alarm Mask. 0 = Z5 validated alarm is passed through. 1 = Z5 validated alarm masked. 2 PP_PDI_ALMDBNM Payload Defect Indicator (PDI) Alarm Delta Binning Mask. 0 = PDI delta alarm is passed through. 1 = PDI delta alarm masked. 1 PP_PDI_ALMBNM Payload Defect Indicator (PDI) Alarm Binning Mask. 0 = PDI alarm is passed through. 1 = PDI alarm masked. 0 PP_J1ACCMP_ALMBNM J1 Access Complete Alarm Binning Mask. 0 = J1 access complete alarm is passed through. 1 = J1 access complete alarm masked. 1 1 1 1 1 1 1 1 1 Function Reset Default -- 1 0x120F 15:10 9 274 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 137. PP_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) (continued) Address 0x1210 Bit 15 Name PP_RDI_ALMDBNM Function Remote Defect Indicator Alarm Delta Binning Mask. 0 = Remote defect indicator delta alarm is passed through. 1 = Remote defect indicator delta alarm masked. 14 PP_PLM_ALMDBNM Payload Label Mismatch Alarm Delta Binning Mask. 0 = Payload label mismatch delta alarm is passed through. 1 = Payload label mismatch delta alarm masked. 13 PP_UNEQR_ALMDBNM Unequipped Received Alarm Delta Binning Mask. 0 = Unequipped received delta alarm is passed through. 1 = Unequipped received delta alarm masked. 12 PP_AIS_ALMDBNM Alarm Indicator Signal Alarm Delta Binning Mask. 0 = Alarm indicator signal delta alarm is passed through. 1 = Alarm indicator signal delta alarm masked. 11 PP_LOP_ALMDBNM Loss of Pointer Alarm Delta Binning Mask. 0 = Loss of pointer delta alarm is passed through. 1 = Loss of pointer delta alarm masked. 10 PP_J1MM_ALMM J1 Mismatch Alarm Binning Mask. 0 = J1 mismatch alarm is passed through. 1 = J1 mismatch alarm masked. 9 PP_J1VLD_ALMBNM J1 Validated Alarm Binning Mask. 0 = J1 validated alarm is passed through. 1 = J1 validated alarm masked. 8 PP_USCNCT_ALMBNM Unsupported Concatenation Alarm Binning Mask. 0 = Unsupported concatenation alarm is passed through. 1 = Unsupported concatenation alarm masked. 7 PP_CNCTMM_ALMBNM Concatenation Mismatch Alarm Binning Mask. 0 = Concatenation mismatch alarm is passed through. 1 = Concatenation mismatch alarm masked. 6 PP_ES_ALMBNM Elastic Store Overrun/Underrun Alarm Binning Mask. 0 = Elastic store overrun/underrun alarm is passed through. 1 = Elastic store overrun/underrun alarm masked. 5 PP_SF_ALMBNM Signal Fail Alarm Binning Mask. 0 = Signal fail alarm is passed through. 1 = Signal fail alarm masked. 1 1 1 1 1 1 1 1 1 1 Reset Default 1 Agere Systems Inc. 275 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 137. PP_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) (continued) Address 0x1210 Bit 4 Name PP_RDI_ALMBNM Function Remote Defect Indicator Alarm Binning Mask. 0 = Remote defect indicator alarm is passed through. 1 = Remote defect indicator alarms masked. 3 PP_PLM_ALMBNM Payload Label Mismatch Alarm Binning Mask. 0 = Payload label mismatch alarm is passed through. 1 = Payload label mismatch alarms masked. 2 PP_UNEQR_ALMBNM Unequipped Received Alarm Binning Mask. 0 = Unequipped received alarm is passed through. 1 = Unequipped received alarms masked. 1 PP_AIS_ALMBNM Alarm Indicator Signal Alarm Binning Mask. 0 = Alarm indicator signal alarm is passed through. 1 = Alarm indicator signal alarms masked. 0 PP_LOP_ALMBNM Loss of Pointer Alarm Binning Mask. 0 = Loss of pointer alarm is passed through. 1 = Loss of pointer alarms masked. 1 1 1 1 Reset Default 1 276 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 138. PP_ES_ALMBNMBSR, Elastic Store Overrun/Underrun Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1211 Bit 15:4 3:0 Name -- PP_ES_ ALMMBSBN[A--D] Reserved. Elastic Store Overrun/Underrun Binning Masks Bytestream A--D. 0 = Elastic store overrun/underrun alarms in bytestream A--D are passed through. 1 = Elastic store overrun/underrun alarms in bytestream A--D are masked. Table 139. PP_TSES_ALMMBSR[A--D], Time Slots 1--12 Elastic Store Overrun/Underrun Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSES_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Elastic Store Overrun/ Underrun Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1111 0x1212, 15:12 0x1213, 11:0 0x1214, 0x1215 Table 140. PP_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1221 Bit 15:4 3:0 Name -- PP_SF_ ALMBNMBS[A--D] Reserved. Signal Fail Binning Masks Bytestream A--D. 0 = Signal fail alarms in bytestream A--D are passed through. 1 = Signal fail alarms in bytestream A--D are masked. Function Reset Default -- 1111 Table 141. PP_TSSF_ALMMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSSF_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Signal Fail Masks Bytestream A--D. Function Reset Default -- 1 0x1222, 15:12 0x1223, 11:0 0x1224, 0x1225 Agere Systems Inc. 277 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 142. PP_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1231 Bit 15:4 3:0 Name -- PP_RDI_ ALMBNMBS[A--D] Reserved. Remote Defect Indicator Binning Masks Bytestream A--D. 0 = Remote defect indicator alarms in bytestream A--D are passed through. 1 = Remote defect indicator alarms in bytestream A--D are masked. Table 143. PP_TSRDI_ALMMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSRDI_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x1232, 15:12 0x1233, 11:0 0x1234, 0x1235 Table 144. PP_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1241 Bit 15:4 3:0 Name -- PP_PLM_ ALMBNMBS[A--D] Reserved. Payload Label Mismatch Binning Masks Bytestream A--D. 0 = Payload label mismatch alarms in bytestream A--D are passed through. 1 = Payload label mismatch alarms in bytestream A--D are masked. Table 145. PP_TSPLM_ALMMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSPLM_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x1242, 15:12 0x1243, 11:0 0x1244, 0x1245 278 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 146. PP_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1251 Bit 15:4 3:0 Name -- PP_UNEQR_ ALMBNMBS[A--D] Reserved. Unequipped Received Binning Masks Bytestream A--D. 0 = Unequipped received alarms in bytestream A--D are passed through. 1 = Unequipped received alarms in bytestream A--D are masked. Table 147. PP_TSUNEQR_ALMMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Masks Bytestream A--D (R/W) Address Bit Name Function Reset Default -- 1 Function Reset Default -- 1 -- Reserved. 0x1252, 15:12 0x1253, 11:0 PP_TSUNEQR_ALMMBS Time Slot 1--Time Slot 12 Unequipped Received 0x1254, [A--D][1--12] Masks Bytestream A--D. 0x1255 Table 148. PP_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1261 Bit 15:4 3:0 Name -- PP_AIS_ ALMBNMBS[A--D] Reserved. Alarms Indicator Signal Binning Masks Bytestream A--D. 0 = Alarms indicator signal alarms in bytestream A--D are passed through. 1 = Alarms indicator signal alarms in bytestream A--D are masked. Table 149. PP_TSAIS_ALMMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSAIS_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarms Indicator Signal Masks Bytestream A--D. Function Function Reset Default -- 1 Reset Default -- 1 0x1262, 15:12 0x1263, 11:0 0x1264, 0x1265 Agere Systems Inc. 279 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 150. PP_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1271 Bit 15:4 3:0 Name -- PP_LOP_ ALMBNMBS[A--D] Reserved. Loss of Pointer Binning Masks Bytestream A--D. 0 = Loss of pointer alarms in bytestream A--D are passed through. 1 = Loss of pointer alarms in bytestream A--D are masked. Function Reset Default -- 1 Table 151. PP_TSLOP_ALMMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSLOP_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Masks Bytestream A--D. Function Reset Default -- 1 0x1272, 15:12 0x1273, 11:0 0x1274, 0x1275 280 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 152. PP_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A--D (R/W) Address 0x1277 Bit 15:4 3:0 Name -- PP_CNCTMM_ ALMMBS[A--D] Reserved. Concatenation Map Mismatch Mask Bytestream A--D. 0 = Path alarm is passed through. 1 = Path alarm is masked. Function Reset Default -- 1 Table 153. PP_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks Bytestream A--D (R/W) Address 0x1279 Bit 15:4 3:0 Name -- PP_USCNCTM_ ALMMBS[A--D] Reserved. Unsupported Concatenation Map Mask Bytestream A--D. 0 = Alarm is passed through. 1 = Alarm is masked. Table 154. PP_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks Bytestream A--D(R/W) Address 0x127B Bit 15:4 3:0 Name -- PP_J1NVLDMSG ALMMBS[A--D] Reserved. J1 New Validated Message Mask Bytestream A--D. 0 = Alarm is passed through. 1 = Alarm is masked. Function Reset Default -- 1 Function Reset Default -- 1 Table 155. PP_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks Bytestream A--D (R/W) Address 0x127D Bit 15:4 3:0 Name -- PP_J1MSGMM_ ALMMBS[A--D] Reserved. J1 Message Mismatch Mask Bytestream A--D. 0 = Alarm is passed through. 1 = Alarm is masked. Function Reset Default -- 1 Agere Systems Inc. 281 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 156. PP_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x1281 Bit 15:4 3:0 Name -- PP_PDI_ ALMBNMBS[A--D] Reserved. Payload Defect Indicator Binning Masks Bytestream A--D. 0 = Payload defect indicator alarms in bytestream A--D are passed through. 1 = Payload defect indicator alarms in bytestream A--D are masked. Table 157. PP_TSPDI_ALMMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSPDI_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Masks Bytestream A--D. Function Reset Default 0 1 Function Reset Default 0 1 0x1282, 15:12 0x1283, 11:0 0x1284, 0x1285 282 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 158. PP_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x1291 Bit 15:4 3:0 Name -- PP_RDI_ALMDBNMBS [A--D] Reserved. Remote Defect Indicator Delta Binning Masks Bytestream A--D. 0 = Remote defect indicator delta alarms in bytestream A--D are passed through. 1 = Remote defect indicator delta alarms in bytestream A--D are masked. Table 159. PP_TSRDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSRDI_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x1292, 15:12 0x1293, 11:0 0x1294, 0x1295 Table 160. PP_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x12A1 Bit 15:4 3:0 Name -- PP_PLM_ALMDBNMBS [A--D] Reserved. Payload Label Mismatch Delta Binning Masks Bytestream A--D. 0 = Payload label mismatch delta alarms in bytestream A--D are passed through. 1 = Payload label mismatch delta alarms in bytestream A--D are masked. Table 161. PP_TSPLM_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSPLM_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x12A2, 15:12 0x12A3, 11:0 0x12A4, 0x12A5 Agere Systems Inc. 283 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 162. PP_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x12B1 Bit 15:4 3:0 Name -- PP_UNEQR_ ALMDBNMBS[A--D] Reserved. Unequipped Received Delta Binning Masks Bytestream A--D. 0 = Unequipped received delta alarms in bytestream A--D are passed through. 1 = Unequipped received delta alarms in bytestream A--D are masked. Table 163. PP_TSUNEQR_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- Reserved. Function Reset Default -- 1 Function Reset Default -- 1 0x12B2, 15:12 0x12B3, 11:0 0x12B4, 0x12B5 PP_TSUNEQR_ Time Slot 1--Time Slot 12 Unequipped Received Delta ALMDMBS[A--D][1--12] Masks Bytestream A--D. 284 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 164. PP_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x12C1 Bit 15:4 3:0 Name -- PP_AIS_ALMDBNMBS [A--D] Reserved. Alarm Indicator Signal Delta Binning Masks Bytestream A--D. 0 = Alarm indicator signal delta alarms in bytestream A--D are passed through. 1 = Alarm indicator signal delta alarms in bytestream A--D are masked. Table 165. PP_TSAIS_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSAIS_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarm Indicator Signal Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x12C2, 15:12 0x12C3, 11:0 0x12C4, 0x12C5 Table 166. PP_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x12D1 Bit 15:4 3:0 Name -- PP_LOP_ALMDBNMBS [A--D] Reserved. Loss of Pointer Delta Binning Masks Bytestream A--D. 0 = Loss of pointer delta alarms in bytestream A--D are passed through. 1 = Loss of pointer delta alarms in bytestream A--D are masked. Table 167. PP_TSLOP_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSLOP_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x12D2, 15:12 0x12D3, 11:0 0x12D4, 0x12D5 Agere Systems Inc. 285 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 168. PP_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W) Address 0x12E0 Bit 15:1 0 Name -- PP_J1BFACCMPIM Reserved. J1 Buffer Access Complete Mask. 0 = Alarm is passed through. 1 = Alarm is masked. Table 169. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Masks Bytestream A--D (R/W) Address Bits 0x12E2 15:4 3:0 Name -- -- Reserved. SS Bits Mismatch Mask Bytestream A--D. 0 = SS bits mismatch alarms in bytestream A--D are passed through. 1 = SS bits mismatch alarms in bytestream A--D are masked. Table 170. STS-1 Channel Path Time Slots 1--12 SS Bits Mismatch Alarm Status Binning Masks Bytestream A--D (R/W) Address Bit Name -- -- Reserved. Time Slot 1--Time Slot 12 SS Bits Mismatch Mask Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 Function Reset Default -- 1 0x12E3, 15:12 0x12E4, 11:0 0x12E5, 0x12E6 286 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 171. PP_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x12E9 Bit 15:4 3:0 Name -- PP_PDI_ALMDBNMBS [A--D] Reserved. Payload Defect Indicator Delta Binning Masks Bytestream A--D. 0 = Payload defect indicator delta alarms in bytestream A--D are passed through. 1 = Payload defect indicator delta alarms in bytestream A--D are masked. Table 172. PP_TSPDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- PP_TSPDI_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x12EA, 15:12 0x12EB, 11:0 0x12EC, 0x12ED Agere Systems Inc. 287 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 173. STS-1 #12 Channel Path Alarm Binning Mask Status Registers (R/W) Address 0x12EF Bit 15:4 3 2 1 0 0x12F1 15:4 3 2 1 0 0x12F3 15:4 3 2 1 0 0x12F5 15:4 3 2 1 0 0x12F7 15:4 3 2 1 0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Z5 New Validated Mask Bytestream A. Z5 New Validated Mask Bytestream B. Z5 New Validated Mask Bytestream C. Z5 New Validated Mask Bytestream D. Reserved. Z4 New Validated Mask Bytestream A. Z4 New Validated Mask Bytestream B. Z4 New Validated Mask Bytestream C. Z4 New Validated Mask Bytestream D. Reserved. Z3 New Validated Mask Bytestream A. Z3 New Validated Mask Bytestream B. Z3 New Validated Mask Bytestream C. Z3 New Validated Mask Bytestream D. Reserved. H4 New Validated Mask Bytestream A. H4 New Validated Mask Bytestream B. H4 New Validated Mask Bytestream C. H4 New Validated Mask Bytestream D. Reserved. F2 New Validated Mask Bytestream A. F2 New Validated Mask Bytestream B. F2 New Validated Mask Bytestream C. F2 New Validated Mask Bytestream D. Function Reset Default -- 1 1 1 1 -- 1 1 1 1 -- 1 1 1 1 -- 1 1 1 1 -- 1 1 1 1 288 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 174. STS-1 Channel Path SS New Validated Bits Alarm Binning Masks Bytestream A--D (R/W) Address 0x12F9 Bit 15:4 3:0 Name -- -- Reserved. SS New Validated Bits Masks Bytestream A--D. 0 = SS new validated bits alarms in bytestream A--D are passed through. 1 = SS new validated bits alarms in bytestream A--D are masked. Table 175. STS-1 Channel Path Time Slots 1--12 SS New Validated Bits Alarm Masks Bytestream A--D (R/W) Address Bit Name -- -- Reserved. Time Slot 1--Time Slot 12 SS New Validated Bits Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x12FA, 15:12 0x12FB, 11:0 0x12FC, 0x12FD Agere Systems Inc. 289 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Path Trace Table 176. PP_PTRBFR[1--32], Path Trace Buffer Registers 1--32 (R/W) Address 0x1300 -- 0x131F Bit 15:8 7:0 Name PP_J1BYTE1[7:0] PP_J1BYTE0[7:0] Function J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer. J1 Byte 0, 2, 4, . . . , 62 Path Trace Buffer. Reset Default 0 0 Table 177. PP_PTRACCTLR1, Path Trace Access Control Register 1 (R/W) Address 0x1330 Bit 15:2 1:0 Name -- PP_J1TS1_CHSEL[1:0] Reserved. J1 Time Slot 1 Channel Select. 00 = Bytestream A. 01 = Bytestream B. 10 = Bytestream C. 11 = Bytestream D. Table 178. PP_PTRACCTLR2, Path Trace Access Control Register 2 (R/W) Address 0x1331 Bit 15:1 0 Name -- PP_J1BF_MSGSEL Reserved. J1 Buffer Message Type Select (Compare/ Received Message). 0 = Received message. 1 = Compare. Table 179. PP_PTRACCTLR3, Path Trace Access Control Register 3 (R/W) Address 0x1332 Bit 15:1 0 Name -- PP_J1BF_ACTYP Reserved. J1 Buffer Access Type (Read/ Write). 0 = Read. 1 = Write. Table 180. PP_PTRACBGR, Path Trace Access Begin (WO) Address 0x1333 Bit 15:1 0 Name -- PP_J1_ACBG Reserved. J1 Access Begin. Write to 1 to start J1 access. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 290 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 181. PP_STS12PTRCTLR[1--6], STS-12 Channel Path Trace Control Registers 1--6 (R/W) Address 0x1338 Bit 15:4 3:0 Name -- Reserved. Function Reset Default 0 1 PP_J1MSG_MSEL[A--D] J1 Message Mode Select (Validated/Provisioned) Bytestream A--D. 0 = Provisioned. 1 = Validated. 0x1339 15:4 3:0 -- PP_J1MSG_TYPSEL [A--D] Reserved. J1 Message Type Select (SDH/SONET) Bytestream A--D. SS bits monitoring (page 249) is enabled only when the J1 message type SDH is selected. When the J1 message type SONET is selected, SS bits monitoring is disabled. 0 = SONET. 1 = SDH. 0 0 0x133C, 0x133D, 0x133E, 0x133F 15:4 3:0 -- Reserved. 0 0 PP_TSSEL_J1[A--D][3:0] Time Slots 1--12 Select for J1 Accumulation Bytestream A--D. 1111 = Reserved. 1110 = Reserved. 1101 = Reserved. 1100 = STS-1 #12 time slot 12. 1011 = STS-1 #11 time slot 8. 1010 = STS-1 #10 time slot 4. 1001 = STS-1 #9 time slot 11. 1000 = STS-1 #8 time slot 7. 0111 = STS-1 #7 time slot 3. 0110 = STS-1 #6 time slot 10. 0101 = STS-1 #5 time slot 6. 0100 = STS-1 #4 time slot 2. 0011 = STS-1 #3 time slot 9. 0010 = STS-1 #2 time slot 5. 0001 = STS-1 #1 time slot 1. 0000 = Reserved. Agere Systems Inc. 291 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 182. STS-12 F2, H4, Z3, Z4, and Z5 Status (RO) Note: For registers 0x1344, 0x1348, 0x134C, and 0x1350 see Table 183. Address 0x1341 0x1342 0x1343 0x1345 0x1346 0x1347 0x1349 0x134A 0x134B 0x134D 0x134E 0x134F Bit 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function F2 Byte--Bytestream A. H4 Byte--Bytestream A. Z3 Byte--Bytestream A. Z4 Byte--Bytestream A. Reserved. Z5 Byte--Bytestream A. F2 Byte--Bytestream B. H4 Byte--Bytestream B. Z3 Byte--Bytestream B. Z4 Byte--Bytestream B. Reserved. Z5 Byte--Bytestream B. F2 Byte--Bytestream C. H4 Byte--Bytestream C. Z3 Byte--Bytestream C. Z4 Byte--Bytestream C. Reserved. Z5 Byte--Bytestream C. F2 Byte--Bytestream D. H4 Byte--Bytestream D. Z3 Byte--Bytestream D. Z4 Byte--Bytestream D. Reserved. Z5 Byte--Bytestream D. Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 292 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Monitoring the Received F2, H4, Z3, Z4, and Z5 Bytes in Terms of Individual Time Slots. First select which time slot within the slice that you want to monitor; the CNTD counter must be set. To do this, use the 0x1344 (slice A), 0x1348 (slice B), 0x134C (slice C), and 0x1350 (slice D) register. The lower 4 bits of each of these registers holds a time-slot number, in the range 1--12. The upper 12 bits of these four registers hold the CNTD counters for each of these values. The default values of zero will produce no capture of Z3, H4, etc. The appropriate CNTD counter must be written to a value with a minimum of 3, and a maximum of 15. In the following examples, all three CNTD counters are written to a value of 3. The time-slot number is the STS-1 number of the time slot, not its position. Therefore, the SONET 1, 4, 7, 10 convention is used, and a value of 1 will capture the first time slot, 4 will capture the second, etc. Three examples: 1) To monitor STS-1 # 4 in OC-48 mode. Write 0x1344 to a value of 0x3334. Wait for the number of frames required by the CNTD counters (three frames in this example). Read 0x1341, 0x1342, and/or 0x1343. Extract the value from the appropriate register (0x1341--F2/H4, 0x1342--Z3/Z4, 0x1343--Z5). 2) To monitor STS-1 # 20 in OC-48 mode. MARS2G5 P-Pro assumes each stream is 12 STS-1s, which are within an STS-12 group, i.e., stream A = STS1 #1 to STS-1 #12, stream B = STS-1 #13 to STS-1 #24, etc. STS-1 # 20 is in stream B, and it is the STS-1 number 8 in that stream. Write 0x1348 to a value of 0x3338. Wait for the number of frames required by the CNTD counters (three frames in this example). Read 0x1345, 0x1346, and/or 0x1347. Extract the value from the appropriate register (0x1345--F2/H4, 0x1346--Z3/Z4, 0x1347--Z5). 3) To monitor STS-1 # 7 on line B in quad OC-12 mode. Write 0x1348 to a value of 0x3337. Wait for the number of frames required by the CNTD counters (three frames in this example). Read 0x1345, 0x1346, and/or 0x1347. Extract the value from the appropriate register (0x1345--F2/H4, 0x1346--Z3/Z4, 0x1347--Z5). As well as waiting, there is a new validated value interrupt. If the new validated value is the same as the old value when changing time slots, this interrupt may not get set. It is recommended to wait for the three-frame duration, since this is a short time. Table 183. Path F2, H4, Z3, Z4, and Z5 Provisioning Bytestream A--D (R/W, Control) Address 0x1344, 0x1348, 0x134C, 0x1350 Bit 15:12 11:8 7:4 3:0 Name -- -- -- -- Function F2 Validated Period Bytestream A--D. H4/Z3/Z4 Validated Period Bytestream A--D. Z5 Validated Period Bytestream A--D. STS-1 Channel Select for F2/H4/Z3/Z4/Z5 Bytes Monitoring Bytestream A--D. Reset Default 0 0 0 0 Agere Systems Inc. 293 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 184. STS-12 SS Bits Status (RO) Address 0x1351 Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1352 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1353 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1354 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1355 15:12 11:10 9:8 7:6 5:4 3:2 1:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Time Slot 1 Received SS Bits--Bytestream A. Time Slot 2 Received SS Bits--Bytestream A. Time Slot 3 Received SS Bits--Bytestream A. Time Slot 4 Received SS Bits--Bytestream A. Time Slot 5 Received SS Bits--Bytestream A. Time Slot 6 Received SS Bits--Bytestream A. Reserved. Time Slot 7 Received SS Bits--Bytestream A. Time Slot 8 Received SS Bits--Bytestream A. Time Slot 9 Received SS Bits--Bytestream A. Time Slot 10 Received SS Bits--Bytestream A. Time Slot 11 Received SS Bits--Bytestream A. Time Slot 12 Received SS Bits--Bytestream A. Reserved. Time Slot 1 Received SS Bits--Bytestream B. Time Slot 2 Received SS Bits--Bytestream B. Time Slot 3 Received SS Bits--Bytestream B. Time Slot 4 Received SS Bits--Bytestream B. Time Slot 5 Received SS Bits--Bytestream B. Time Slot 6 Received SS Bits--Bytestream B. Reserved. Time Slot 7 Received SS Bits--Bytestream B. Time Slot 8 Received SS Bits--Bytestream B. Time Slot 9 Received SS Bits--Bytestream B. Time Slot 10 Received SS Bits--Bytestream B. Time Slot 11 Received SS Bits--Bytestream B. Time Slot 12 Received SS Bits--Bytestream B. Reserved. Time Slot 1 Received SS Bits--Bytestream C. Time Slot 2 Received SS Bits--Bytestream C. Time Slot 3 Received SS Bits--Bytestream C. Time Slot 4 Received SS Bits--Bytestream C. Time Slot 5 Received SS Bits--Bytestream C. Time Slot 6 Received SS Bits--Bytestream C. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 294 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 184. STS-12 SS Bits Status (RO) (continued) Address 0x1356 Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1357 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1358 15:12 11:10 9:8 7:6 5:4 3:2 1:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Time Slot 7 Received SS Bits--Bytestream C. Time Slot 8 Received SS Bits--Bytestream C. Time Slot 9 Received SS Bits--Bytestream C. Time Slot 10 Received SS Bits--Bytestream C. Time Slot 11 Received SS Bits--Bytestream C. Time Slot 12 Received SS Bits--Bytestream C. Reserved. Time Slot 1 Received SS Bits--Bytestream D. Time Slot 2 Received SS Bits--Bytestream D. Time Slot 3 Received SS Bits--Bytestream D. Time Slot 4 Received SS Bits--Bytestream D. Time Slot 5 Received SS Bits--Bytestream D. Time Slot 6 Received SS Bits--Bytestream D. Reserved. Time Slot 7 Received SS Bits--Bytestream D. Time Slot 8 Received SS Bits--Bytestream D. Time Slot 9 Received SS Bits--Bytestream D. Time Slot 10 Received SS Bits--Bytestream D. Time Slot 11 Received SS Bits--Bytestream D. Time Slot 12 Received SS Bits--Bytestream D. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. 295 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Persistency Table 185. PP_TSRDI_ALMPSBSR[A--D], Time Slots 1--12 RDI Alarm Persistency Bytestream A--D (RO) Address Bit Name -- PP_TSRDI_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 RDI Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x1382, 15:12 0x1383, 11:0 0x1384, 0x1385 Table 186. PP_TSPLM_ALMPSBSR[A--D], Time Slots 1--12 PLM Alarm Persistency Bytestream A--D (RO) Address Bit Name -- PP_TSPLM_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 Payload Label Mismatch Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x138A, 15:12 0x138B, 11:0 0x138C, 0x138D Table 187. PP_TSPUNEQ_ALMPSBSR[A--D], Time Slots 1--12 Path Unequipped Alarm Persistency Bytestream A--D (RO) Address Bit Name -- PP_TSPUNEQ_ ALMPSBS[A--D][1--12] Reserved. Time Slots 1--12 Path Unequipped Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x1392, 15:12 0x1393, 11:0 0x1394, 0x1395 296 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 188. PP_TSAIS_ALMPSBSR[A--D], Time Slots 1--12 AIS Alarm Persistency Bytestream A--D (RO) Address Bit Name -- PP_TSAIS_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 AIS Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x139A, 15:12 0x139B, 11:0 0x139C, 0x139D Table 189. PP_TSLOP_ALMPSBSR[A--D], Time Slots 1--12 LOP Alarm Persistency Bytestream A--D (RO) Address Bit Name -- PP_TSLOP_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 LOP Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x13A2, 15:12 0x13A3, 11:0 0x13A4, 0x13A5 Table 190. PP_TSPDI_ALMPSBSR[A--D], Time Slots 1--12 PDI Alarm Persistency Bytestream A--D (RO) Address Bit Name -- PP_TSPDI_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 PDI Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x13AA, 15:12 0x13AB, 11:0 0x13AC, 0x13AD Agere Systems Inc. 297 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) State Table 191. PP_TSRDI_STBSR[A--D], Time Slots 1--12 RDI State Bytestream A--D (RO) Address Bit Name -- PP_TSRDI_STBS [A--D][1--12] Reserved. Time Slots 1--12 RDI State Bytestream A--D. Function Reset Default 0 0 0x13C2, 15:12 0x13C3, 11:0 0x13C4, 0x13C5 Table 192. PP_TSPLM_STBSR[A--D], Time Slots 1--12 PLM State Bytestream A--D (RO) Address Bit Name -- PP_TSPLM_STBS [A--D][1--12] Reserved. Time Slots 1--12 Payload Label Mismatch State Bytestream A--D. Function Reset Default 0 0 0x13CA, 15:12 0x13CB, 11:0 0x13CC, 0x13CD Table 193. PP_TSPUNEQ_STBSR[A--D], Time Slots 1--12 Path Unequipped State Bytestream A--D (RO) Address Bit Name -- PP_TSRDI_STBS [A--D][1--12] Reserved. Time Slots 1--12 Path Unequipped State Bytestream A--D. Function Reset Default 0 0 0x13D2, 15:12 0x13D3, 11:0 0x13D4, 0x13D5 298 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 194. PP_TSAIS_STBSR[A--D], Time Slots 1--12 AIS State Bytestream A--D (RO) Address Bit Name -- PP_TSAIS_STBS [A--D][1--12] Reserved. Time Slots 1--12 AIS State Bytestream A--D. Function Reset Default 0 0 0x13DA, 15:12 0x13DB, 11:0 0x13DC, 0x13DD Table 195. PP_TSLOP_STBSR[A--D], Time Slots 1--12 LOP State Bytestream A--D (RO) Address Bit Name -- PP_TSLOP_STBS [A--D][1--12] Reserved. Time Slots 1--12 LOP State Bytestream A--D. Function Reset Default 0 0 0x13E2, 15:12 0x13E3, 11:0 0x13E4, 0x13E5 Table 196. PP_TSPDI_STBSR[A--D], Time Slots 1--12 PDI State Bytestream A--D (RO) Address Bit Name -- PP_TSPDI_STBS [A--D][1--12] Reserved. Time Slots 1--12 PDI State Bytestream A--D. Function Reset Default 0 0 0x13EA, 15:12 0x13EB, 11:0 0x13EC, 0x13ED Agere Systems Inc. 299 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Signal Fail Table 197. PP_SFWSZ_SELR[1--2], Signal Fail Window Size Select Registers 1--2 (R/W, Control) Address 0x1400 Bit 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Name PP_SFWSZ_SELSET [0--7][1:0] Function Window Size Select Set Threshold 0--7. 00 = Window size 0. 01 = Window size 1. 10 = Window size 2. 11 = Window size 3. Reset Default 1 2 1 2 1 2 1 2 2 3 2 3 2 3 2 3 0x1401 PP_SFWSZ_SELCLR [0--7][1:0] Window Size Select Clear Threshold 0--7. 00 = Window size 0. 01 = Window size 1. 10 = Window size 2. 11 = Window size 3. 300 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 198. PP_SFDR[0--7], Signal Fail Detect Threshold Registers 0--7 (R/W, Control) Address 0x1410 Bit 15:9 8:0 Name -- PP_SFD0[8:0] Reserved. STS-1 Signal Fail Detect Threshold 0. Number of bit/block errors within detection window required to trigger a signal fail. 0x1411 0x1412 0x1413 0x1414 0x1415 0x1416 0x1417 15:9 8:0 15:14 13:0 15:14 13:0 15:14 13:0 15:14 13:0 15:14 13:0 15:14 13:0 -- PP_SFD1[8:0] -- PP_SFD2[13:0] -- PP_SFD3[13:0] -- PP_SFD4[13:0] -- PP_SFD5[13:0] -- PP_SFD6[13:0] -- PP_SFD7[13:0] Reserved. STS-1 Signal Fail Detect Threshold 1. Reserved. STS-Nc Signal Fail Detect Threshold 2. Reserved. STS-Nc Signal Fail Detect Threshold 3. Reserved. STS-Nc Signal Fail Detect Threshold 4. Reserved. STS-Nc Signal Fail Detect Threshold 5. Reserved. STS-Nc Signal Fail Detect Threshold 6. Reserved. STS-Nc Signal Fail Detect Threshold 7. 0 0x0DE 0 0x0233 0 0x02B2 0 0x3A3 0 0x055E 0 0x51D 0 0x0A62 Function Reset Default 0 0x0CF Agere Systems Inc. 301 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 199. PP_SFCLRR[0--7], Signal Fail Clear Threshold Registers 0--7 (R/W, Control) Address 0x1418 Bit 15:9 8:0 Name -- PP_SFCLR0[8:0] Reserved. STS-1 Signal Fail Clear Threshold 0. Number of bit/block errors within detection window permitted when clearing a signal fail. 0x1419 15:9 8:0 0x141A 15:14 13:0 0x141B 15:14 13:0 0x141C 15:14 13:0 0x141D 15:14 13:0 0x141E 15:14 13:0 0x141F 15:14 13:0 -- PP_SFCLR1[8:0] -- PP_SFCLR2[13:0] -- PP_SFCLR3[13:0] -- PP_SFCLR4[13:0] -- PP_SFCLR5[13:0] -- PP_SFCLR6[13:0] -- PP_SFCLR7[13:0] Reserved. STS-1 Signal Fail Clear Threshold 1. Reserved. STS-Nc Signal Fail Clear Threshold 2. Reserved. STS-Nc Signal Fail Clear Threshold 3. Reserved. STS-Nc Signal Fail Clear Threshold 4. Reserved. STS-Nc Signal Fail Clear Threshold 5. Reserved. STS-Nc Signal Fail Clear Threshold 6. Reserved. STS-Nc Signal Fail Clear Threshold 7. 0 0x115 0 0x030B 0 0x031B 0 0x5D8 0 0x0618 0 0x0B08 0 0x0BFC Function Reset Default 0 0x113 Table 200. PP_SFWSZR[0--3], Signal Fail Window Size 0/1/2/3 Registers (R/W, Control) Address 0x1420 Bit 15:0 Name PP_SFWSZ0[15:0] Function Signal Fail Window Size 0 (in 0.5 ms Increments). A setting of zero is the same as 1; will produce a 0.5 ms window size. Signal Fail Window Size 1 (in 0.5 ms Increments). A setting of zero is the same as 1; will produce a 0.5 ms window size. Signal Fail Window Size 2 (in 0.5 ms Increments). A setting of zero is the same as 1; will produce a 0.5 ms window size. Signal Fail Window Size 3 (in 0.5 ms Increments). A setting of zero is the same as 1; will produce a 0.5 ms window size. Reset Default 0x000A 0x1430 15:0 PP_SFWSZ1[15:0] 0x0064 0x1440 15:0 PP_SFWSZ2[15:0] 0x03E8 0x1450 15:0 PP_SFWSZ3[15:0] 0x2710 Signal Fail Window Size Registers: Above are the settings for the length of the four free-running windows that are used in conjunction with the set and clear thresholds for the signal fail detection. This time unit depends on the number of columns in a frame setting. The time unit is four times an STS-frame size, which is 0.5 ms for a system setting of 90 columns. After changing one of these window registers, it will take two time unit pules to occur before this new value is used, i.e., the old window will come to a halt and the new one will begin from 0.5 ms to 1 ms (assuming 90 columns). 302 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Concatenation The expected concatenation map register is programmed via programmable registers (Table 201) on a per timeslot (STS-1) basis. The concatenation state of each time slot can be read from the received concatenation map register (PP_RCNCTM_TSBSR[A--D], Received Concatenation Map Time Slots 1--12 in Bytestream A--D (RO), Table 203). Comparison of the expected and received concatenation state is enabled on a per time-slot basis by software setting of the concatenation compare enable register (PP_CNCTCPREN_TSBSR[A--D], Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D (R/W), Table 202). Alarms are binned on a per bytestream (STS-12) basis in the concatenation map mismatch register (PP_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW), Table 113), and resulting interrupts can be masked by the concatenation map mismatch mask register (see PP_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A--D (R/W), Table 152) mismatches in the first time slot of a bytestream are special cases. When the expected state of a bytestream is concatenation and the received state is normal, the mismatch status bit for the previous bytestream will be set since the errored time slot is trying to concatenate to an STS-1 in the previous bytestream. Table 201. PP_ECNCTM_TSBSR[A--D], Expected Concatenation Map Time Slots 1--12 in Bytestream A--D (R/W) Address Bit Name -- PP_ECNCT_STTSBS [A--D][1--12] Reserved. Expected Concatenation State for Time Slots 1--12 in Bytestream A--D. 0 = Time slot not expected to be in concatenation. 1 = Time slot expected to be in concatenation. Function Reset Default 0 0 0x1502, 15:12 0x1503, 11:0 0x1504, 0x1505 Table 202. PP_CNCTCPREN_TSBSR[A--D], Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D (R/W) Address Bit Name -- PP_CNCTCPREN_ TSBS[A--D][1--12] Reserved. Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D. 0 = Inhibit comparison of received and expected concatenation states. 1 = Compare received and expected concatenation states. Function Reset Default 0 0 0x1507, 15:12 0x1508, 11:0 0x1509, 0x150A Table 203. PP_RCNCTM_TSBSR[A--D], Received Concatenation Map Time Slots 1--12 in Bytestream A--D (RO) Address Bit Name -- PP_RCNCT_STTSBS [A--D][1--12] Reserved. Received Concatenation State for Time Slots 1--12 in Bytestream A--D. 0 = Concatenation state not detected. 1 = Concatenation state detected. Agere Systems Inc. 303 Function Reset Default 0 0 0x1512, 15:12 0x1513, 11:0 0x1514, 0x1515 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) AIS Insert Control Table 204. PP_SWAIS_ISRTR, Software AIS Insert (R/W) Address Bit Name -- PP_SWAIS_ISRT [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 STS AIS Insert Bytestream A--D. 0 = No AIS insert. 1 = AIS insert. Pointer Processor Control Table 205. PP_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W) Address 0x1580 Bit 15:4 3:0 Name -- PP_PINCDEC[A--D] Reserved. Pointer Increment/Decrement Rules to Use (SONET/ SDH) Bytestream A--D. Function Reset Default -- 1111 Function Reset Default 0 0 0x1542, 15:12 0x1543, 11:0 0x1544, 0x1545 Table 206. PP_TSSS_ISRTBSR[A--D], Time Slot 1--Time Slot 12 SS Bits Insert Bytestream A--D (R/W) Address Bit Name -- PP_TSSS_ISRTBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 SS Bits Insert Bytestream A--D. 0 = Pass through. 1 = Insert. Table 207. PP_TSE1F1_ISRTBSR[A--D], Time Slot 1--Time Slot 12 E1/F1 Insert Bytestream A--D (R/W) Address Bit Name -- PP_TSE1F1_ISRTBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 E1/F1 Insert Bytestream A--D. 0 = Path status byte. 1 = Insert. Function Reset Default -- 0 Function Reset Default -- 0 0x1582, 15:12 0x1583, 11:0 0x1584, 0x1585 0x1587, 15:12 0x1588, 11:0 0x1589, 0x158A 304 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 208. PP_E2_ISRTCTLR[A--D], E2 Insert Control Bytestream A--D (R/W) Address 0x158C, 0x158D, 0x158E, 0x158F Bit 15:1 0 Name -- PP_E2_ISRTCTL[A--D] Reserved. E2 Insert Control Bytestream A--D. 0 = Line status byte. 1 = Software insert. Function Reset Default -- 0 Table 209. PP_TS_INCDECBNR[A--D], Time Slots 1--12 Increment/Decrement Binning Select Bytestream A--D (R/W) Address 0x1590, 0x1591, 0x1592, 0x1593 Bit 15:4 3:0 Name -- PP_TS_INCDECBN [A--D][3:0] Reserved. Time Slots 1--12 Increment/Decrement Binning Select Bytestream A--D. 1111 = None selected counter disabled (see note below). 1110 = None selected counter disabled (see note below). 1101 = None selected counter disabled (see note below). 1100 = STS-1 #12 time slot 12. 1011 = STS-1 #11 time slot 8. 1010 = STS-1 #10 time slot 4. 1001 = STS-1 #9 time slot 11. 1000 = STS-1 #8 time slot 7. 0111 = STS-1 #7 time slot 3. 0110 = STS-1 #6 time slot 10. 0101 = STS-1 #5 time slot 6. 0100 = STS-1 #4 time slot 2. 0011 = STS-1 #3 time slot 9. 0010 = STS-1 #2 time slot 5. 0001 = STS-1 #1 time slot 1. 0000 = None selected counter disabled (see note below). Note:Selecting 0, 13, 14, 15 will cause the increment/ decrement counter to remain at its last count until the next PM 1-second pulse when it will clear and remain at 0 thereafter. Table 210. PP_AISONTIM_ISRTR[A--D], STS-12 Pointer Processor Control (R/W) Address Bit Name -- PP_AISONTIM_ISRT [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 TIM Insert Bytestream A--D. 0 = No TIM insert. 1 = TIM insert. Function Reset Default 0 0 Function Reset Default -- 0000 (Disabl ed) 0x1594, 15:12 0x1595, 11:0 0x1596, 0x1597 Agere Systems Inc. 305 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 211. PP_TSPDIVLD_CTLBSR[A--D], Time Slot 1--Time Slot 12 PDI Validate Control Bytestream A--D (R/W) Address Bit Name Function Reset Default Note: There are four PM increment/decrement counters; increment and decrement for both the interpreter and generator for each STS-12 group. For a concatenation spanning STS-12 blocks, the select should be set to the head of the concatenation. It is suggested for clarity that counters not being used be disabled by setting them to 0; for example, in an STS-48C, bytestream A increment/decrement binning select should be set to STS-1 #1 and the selects for streams B, C, and D should be set to 0. The increments and decrements for the entire concatenation should then be read from the stream A registers. 0x15A2, 15:12 0x15A3, 11:0 0x15A4, 0x15A5 -- PP_TSPDIVLD_CTLBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 PDI Validate Control Bytestream A--D. 0 = Disables PDI codes. 1 = Enables PDI codes to affect path status byte. Provisioning Table 212. PP_EXPC2_PVSNR[1--24], Expected C2 Byte Provisioning (R/W) Address 0x1600 -- 0x1617 Bit 15:8 7:0 Name PP_EXPC2 [1, 3, 5, . . . , 47][7:0] PP_EXPC2 [2, 4, 6, . . . , 48][7:0] Function Time Slot 1, 3, 5, 7, 9, . . ., 47 Expected C2 Byte. Time Slot 2, 4, 6, 8, 10, . . ., 48 Expected C2 Byte. Reset Default 0 0 -- 0 Note: The expected C2 byte is only a programming mode and changing them does not affect the validation counters. Table 213. PP_TSCBB_ERRBSR[A--D], Time Slot 1--Time Slot 12 Count Block/Bit Errors Bytestream A--D Address Bit Name -- PP_TSCBB_ERRBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Count Block/Bit Errors Bytestream A--D. Function Reset Default -- 0 0x1618, 15:12 0x1619, 11:0 0x161A, 0x161B 306 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 214. PP_TS1_6_SSBSRA, PP_TS7_12_SSBSRA, Time Slots 1--12 SS Bits Insertion Value Bytestream A (R/W) Address 0x1620 Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1621 15:12 11:10 9:8 7:6 5:4 3:2 1:0 Name -- PP_TS_SSA1 PP_TS_SSA2 PP_TS_SSA3 PP_TS_SSA4 PP_TS_SSA5 PP_TS_SSA6 -- PP_TS_SSA7 PP_TS_SSA8 PP_TS_SSA9 PP_TS_SSA10 PP_TS_SSA11 PP_TS_SSA12 Reserved. Time Slot 1 SS Bits Setting--Stream A. Time Slot 2 SS Bits Setting--Stream A. Time Slot 3 SS Bits Setting--Stream A. Time Slot 4 SS Bits Setting--Stream A. Time Slot 5 SS Bits Setting--Stream A. Time Slot 6 SS Bits Setting--Stream A. Reserved. Time Slot 7 SS Bits Setting--Stream A. Time Slot 8 SS Bits Setting--Stream A. Time Slot 9 SS Bits Setting--Stream A. Time Slot 10 SS Bits Setting--Stream A. Time Slot 11 SS Bits Setting--Stream A. Time Slot 12 SS Bits Setting--Stream A. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 215. PP_TS1_6_SSBSRB, PP_TS7_12_SSBSRB, Time Slots 1--12 SS Bits Insertion Value Bytestream B (R/W) Address 0x1622 Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1623 15:12 11:10 9:8 7:6 5:4 3:2 1:0 Name -- PP_TS_SSB1 PP_TS_SSB2 PP_TS_SSB3 PP_TS_SSB4 PP_TS_SSB5 PP_TS_SSB6 -- PP_TS_SSB7 PP_TS_SSB8 PP_TS_SSB9 PP_TS_SSB10 PP_TS_SSB11 PP_TS_SSB12 Reserved. Time Slot 1 SS Bits Setting--Stream B. Time Slot 2 SS Bits Setting--Stream B. Time Slot 3 SS Bits Setting--Stream B. Time Slot 4 SS Bits Setting--Stream B. Time Slot 5 SS Bits Setting--Stream B. Time Slot 6 SS Bits Setting--Stream B. Reserved. Time Slot 7 SS Bits Setting--Stream B. Time Slot 8 SS Bits Setting--Stream B. Time Slot 9 SS Bits Setting--Stream B. Time Slot 10 SS Bits Setting--Stream B. Time Slot 11 SS Bits Setting--Stream B. Time Slot 12 SS Bits Setting--Stream B. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. 307 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 216. PP_TS1_6_SSBSRC, PP_TS7_12_SSBSRC, Time Slots 1--12 SS Bits Insertion Value Bytestream C (R/W) Address 0x1624 Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1625 15:12 11:10 9:8 7:6 5:4 3:2 1:0 Name -- PP_TS_SSC1 PP_TS_SSC2 PP_TS_SSC3 PP_TS_SSC4 PP_TS_SSC5 PP_TS_SSC6 -- PP_TS_SSC7 PP_TS_SSC8 PP_TS_SSC9 PP_TS_SSC10 PP_TS_SSC11 PP_TS_SSC12 Reserved. Time Slot 1 SS Bits Setting--Stream C. Time Slot 2 SS Bits Setting--Stream C. Time Slot 3 SS Bits Setting--Stream C. Time Slot 4 SS Bits Setting--Stream C. Time Slot 5 SS Bits Setting--Stream C. Time Slot 6 SS Bits Setting--Stream C. Reserved. Time Slot 7 SS Bits Setting--Stream C. Time Slot 8 SS Bits Setting--Stream C. Time Slot 9 SS Bits Setting--Stream C. Time Slot 10 SS Bits Setting--Stream C. Time Slot 11 SS Bits Setting--Stream C. Time Slot 12 SS Bits Setting--Stream C. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 217. PP_TS1_6_SSBSRD, PP_TS7_12_SSBSRD, Time Slots 1--12 SS Bits Insertion Value Bytestream D (R/W) Address 0x1626 Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0 0x1627 15:12 11:10 9:8 7:6 5:4 3:2 1:0 Name -- PP_TS_SSD1 PP_TS_SSD2 PP_TS_SSD3 PP_TS_SSD4 PP_TS_SSD5 PP_TS_SSD6 -- PP_TS_SSD7 PP_TS_SSD8 PP_TS_SSD9 PP_TS_SSD10 PP_TS_SSD11 PP_TS_SSD12 Reserved. Time Slot 1 SS Bits Setting--Stream D. Time Slot 2 SS Bits Setting--Stream D. Time Slot 3 SS Bits Setting--Stream D. Time Slot 4 SS Bits Setting--Stream D. Time Slot 5 SS Bits Setting--Stream D. Time Slot 6 SS Bits Setting--Stream D. Reserved. Time Slot 7 SS Bits Setting--Stream D. Time Slot 8 SS Bits Setting--Stream D. Time Slot 9 SS Bits Setting--Stream D. Time Slot 10 SS Bits Setting--Stream D. Time Slot 11 SS Bits Setting--Stream D. Time Slot 12 SS Bits Setting--Stream D. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 308 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 218. SS Bits Provisioning (R/W) Address 0x1629 Bit 15:4 3:0 Name -- -- Function -- SS Bits Monitoring Mode Bytestream A--D. 0 = Compare mode. 1 = Validation mode. Table 219. SS Bits Validation/Compare Period (R/W) Address 0x162A Bit 15:4 3:0 Name -- -- -- SS Bits Validation/Compare Period Bytestream A--D. Function Reset Default -- 0x5 Reset Default -- -- Table 220. Elastic Store Decrement and Increment (R/W) Address 0x162C Bit 15:8 7:0 Name PP_ES_DEC_MAX[7:0] PP_ES_INC_MIN[7:0] Function Elastic Store Decrement Region Maximum. Must be set to 0x03. Elastic Store Increment Region Minimum. Must be set to 0xC3. Reset Default 0x03 0xA4 Table 221. Elastic Store Overflow Region (R/W) Address 0x162D Bit 15:8 7:0 Name PP_ES_OVR_MAX[7:0] PP_ES_OVR_MIN[7:0] Function Elastic Store Overflow Region Maximum. Elastic Store Increment Region Minimum. Reset Default 0x03 0x66 Table 222. PP_TS_E1F1ISRTR[1--24], Time Slots 1--48 E1/F1 Insert Address 0x1650 -- 0x1667 Bit 15:8 7:0 Name PP_TS_E1F1ISRT [1, 3, 5, . . ., 47] PP_TS_E1F1ISRT [2, 4, 6, . . ., 48] Function Time Slot 1--Time Slot 47 E1/F1 Insert Byte. Time Slot 2--Time Slot 48 E1/F1 Insert Byte. Reset Default 0 0 Table 223. PP_E2_ISRTBSR[A--D], E2 Byte Insert Bytestream A--D Address 0x1668, 0x1669, 0x166A, 0x166B Bit 15:8 7:0 Name -- PP_E2_ISRTBS [A--D][7:0] Reserved. E2 Byte Insert Bytestream A--D. Function Reset Default 0 0 Agere Systems Inc. 309 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Maintenance Table 224. PP_TSMNTR[1--48], Time Slots 1--48 Maintenance (R/W) Address 0x1690 -- 0x16BF Bit 15:3 2:0 Name -- Reserved. Function Reset Default 0 0 PP_TSSF_TH[1--48][2:0] Time Slot 1--Time Slot 48 Signal Fail Threshold Select. This value sets the signal fail threshold for the respective time slot. Interpreter Increment/Decrement PM Table 225. PP_PI_LSECINCR[A--D], Pointer Interpreter Last Second Increments Bytestream A--D (RO) Address Bit Name -- PP_PI_LSECINC [A--D][10:0] Reserved. Last Second Increments in Pointer Interpreter Bytestream A--D. Function Reset Default 0 0 0x1702, 15:11 0x1703, 10:0 0x1704, 0x1705 Table 226. PP_PI_LSECDECR[A--D], Pointer Interpreter Last Second Decrements Bytestream A--D (RO) Address Bit Name -- PP_PI_LSECDEC [A--D][10:0] Reserved. Last Second Decrements in Pointer Interpreter Bytestream A--D. Function Reset Default 0 0 0x1712, 15:11 0x1713, 10:0 0x1714, 0x1715 Generator Increment/Decrement PM Table 227. PP_PG_LSECINCR[A--D], Pointer Generator Last Second Increments Bytestream A--D (RO) Address Bit Name -- PP_PG_LSECINCR [A--D][10:0] Reserved. Last Second Increments in Pointer Generator Bytestream A--D. Function Reset Default 0 0 0x1742, 15:11 0x1743, 10:0 0x1744, 0x1745 Table 228. PP_PG_LSECDECR[A--D], Pointer Generator Last Second Decrements Bytestream A--D (RO) Address Bit Name -- PP_PG_LSECDECR [A--D][10:0] Reserved. Last Second Decrements in Pointer Generator Bytestream A--D. Function Reset Default 0 0 0x1752, 15:11 0x1753, 10:0 0x1754, 0x1755 310 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Performance Monitoring Table 229. PP_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO) Address 0x1780 Bit 15:7 6 Name -- PP_1BRDI_DPM Reserved. One-Bit RDI Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 5 PP_ERDI_PDPM ERDI Payload Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 4 PP_ERDI_CDPM ERDI Connectivity Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 3 PP_ERDI_SDPM ERDI Server Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 2 PP_UNEQR_ALMPM Unequipped Received Alarm PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 1 PP_AIS_ALMPM Alarm Indicator Signal Alarm PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 PP_LOP_ALMPM Loss of Pointer Alarm PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 0 0 0 0 0 Function Reset Default 0 0 Agere Systems Inc. 311 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 230. PP_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A--D (RO) Address 0x1781 Bit 15:4 3:0 Name -- PP_1BRDI_DPMBS [A--D] Reserved. One-Bit RDI Defect PM Bytestream A--D. 0 = One-bit RDI defect PM has not been detected for any STS-1s in bytestream A--D. 1 = One-bit RDI defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 231. PP_TS1BRDI_DPMBSR[A--D], Path Overhead Time Slots 1--12 One-Bit RDI Defect PM Bytestream A--D (RO) Address Bit Name -- PP_TS1BRDI_DPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 One-Bit RDI Defect PM Bytestream A--D. Function Reset Default 0 0 0x1782, 15:12 0x1783, 11:0 0x1784, 0x1785 Table 232. PP_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A--D (RO) Address 0x1791 Bit 15:4 3:0 Name -- PP_ERDI_PDPMBS [A--D] Reserved. ERDI Payload Defect PM Bytestream A--D. 0 = ERDI payload defect PM has not been detected for any STS-1s in bytestream A--D. 1 = ERDI payload defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 233. PP_TSERDI_PDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Payload Defect PM Bytestream A--D (RO) Address Bit Name -- PP_TSERDI_PDPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 ERDI Payload Defect PM Bytestream A--D. Function Reset Default 0 0 0x1792, 15:12 0x1793, 11:0 0x1794, 0x1795 312 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 234. PP_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A--D (RO) Address 0x17A1 Bit 15:4 3:0 Name -- PP_ERDI_CDPMBS [A--D] Reserved. ERDI Connectivity Defect PM Bytestream A--D. 0 = ERDI connectivity defect PM has not been detected for any STS-1s in bytestream A--D. 1 = ERDI connectivity defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 235. PP_TSERDI_CDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Connectivity Defect PM Bytestream A--D (RO) Address Bit Name -- PP_TSERDI_CDPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 ERDI Connectivity Defect PM Bytestream A--D. Function Reset Default 0 0 0x17A2, 15:12 0x17A3, 11:0 0x17A4, 0x17A5 Table 236. PP_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A--D (RO) Address 0x17B1 Bit 15:4 3:0 Name -- PP_ERDI_SDPMBS [A--D] Reserved. ERDI Server Defect PM Bytestream A--D. 0 = ERDI server defect PM has not been detected for any STS-1s in bytestream A--D. 1 = ERDI server defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 237. PP_TSERDI_SDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Server Defect PM Bytestream A--D (RO) Address Bit Name -- PP_TSERDI_SDPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 ERDI Server Defect PM Bytestream A--D. Function Reset Default 0 0 0x17B2 15:12 0x17B3 11:0 0x17B4 0x17B5 Agere Systems Inc. 313 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 238. PP_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A--D (RO) Address 0x17C1 Bit 15:4 3:0 Name -- Reserved. 0 = Unequipped received PM has not been detected for any STS-1s in bytestream A--D. 1 = Unequipped received PM has been detected for one or more STS-1s in bytestream A--D. Table 239. PP_TSUNEQR_PMBSR[A--D], Path Overhead Time Slots 1--12 Unequipped Received PM Bytestream A--D (RO) Address Bit Name -- PP_TSUNEQR_PMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Unequipped Received PM Bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 PP_UNEQR_PMBS[A--D] Unequipped Received PM Bytestream A--D. 0x17C2 15:12 0x17C3 11:0 0x17C4 0x17C5 Table 240. PP_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A--D (RO) Address 0x17D1 Bit 15:4 3:0 Name -- PP_AIS_PMBS[A--D] Reserved. Alarm Indicator Signal PM Bytestream A--D. 0 = Alarm indicator signal PM has not been detected for any STS-1s in bytestream A--D. 1 = Alarm indicator signal PM has been detected for one or more STS-1s in bytestream A--D. Table 241. PP_TSAIS_PMBSR[A--D], Path Overhead Time Slots 1--12 Alarm Indicator Signal PM Bytestream A--D (RO) Address Bit Name -- PP_TSAIS_PMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarm Indicator Signal PM Bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x17D2 15:12 0x17D3 11:0 0x17D4 0x17D5 314 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Descriptions (continued) Table 242. PP_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A--D (RO) Address 0x17E1 Bit 15:4 3:0 Name -- PP_LOP_PMBSR[A--D] Reserved. Loss of Pointer PM Bytestream A--D. 0 = Loss of pointer PM has not been detected for any STS-1s in bytestream A--D. 1 = Loss of pointer PM has been detected for one or more STS-1s in bytestream A--D. Table 243. PP_TSLOP_PMBSR[A--D], Path Overhead Time Slots 1--12 Loss of Pointer PM Bytestream A--D (RO) Address Bit Name -- PP_TSLOP_PMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer PM Bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x17E2, 15:12 0x17E3, 11:0 0x17E4, 0x17E5 Table 244. PP_LSECCVP_CPMR[1--48], Last Second CV-P Count Time Slot 1--Time Slot 48 PM (RO) Address 0x1800 -- 0x182F Bit 15:0 Name PP_LSECCVP_CPM [1--48][15:0] Function Time Slot 1--Time Slot 48 CV Count PM. Reset Default 0 Table 245. PP_LSECREIP_CPMR[1--48], Last Second REI-P Count Time Slot 1--Time Slot 48 PM (RO) Address 0x1880 -- 0x18AF Bit 15:0 Name PP_LSECREIP_CPM [1--48][15:0] Function Time Slot 1--Time Slot 48 REI Count PM. Reset Default 0 Agere Systems Inc. 315 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Descriptions (continued) RDI, C2, and PDI Status Table 246. PP_TSRDIPR[1--48], Time Slots 1--48 Path RDI Status (RO) Address 0x1900 -- 0x192F Bit 15:3 2:0 Name -- Reserved. Function Reset Default 0 0 PP_TS_RRDI[1--48][2:0] Time Slot 1--Time Slot 48 Received RDI Code. Table 247. PP_TSC2R[1--24], Time Slots 1--48 Path C2 Status (RO) Address 0x1930 -- 0x1947 Bit 15:8 7:0 Name PP_TSRC2 [1, 3, . . ., 47][7:0] PP_TSRC2 [2, 4, . . ., 48][7:0] Function Time Slot 1, 3, 5, 7, . . ., 47 Received C2 Byte. Time Slot 2, 4, 6, 8, . . ., 48 Received C2 Byte. Reset Default 0 0 Table 248. PP_TSPDIR[1--24], Time Slots 1--48 Path PDI Status (RO) Address 0x1960 -- 0x1977 Bit 15:8 7:0 Name PP_TSRPDI [1, 3, . . ., 47][7:0] PP_TSRPDI [2, 4, . . ., 48][7:0] Function Time Slot 1, 3, 5, 7, . . ., 47 Received PDI Byte. Time Slot 2, 4, 6, 8, . . ., 48 Received PDI Byte. Reset Default 0 0 316 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map Table 249. Pointer Processor Register Map Note: Shading denotes reserved bits. Addr 0x1000 0x1001 0x1002 -- 0x100E 0x100F Symbol PP_IDR PP_CORWR -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Version Control (RO) PP_ID[15:0] PP_ CORW Interrupts PP_POH_ALMBNR1 -- -- -- -- -- -- -- PP_PDI_A LMDBN PP_ UNEQR_ ALMBN PP_PDI_A LMBN PP_AIS_ ALMBN PP_ J1ACCMP _ALMBN PP_LOP_ ALMBN 0x1010 PP_POH_ALMBNR2 PP_RDI_A LMDBN PP_PLM_ ALMDBN PP_ UNEQR_ ALMDBN PP_AIS_A LMDBN PP_LOP_ ALMDBN PP_J1MM _ALMBN PP_J1VLD PP_ _ALMBN USCNCT_ ALMBN PP_ CNCTMM _ALMBN PP_ES_ ALMBN PP_SF_ ALMBN PP_RDI_ ALMBN PP_PLM_ ALMBN 0x1011 -- 0x1020 0x1021 0x1022 0x1023 0x1024 0x1025 0x1026 -- 0x1030 0x1031 0x1032 0x1033 0x1034 0x1035 0x1036 -- 0x1040 -- PP_ES_ALMBNBSR PP_TSES_ALMBSRA PP_TSES_ALMBSRB PP_TSES_ALMBSRC PP_TSES_ALMBSRD -- Elastic Store Overrun/Underrun Alarm Binning PP_ES_ALMBNBS[A--D] Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream A PP_TSES_ALMBSA[1--12] Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream B PP_TSES_ALMBSB[1--12] Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream C PP_TSES_ALMBSC[1--12] Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream D PP_TSES_ALMBSD[1--12] PP_SF_ALMBNBSR PP_TSSF_ALMBSRA PP_TSSF_ALMBSRB PP_TSSF_ALMBSRC PP_TSSF_ALMBSRD -- Signal Fail Alarm per STS-1 Bytestream A PP_TSSF_ALMBSA[1--12] Signal Fail Alarm per STS-1 Bytestream B PP_TSSF_ALMBSB[1--12] Signal Fail Alarm per STS-1 Bytestream C PP_TSSF_ALMBSC[1--12] Signal FAil Alarm per STS-1 Bytestream D PP_TSSF_ALMBSD[1--12] Signal Fail Binning PP_SF_ALMBNBS[A--D] Agere Systems Inc. 317 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1041 0x1042 0x1043 0x1044 0x1045 0x1046 -- 0x1050 0x1051 0x1052 0x1053 0x1054 0x1055 0x1056 -- 0x1060 0x1061 0x1062 0x1063 0x1064 0x1065 0x1066 -- 0x1070 Symbol PP_RDI_ALMBNBSR PP_TSRDI_ALMBSRA PP_TSRDI_ALMBSRB PP_TSRDI_ALMBSRC PP_TSRDI_ALMBSRD -- Remote Defect Indicator Alarm per STS-1 Bytestream A PP_TSRDI_ALMBSA[1--12] Remote Defect Indicator Alarm per STS-1 Bytestream B PP_TSRDI_ALMBSB[1--12] Remote Defect Indicator Alarm per STS-1 Bytestream C PP_TSRDI_ALMBSC[1--12] Remote Defect Indicator Alarm per STS-1 Bytestream D PP_TSRDI_ALMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remote Defect Indicator Alarm Binning PP_RDI_ALMBNBS[A--D] PP_PLM_ALMBNBSR PP_TSPLM_ALMBSRA PP_TSPLM_ALMBSRB PP_TSPLM_ALMBSRC PP_TSPLM_ALMBSRD -- Payload Label Mismatch Alarm per STS-1 Bytestream A PP_TSPLM_ALMBSA[1--12] Payload Label Mismatch Alarm per STS-1 Bytestream B PP_TSPLM_ALMBSB[1--12] Payload Label Mismatch Alarm per STS-1 Bytestream C PP_TSPLM_ALMBSC[1--12] Payload Label Mismatch Alarm per STS-1 Bytestream D PP_TSPLM_ALMBSD[1--12] Payload Label Mismatch Alarm Binning PP_PLM_ALMBNBS[A--D] PP_UNEQR_ALMBNBSR PP_TSUNEQR_ALMBSRA PP_TSUNEQR_ALMBSRB PP_TSUNEQR_ALMBSRC PP_TSUNEQR_ALMBSRD -- Unequipped Received Alarm per STS-1 Bytestream A PP_TSUNEQR_ALMBSA[1--12] Unequipped Received Alarm per STS-1 Bytestream B PP_TSUNEQR_ALMBSB[1--12] Unequipped Received Alarm per STS-1 Bytestream C PP_TSUNEQR_ALMBSC[1--12] Unequipped Received Alarm per STS-1 Bytestream D PP_TSUNEQR_ALMBSD[1--12] Unequipped Received Alarm Binning PP_UNEQR_ALMBNBS[A--D) 318 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1071 0x1072 0x1073 0x1074 0x1075 0x1076 -- 0x1080 0x1081 0x1082 0x1083 0x1084 0x1085 0x1086 -- 0x1090 0x1091 0x1092 -- 0x10A0 0x10A1 0x10A2 -- 0x10C0 0x10C1 0x10C2 -- 0x10D0 Symbol PP_AIS_ALMBNBSR PP_TSAIS_ALMBSRA PP_TSAIS_ALMBSRB PP_TSAIS_ALMBSRC PP_TSAIS_ALMBSRD -- Alarm Indicator Signal Alarm per STS-1 Bytestream A PP_TSAIS_ALMBSA[1--12] Alarm Indicator Signal Alarm per STS-1 Bytestream B PP_TSAIS_ALMBSB[1--12] Alarm Indicator Signal Alarm per STS-1 Bytestream C PP_TSAIS_ALMBSC[1--12] Alarm Indicator Signal Alarm per STS-1 Bytestream D PP_TSAIS_ALMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Alarm Indicator Signal Alarm Binning PP_AIS_ALMBNBS[A--D] PP_LOP_ALMBNBSR PP_TSLOP_ALMBSRA PP_TSLOP_ALMBSRB PP_TSLOP_ALMBSRC PP_TSLOP_ALMBSRD -- Loss of Pointer Alarm per STS-1 Bytestream A PP_TSLOP_ALMBSA[1--12] Loss of Pointer Alarm per STS-1 Bytestream B PP_TSLOP_ALMBSB[1--12] Loss of Pointer Alarm per STS-1 Bytestream C PP_TSLOP_ALMBSC[1--12] Loss of Pointer Alarm per STS-1 Bytestream D PP_TSLOP_ALMBSD[1--12] Loss of Pointer Alarm Binning PP_LOP_ALMBNBS[A--D] PP_CNCTMM_ALMBNBSR -- Concatenation Map Mismatch Alarm Binning PP_CNCTMM_ALMBNBS[A--D] PP_USCNCTM_ALMBNBSR -- Unsupported Concatenation Map Alarm Binning PP_USCNCTM_ALMBNBS[A--D] PP_J1NVLDMSG_ALMBNBSR -- J1 New Validated Message Alarm Binning PP_J1NVLDMSG_ALMBNBS[A--D] Agere Systems Inc. 319 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x10D1 0x10D2 -- 0x1100 0x1101 0x1102 0x1103 0x1104 0x1105 0x1106 -- 0x1110 0x1111 0x1112 0x1113 0x1114 0x1115 0x1116 -- 0x1120 0x1121 0x1122 0x1123 0x1124 0x1125 Symbol PP_J1MSGMM_ALMBNBSR -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 J1 Message Mismatch Alarm Binning PP_J1MSGMM_ALMBNBS[A--D] PP_PDI_ALMBNBSR PP_TSPDI_ALMBSRA PP_TSPDI_ALMBSRB PP_TSPDI_ALMBSRC PP_TSPDI_ALMBSRD -- Payload Defect Indicator Alarm per STS-1 Bytestream A PP_TSPDI_ALMBSA[1--12] Payload Defect Indicator Alarm per STS-1 Bytestream B PP_TSPDI_ALMBSB[1--12] Payload Defect Indicator Alarm per STS-1 Bytestream C PP_TSPDI_ALMBSC[1--12] Payload Defect Indicator Alarm per STS-1 Bytestream D PP_TSPDI_ALMBSD[1--12] Payload Defect Indicator Alarm Binning PP_PDI_ALMBNBS[A--D] PP_RDI_ALMDBNBSR PP_TSRDI_ALMDBSRA PP_TSRDI_ALMDBSRB PP_TSRDI_ALMDBSRC PP_TSRDI_ALMDBSRD -- Remote Defect Indicator Alarm Delta Binning PP_RDI_ALMDBNBS[A--D] Remote Defect Indicator Alarm Delta per STS-1 Bytestream A PP_TSRDI_ALMDBSA[1--12] Remote Defect Indicator Alarm Delta per STS-1 Bytestream B PP_TSRDI_ALMDBSB[1--12] Remote Defect Indicator Alarm Delta per STS-1 Bytestream C PP_TSRDI_ALMDBSC[1--12] Remote Defect Indicator Alarm Delta per STS-1 Bytestream D PP_TSRDI_ALMDBSD[1--12] PP_PLM_ALMDBNBSR PP_TSPLM_ALMDBSRA PP_TSPLM_ALMDBSRB PP_TSPLM_ALMDBSRC PP_TSPLM_ALMDBSRD Payload Label Mismatch Alarm Delta Binning PP_PLM_ALMDBNBS[A--D] Payload Label Mismatch Alarm Delta per STS-1 Bytestream A PP_TSPLM_ALMDBSA[1--12] Payload Label Mismatch Alarm Delta per STS-1 Bytestream B PP_TSPLM_ALMDBSB[1--12] Payload Label Mismatch Alarm Delta per STS-1 Bytestream C PP_TSPLM_ALMDBSC[1--12] Payload Label Mismatch Alarm Delta per STS-1 Bytestream D PP_TSPLM_ALMDBSD[1--12] 320 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1126 -- 0x1130 0x1131 0x1132 0x1133 0x1134 0x1135 0x1136 -- 0x1140 0x1141 0x1142 0x1143 0x1144 0x1145 0x1146 -- 0x1150 0x1151 0x1152 0x1153 0x1154 0x1155 0x1156 -- 0x115F Symbol -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PP_UNEQR_ALMDBNBSR PP_TSUNEQR_ALMDBSRA PP_TSUNEQR_ALMDBSRB PP_TSUNEQR_ALMDBSRC PP_TSUNEQR_ALMDBSRD -- Unequipped Received Alarm Delta per STS-1 Bytestream A PP_TSUNEQR_ALMDBSA[1--12] Unequipped Received Alarm Delta per STS-1 Bytestream B PP_TSUNEQR_ALMDBSB[1--12] Unequipped Received Alarm Delta per STS-1 Bytestream C PP_TSUNEQR_ALMDBSC[1--12] Unequipped Received Alarm Delta per STS-1 Bytestream D PP_TSUNEQR_ALMDBSD[1--12] Unequipped Received Alarm Delta Binning PP_UNEQR_ALMDBNBS[A--D] PP_AIS_ALMDBNBSR PP_TSAIS_ALMDBSRA PP_TSAIS_ALMDBSRB PP_TSAIS_ALMDBSRC PP_TSAIS_ALMDBSRD -- Alarm Indicator Signal Alarm Delta per STS-1 Bytestream A PP_TSAIS_ALMDBSA[1--12] Alarm Indicator Signal Alarm Delta per STS-1 Bytestream B PP_TSAIS_ALMDBSB[1--12] Alarm Indicator Signal Alarm Delta per STS-1 Bytestream C PP_TSAIS_ALMDBSC[1--12] Alarm Indicator Signal Alarm Delta per STS-1 Bytestream D PP_TSAIS_ALMDBSD[1--12] Alarm Indicator Signal Alarm Delta Binning PP_AIS_ALMDBNBS[A--D] PP_LOP_ALMDBNBSR PP_TSLOP_ALMDBSRA PP_TSLOP_ALMDBSRB PP_TSLOP_ALMDBSRC PP_TSLOP_ALMDBSRD -- Loss of Pointer Alarm Delta per STS-1 Bytestream A PP_TSLOP_ALMDBSA[1--12] Loss of Pointer Alarm Delta per STS-1 Bytestream B PP_TSLOP_ALMDBSB[1--12] Loss of Pointer Alarm Delta per STS-1 Bytestream C PP_TSLOP_ALMDBSC[1--12] Loss of Pointer Alarm Delta per STS-1 Bytestream D PP_TSLOP_ALMDBSD[1--12] Loss of Pointer Alarm Delta Binning PP_LOP_ALMDBNBS[A--D] Agere Systems Inc. 321 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1160 0x1161 -- 0x1170 0x1171 0x1172 0x1173 0x1174 0x1175 0x1176 0x1177 0x1178 0x1179 0x117A 0x117B 0x117C 0x117D 0x117E 0x117F 0x1180 0x1181 0x1182 0x1183 0x1184 0x1185 0x1186 0x1187 0x1188 0x1189 0x118A 0x118B 0x118C -- 0x120E Symbol PP_PTRACCMPIR -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PP_J1BFA CCMPI PP_PDI_ALMDBNBSR PP_TSPDI_ALMDBSRA PP_TSPDI_ALMDBSRB PP_TSPDI_ALMDBSRC PP_TSPDI_ALMDBSRD -- PP_ -- PP_ -- PP_ -- PP_ -- PP_ -- PP_ -- PP_ PP_ PP_ PP_ -- PP_ -- PP_ PP_ PP_ PP_ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PDI Alarm Delta per STS-1 Bytestream A PP_TSPDI_ALMDBSA[1--12] PDI Alarm Delta per STS-1 Bytestream B PP_TSPDI_ALMDBSB[1--12] PDI Alarm Delta per STS-1 Bytestream C PP_TSPDI_ALMDBSC[1--12] PDI Alarm Delta per STS-1 Bytestream D PP_TSPDI_ALMDBSD[1--12] PDI Alarm Delta Binning PP_PDI_ALMDBNBS[A--D] STS-1 #12 Channel Path Alarms Binning -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS-1 Channel Path Alarms -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS-1 Channel Path Alarms -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 322 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x120F PP_POH_ALMBNMR1 14 13 12 11 10 9 Masks -- -- -- -- -- -- -- PP_PDI_A LMDBNM PP_ UNEQR_ ALMBNM PP_PDI_A LMBNM PP_AIS_ ALMBNM PP_ J1ACCMP_ ALMBNM PP_LOP_ ALMBNM 8 Bit Number 7 6 5 4 3 2 1 0 0x1210 PP_POH_ALMBNMR2 PP_RDI_A PP_PLM_A LMDBNM LMDBNM PP_ PP_AIS_ PP_LOP_ PP_J1MM_ UNEQR_ ALMDBNM ALMDBNM ALMBNM ALMDBNM PP_ J1VLD_ ALMBNM PP_ USCNCT_ ALMBNM PP_ CNCTMM_ ALMBNM PP_ES_ ALMBNM PP_SF_ ALMBNM PP_RDI_ ALMBNM PP_PLM_A LMBNM 0x1211 0x1212 0x1213 0x1214 0x1215 0x1216 -- 0x1220 0x1221 0x1222 0x1223 0x1224 0x1225 0x1226 -- 0x1230 0x1231 0x1232 0x1233 0x1234 PP_ES_ALMBNMBSR PP_TSES_ALMMBSRA PP_TSES_ALMMBSRB PP_TSES_ALMMBSRC PP_TSES_ALMMBSRD -- Elastic Store Overrun/Underrun Alarm Binning Mask PP_ES_ALMBNMBS[A--D] Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream A PP_TSES_ALMMBSA[1--12] Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream B PP_TSES_ALMMBSB[1--12] Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream C PP_TSES_ALMMBSC[1--12] Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream D PP_TSES_ALMMBSD[1--12] PP_SF_ALMBNMBSR PP_TSSF_ALMMBSRA PP_TSSF_ALMMBSRB PP_TSSF_ALMMBSRC PP_TSSF_ALMMBSRD -- Signal Fail Alarm Mask per STS-1 Bytestream A PP_TSSF_ALMMBSA[1--12] Signal Fail Alarm Mask per STS-1 Bytestream B PP_TSSF_ALMMBSB[1--12] Signal Fail Alarm Mask per STS-1 Bytestream C PP_TSSF_ALMMBSC[1--12] Signal FAil Alarm Mask per STS-1 Bytestream D PP_TSSF_ALMMBSD[1--12] Signal Fail Alarm Binning Mask PP_SF_ALMBNMBS[A--D] PP_RDI_ALMBNMBSR PP_TSRDI_ALMMBSRA PP_TSRDI_ALMMBSRB PP_TSRDI_ALMMBSRC Remote Defect Indicator Alarm Binning Mask PP_RDI_ALMBNMBS[A--D] Remote Defect Indicator Alarm Mask per STS-1 Bytestream A PP_TSRDI_ALMMBSA[1--12] Remote Defect Indicator Alarm Mask per STS-1 Bytestream B PP_TSRDI_ALMMBSB[1--12] Remote Defect Indicator Alarm Mask per STS-1 Bytestream C PP_TSRDI_ALMMBSC[1--12] Agere Systems Inc. 323 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1235 0x1236 -- 0x1240 0x1241 0x1242 0x1243 0x1244 0x1245 0x1246 -- 0x1250 0x1251 0x1252 0x1253 0x1254 0x1255 0x1256 -- 0x1260 0x1261 0x1262 0x1263 0x1264 0x1265 Symbol 15 PP_TSRDI_ALMMBSRD -- 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 Remote Defect Indicator Alarm Mask per STS-1 Bytestream D PP_TSRDI_ALMMBSD[1--12] PP_PLM_ALMBNMBSR PP_TSPLM_ALMMBSRA PP_TSPLM_ALMMBSRB PP_TSPLM_ALMMBSRC PP_TSPLM_ALMMBSRD -- Payload Label Mismatch Alarm Binning Mask PP_PLM_ALMBNMBS[A--D] Payload Label Mismatch Alarm Mask per STS-1 Bytestream A PP_TSPLM_ALMMBSA[1--12] Payload Label Mismatch Alarm Mask per STS-1 Bytestream B PP_TSPLM_ALMMBSB[1--12] Payload Label Mismatch Alarm Mask per STS-1 Bytestream C PP_TSPLM_ALMMBSC[1--12] Payload Label Mismatch Alarm Mask per STS-1 Bytestream D PP_TSPLM_ALMMBSD[1--12] PP_UNEQR_ALMBNMBSR PP_TSUNEQR_ALMMBSRA PP_TSUNEQR_ALMMBSB PP_TSUNEQR_ALMMBSC PP_TSUNEQR_ALMMBSD -- Unequipped Received Alarm Mask per STS-1 Bytestream A PP_TSUNEQR_ALMMBSA[1--12] Unequipped Received Alarm Mask per STS-1 Bytestream B PP_TSUNEQR_ALMMBSB[1--12] Unequipped Received Alarm Mask per STS-1 Bytestream C PP_TSUNEQR_ALMMBSC[1--12] Unequipped Received Alarm Mask per STS-1 Bytestream D PP_TSUNEQR_ALMMBSD[1--12] Unequipped Received Alarm Binning Mask PP_UNEQR_ALMBNMBS[A--D] PP_AIS_ALMBNMBSR PP_TSAIS_ALMMBSRA PP_TSAIS_ALMMBSRB PP_TSAIS_ALMMBSRC PP_TSAIS_ALMMBSRD Alarm Indicator Signal Alarm Mask per STS-1 Bytestream A PP_TSAIS_ALMMBSA[1--12] Alarm Indicator Signal Alarm Mask per STS-1 Bytestream B PP_TSAIS_ALMMBSB[1--12] Alarm Indicator Signal Alarm Mask per STS-1 Bytestream C PP_TSAIS_ALMMBSC[1--12] Alarm Indicator Signal Alarm Mask per STS-1 Bytestream D PP_TSAIS_ALMMBSD[1--12] Alarm Indicator Signal Alarm Binning Mask PP_AIS_ALMBNMBS[A--D] 324 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1266 -- 0x1270 0x1271 0x1272 0x1273 0x1274 0x1275 0x1276 0x1277 0x1278 0x1279 0x127A 0x127B 0x127C 0x127D 0x127E -- 0x1280 0x1281 0x1282 0x1283 0x1284 0x1285 Symbol 15 -- 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 PP_LOP_ALMBNMBSR PP_TSLOP_ALMMBSRA PP_TSLOP_ALMMBSRB PP_TSLOP_ALMMBSRC PP_TSLOP_ALMMBSRD -- PP_CNCTMM_ALMMBSR -- PP_USCNCTM_ALMMBSR -- PP_J1NVLDMSG_ALMMBSR -- PP_J1MSGMM_ALMMBSR -- Loss of Pointer Alarm Mask per STS-1 Bytestream A PP_TSLOP_ALMMBSA[1--12] Loss of Pointer Alarm Mask per STS-1 Bytestream B PP_TSLOP_ALMMBSB[1--12] Loss of Pointer Alarm Mask per STS-1 Bytestream C PP_TSLOP_ALMMBSC[1--12] Loss of Pointer Alarm Mask per STS-1 Bytestream D PP_TSLOP_ALMMBSD[1--12] Loss of Pointer Alarm Binning Mask PP_LOP_ALMBNMBS[A--D] Concatenation Map Mismatch Alarm Mask PP_CNCTMM_ALMMBS[A--D] Unsupported Concatenation Map Alarm Mask PP_USCNCTM_ALMMBS[A--D] J1 New Validated Message Alarm Mask PP_J1NVLDMSG_ALMMBS[A--D] J1 Message Mismatch Alarm Mask PP_J1MSGMM_ALMMBS[A--D] PP_PDI_ALMBNMBSR PP_TSPDI_ALMMBSRA PP_TSPDI_ALMMBSRB PP_TSPDI_ALMMBSRC PP_TSPDI_ALMMBSRD Payload Defect Indicator Alarm Binning Mask PP_PDI_ALMBNMBS[A--D] Payload Defect Indicator Alarm Mask per STS-1 Bytestream A PP_TSPDI_ALMMBSA[1--12] Payload Defect Indicator Alarm Mask per STS-1 Bytestream B PP_TSPDI_ALMMBSB[1--12] Payload Defect Indicator Alarm Mask per STS-1 Bytestream C PP_TSPDI_ALMMBSC[1--12] Payload Defect Indicator Alarm Mask per STS-1 Bytestream D PP_TSPDI_ALMMBSD[1--12] Agere Systems Inc. 325 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x1286 -- 0x1290 0x1291 0x1292 0x1293 0x1294 0x1295 0x1296 -- 0x12A0 0x12A1 0x12A2 0x12A3 0x12A4 0x12A5 0x12A6 --0x12B 0x12B1 0x12B2 0x12B3 0x12B4 0x12B5 0x12B6 -- 0x12C0 Symbol 15 -- 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 PP_RDI_ALMDBNMBSR PP_TSRDI_ALMDMBSRA PP_TSRDI_ALMDMBSRB PP_TSRDI_ALMDMBSRC PP_TSRDI_ALMDMBSRD -- Remote Defect Indicator Alarm Delta Binning Mask PP_RDI_ALMDBNMBS[A--D] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream A PP_TSRDI_ALMDMBSA[1--12] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream B PP_TSRDI_ALMDMBSB[1--12] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream C PP_TSRDI_ALMDMBSC[1--12] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream D PP_TSRDI_ALMDMBSD[1--12] PP_PLM_ALMDBNMBSR PP_TSPLM_ALMDMBSRA PP_TSPLM_ALMDMBSRB PP_TSPLM_ALMDMBSRC PP_TSPLM_ALMDMBSRD -- PP_UNEQR_ALMDBNMBSR PP_TSUNEQR_ALMDMBSRA PP_TSUNEQR_ALMDMBSRB PP_TSUNEQR_ALMDMBSRC PP_TSUNEQR_ALMDMBSRD -- Payload Label Mismatch Alarm Delta Binning Mask PP_PLM_ALMDBNMBS[A--D] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream A PP_TSPLM_ALMDMBSA[1--12] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream B PP_TSPLM_ALMDMBSB[1--12] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream C PP_TSPLM_ALMDMBSC[1--12] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream D PP_TSPLM_ALMDMBSD[1--12] Unequipped Received Alarm Delta Binning Mask PP_UNEQR_ALMDBNMBS[A--D] Unequipped Received Alarm Delta Mask per STS-1 Bytestream A PP_TSUNEQR_ALMDMBSA[1--12] Unequipped Received Alarm Delta Mask per STS-1 Bytestream B PP_TSUNEQR_ALMDMBSB[1--12] Unequipped Received Alarm Delta Mask per STS-1 Bytestream C PP_TSUNEQR_ALMDMBSC[1--12] Unequipped Received Alarm Delta Mask per STS-1 Bytestream D PP_TSUNEQR_ALMDMBSD[1--12] 326 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x12C1 0x12C2 0x12C3 0x12C4 0x12C5 0x12C6 -- 0x12D0 0x12D1 0x12D2 0x12D3 0x12D4 0x12D5 0x12D6 -- 0x12DF 0x12E0 0x12E1 0x12E2 0x12E3 0x12E4 0x12E5 0x12E6 0x12E7 -- 0x12E8 Symbol 15 PP_AIS_ALMDBNMBSR PP_TSAIS_ALMDMBSRA PP_TSAIS_ALMDMBSRB PP_TSAIS_ALMDMBSRC PP_TSAIS_ALMDMBSRD -- 14 13 12 11 10 9 8 Bit Number 7 6 5 4 3 2 1 0 Alarm Indicator Signal Alarm Delta Binning Mask PP_AIS_ALMDBNMBS[A--D] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream A PP_TSAIS_ALMDMBSA[1--12] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream B PP_TSAIS_ALMDMBSB[1--12] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream C PP_TSAIS_ALMDMBSC[1--12] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream D PP_TSAIS_ALMDMBSD[1--12] PP_LOP_ALMDBNMBSR PP_TSLOP_ALMDMBSRA PP_TSLOP_ALMDMBSRB PP_TSLOP_ALMDMBSRC PP_TSLOP_ALMDMBSRD -- Loss of Pointer Alarm Delta Mask per STS-1 Bytestream A PP_TSLOP_ALMDMBSA[1--12] Loss of Pointer Alarm Delta Mask per STS-1 Bytestream B PP_TSLOP_ALMDMBSB[1--12] Loss of Pointer Alarm Delta Mask per STS-1 Bytestream C PP_TSLOP_ALMDMBSC[1--12] Loss of Pointer Alarm Delta Mask per STS-1 Bytestream D PP_TSLOP_ALMDMBSD[1--12] Loss of Pointer Alarm Delta Binning Mask PP_LOP_ALMDBNMBS[A--D] PP_PTRACCMPIR -- PP_ -- PP_ PP_ PP_ PP_ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PP_J1BFACCMPIM STS-1 Channel Path Alarm Masks -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Agere Systems Inc. 327 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x12E9 0x12EA 0x12EB 0x12EC 0x12ED 0x12EE 0x12EF 0x12F0 0x12F1 0x12F2 0x12F3 0x12F4 0x12F5 0x12F6 0x12F7 0x12F8 0x12F9 0x12FA 0x12FB 0x12FC 0x12FD 0x12FE -- 0x12FF Symbol 15 PP_PDI_ALMDBNMBSR PP_TSPDI_ALMDMBSRA PP_TSPDI_ALMDMBSRB PP_TSPDI_ALMDMBSRC PP_TSPDI_ALMDMBSRD -- PP_ -- -- PP_ -- PP_ -- PP_ -- PP_ -- PP_ -- PP_ PP_ PP_ PP_ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS-1 Channel Path Alarm Masks -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STS-1 #12 Channel Path Alarm Masks -- -- -- PDI Alarm Delta Mask per STS-1 Bytestream A PP_TSPDI_ALMDMBSA[1--12] PDI Alarm Delta Mask per STS-1 Bytestream B PP_TSPDI_ALMDMBSB[1--12] PDI Alarm Delta Mask per STS-1 Bytestream C PP_TSPDI_ALMDMBSC[1--12] PDI Alarm Delta Mask per STS-1 Bytestream D PP_TSPDI_ALMDMBSD[1--12] 14 13 12 11 10 9 8 Bit Number 7 6 5 4 3 2 1 0 PDI Alarm Delta Binning Mask PP_PDI_ALMDBNMBS[A--D] 328 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 -- 0x1300 -- 0x131F 0x1330 0x1331 0x1332 0x1333 0x1334 -- 0x1337 0x1338 0x1339 0x133A -- 0x133B 0x133C 0x133D 0x133E 0x133F 0x1340 0x1341 0x1342 0x1343 0x1344 0x1345 0x1346 0x1347 0x1348 0x1349 0x134A 0x134B 0x134C -- PP_PTRBFR[1--32] 14 13 12 11 10 9 Path Trace J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer PP_J1BYTE[1, 3, 5, . . . , 63][7:0] J1 Byte 0, 2, 4, . . . , 62 Path Trace Buffer PP_J1BYTE[0, 2, 4, . . . , 62][7:0] 8 Bit Number 7 6 5 4 3 2 1 0 PP_PTRACCTLR1 PP_PTRACCTLR2 PP_PTRACCTLR3 PP_PTRACBGR -- PP_J1TS1_CHSEL[1:0] PP_J1BF_ MSGSEL PP_J1BF_ ACTYP PP_J1_ ACBG PP_STS12PTRCTLR1 PP_STS12PTRCTLR2 -- J1 Message Mode Select PP_J1MSG_MSEL[A--D] J1 Message Type Select PP_J1MSG_TYPSEL[A--D] PP_STS12PTRCTLR3 PP_STS12PTRCTLR4 PP_STS12PTRCTLR5 PP_STS12PTRCTLR6 -- PP_ PP_ PP_ -- PP_ PP_ PP_ -- PP_ PP_ PP_ -- F2 Validation Period H4/Z3/Z4 Validation Period -- -- F2 Validation Period -- -- -- -- -- -- -- -- H4/Z3/Z4 Validation Period -- -- -- -- -- -- -- -- -- -- -- F2 Validation Period -- -- -- -- -- -- -- -- H4/Z3/Z4 Validation Period -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Time Slots 1--12 Select for J1 Accumulation PP_TSSEL_J1A[3:0] PP_TSSEL_J1B[3:0] PP_TSSEL_J1C[3:0] PP_TSSEL_J1D[3:0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Z5 Validation Period STS-1 Channel Select for F2/H4/Zi Bytes Monitoring Z5 Validation Period STS-1 Channel Select for F2/H4/Zi Bytes Monitoring Z5 Validation Period STS-1 Channel Select for F2/H4/Zi Bytes Monitoring Agere Systems Inc. 329 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x134D 0x134E 0x134F 0x1350 0x1351 0x1352 0x1353 0x1354 0x1355 0x1356 0x1357 0x1358 0x1359 -- 0x137F Symbol 15 PP_ PP_ PP_ -- PP_ PP_ PP_ PP_ PP_ PP_ PP_ PP_ -- F2 Validation Period -- -- -- -- -- -- -- -- H4/Z3/Z4 Validation Period -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 14 -- -- 13 -- -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- Bit Number 7 -- -- -- 6 -- -- -- -- -- -- -- -- -- -- -- 5 -- -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- -- -- -- -- -- -- 3 -- -- -- -- -- -- -- -- -- -- -- 2 -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- Z5 Validation Period STS-1 Channel Select for F2/H4/Zi Bytes Monitoring 330 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x1380 -- 0x1381 0x1382 0x1383 0x1384 0x1385 0x1386 -- 0x1389 0x138A 0x138B 0x138C 0x138D 0x138E -- 0x1391 0x1392 0x1393 0x1394 0x1395 0x1396 -- 0x1399 -- 14 13 12 11 10 9 Persistency Bit Number 8 7 6 5 4 3 2 1 0 PP_TSRDI_ALMPSBSRA PP_TSRDI_ALMPSBSRB PP_TSRDI_ALMPSBSRC PP_TSRDI_ALMPSBSRD -- RDI Alarm Persistency per STS-1 Bytestream A PP_TSRDI_ALMPSBSA[1--12] RDI Alarm Persistency per STS-1 Bytestream B PP_TSRDI_ALMPSBSB[1--12] RDI Alarm Persistency per STS-1 Bytestream C PP_TSRDI_ALMPSBSC[1--12] RDI Alarm Persistency per STS-1 Bytestream D PP_TSRDI_ALMPSBSD[1--12] PP_TSPLM_ALMPSBSRA PP_TSPLM_ALMPSBSRB PP_TSPLM_ALMPSBSRC PP_TSPLM_ALMPSBSRD -- Payload Label Mismatch Alarm Persistency per STS-1 Bytestream A PP_TSPLM_ALMPSBSA[1--12] Payload Label Mismatch Alarm Persistency per STS-1 Bytestream B PP_TSPLM_ALMPSBSB[1--12] Payload Label Mismatch Alarm Persistency per STS-1 Bytestream C PP_TSPLM_ALMPSBSC[1--12] Payload Label Mismatch Alarm Persistency per STS-1 Bytestream D PP_TSPLM_ALMPSBSD[1--12] PP_TSPUNEQ_ALMPSBSRA PP_TSPUNEQ_ALMPSBSRB PP_TSPUNEQ_ALMPSBSRC PP_TSPUNEQ_ALMPSBSRD -- Path Unequipped Alarm Persistency per STS-1 Bytestream A PP_TSPUNEQ_ALMPSBSA[1--12] Path Unequipped Alarm Persistency per STS-1 Bytestream B PP_TSPUNEQ_ALMPSBSB[1--12] Path Unequipped Alarm Persistency per STS-1 Bytestream C PP_TSPUNEQ_ALMPSBSC[1--12] Path Unequipped Alarm Persistency per STS-1 Bytestream D PP_TSPUNEQ_ALMPSBSD[1--12] Agere Systems Inc. 331 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x139A 0x139B 0x139C 0x139D 0x139E -- 0x13A1 0x13A2 0x13A3 0x13A4 0x13A5 0x13A6 -- 0x13A9 0x13AA 0x13AB 0x13AC 0x13AD 0x13AE -- 0x13BF Symbol 15 PP_TSAIS_ALMPSBSRA PP_TSAIS_ALMPSBSRB PP_TSAIS_ALMPSBSRC PP_TSAIS_ALMPSBSRD -- 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 AIS Alarm Persistency per STS-1 Bytestream A PP_TSAIS_ALMPSBSA[1--12] AIS Alarm Persistency per STS-1 Bytestream B PP_TSAIS_ALMPSBSB[1--12] AIS Alarm Persistency per STS-1 Bytestream C PP_TSAIS_ALMPSBSC[1--12] AIS Alarm Persistency per STS-1 Bytestream D PP_TSAIS_ALMPSBSD[1--12] PP_TSLOP_ALMPSBSRA PP_TSLOP_ALMPSBSRB PP_TSLOP_ALMPSBSRC PP_TSLOP_ALMPSBSRD -- LOP Alarm Persistency per STS-1 Bytestream A PP_TSLOP_ALMPSBSA[1--12] LOP Alarm Persistency per STS-1 Bytestream B PP_TSLOP_ALMPSBSB[1--12] LOP Alarm Persistency per STS-1 Bytestream C PP_TSLOP_ALMPSBSC[1--12] LOP Alarm Persistency per STS-1 Bytestream D PP_TSLOP_ALMPSBSD[1--12] PP_TSPDI_ALMPSBSRA PP_TSPDI_ALMPSBSRB PP_TSPDI_ALMPSBSRC PP_TSPDI_ALMPSBSRD -- PDI Alarm Persistency per STS-1 Bytestream A PP_TSPDI_ALMPSBSA[1--12] PDI Alarm Persistency per STS-1 Bytestream B PP_TSPDI_ALMPSBSB[1--12] PDI Alarm Persistency per STS-1 Bytestream C PP_TSPDI_ALMPSBSC[1--12] PDI Alarm Persistency per STS-1 Bytestream D PP_TSPDI_ALMPSBSD[1--12] 332 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x13C0 -- 0x13C1 0x13C2 0x13C3 0x13C4 0x13C5 0x13C6 -- 0x13C9 0x13CA 0x13CB 0x13CC 0x13CD 0x13CE -- 0x13D1 0x13D2 0x13D3 0x13D4 0x13D5 0x13D6 -- 0x13D9 -- 14 13 12 11 10 9 State Bit Number 8 7 6 5 4 3 2 1 0 PP_TSRDI_STBSRA PP_TSRDI_STBSRB PP_TSRDI_STBSRC PP_TSRDI_STBSRD -- RDI State per STS-1 Bytestream A PP_TSRDI_STBSA[1--12] RDI State per STS-1 Bytestream B PP_TSRDI_STBSB[1--12] RDI State per STS-1 Bytestream C PP_TSRDI_STBSC[1--12] RDI State per STS-1 Bytestream D PP_TSRDI_STBSD[1--12] PP_TSPLM_STBSRA PP_TSPLM_STBSRB PP_TSPLM_STBSRC PP_TSPLM_STBSRD -- Payload Label Mismatch State per STS-1 Bytestream A PP_TSPLM_STBSA[1--12] Payload Label Mismatch State per STS-1 Bytestream B PP_TSPLM_STBSB[1--12] Payload Label Mismatch State per STS-1 Bytestream C PP_TSPLM_STBSC[1--12] Payload Label Mismatch State per STS-1 Bytestream D PP_TSPLM_STBSD[1--12] PP_TSPUNEQ_STBSRA PP_TSPUNEQ_STBSRB PP_TSPUNEQ_STBSRC PP_TSPUNEQ_STBSRD -- Path Unequipped State per STS-1 Bytestream A PP_TSPUNEQ_STBSA[1--12] Path Unequipped State per STS-1 Bytestream B PP_TSPUNEQ_STBSB[1--12] Path Unequipped State per STS-1 Bytestream C PP_TSPUNEQ_STBSC[1--12] Path Unequipped State per STS-1 Bytestream D PP_TSPUNEQ_STBSD[1--12] Agere Systems Inc. 333 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x13DA 0x13DB 0x13DC 0x13DD 0x13DE -- 0x13E1 0x13E2 0x13E3 0x13E4 0x13E5 0x13E6 -- 0x13E9 0x13EA 0x13EB 0x13EC 0x13ED 0x13EE -- 0x13FF Symbol 15 PP_TSAIS_STBSRA PP_TSAIS_STBSRB PP_TSAIS_STBSRC PP_TSAIS_STBSRD -- 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 AIS State per STS-1 Bytestream A PP_TSAIS_STBSA[1--12] AIS State per STS-1 Bytestream B PP_TSAIS_STBSB[1--12] AIS State per STS-1 Bytestream C PP_TSAIS_STBSC[1--12] AIS State per STS-1 Bytestream D PP_TSAIS_STBSD[1--12] PP_TSLOP_STBSRA PP_TSLOP_STBSRB PP_TSLOP_STBSRC PP_TSLOP_STBSRD -- LOP State per STS-1 Bytestream A PP_TSLOP_STBSA[1--12] LOP State per STS-1 Bytestream B PP_TSLOP_STBSB[1--12] LOP State per STS-1 Bytestream C PP_TSLOP_STBSC[1--12] LOP State per STS-1 Bytestream D PP_TSLOP_STBSD[1--12] PP_TSPDI_STBSRA PP_TSPDI_STBSRB PP_TSPDI_STBSRC PP_TSPDI_STBSRD -- PDI State per STS-1 Bytestream A PP_TSPDI_STBSA[1--12] PDI State per STS-1 Bytestream B PP_TSPDI_STBSB[1--12] PDI State per STS-1 Bytestream C PP_TSPDI_STBSC[1--12] LOP State per STS-1 Bytestream D PP_TSPDI_STBSD[1--12] 334 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x1400 0x1401 0x1402 -- 0x140F 0x1410 0x1411 0x1412 0x1413 0x1414 0x1415 0x1416 0x1417 0x1418 0x1419 0x141A 0x141B 0x141C 0x141D 0x141E 0x141F 0x1420 0x1421 -- 0x142F 0x1430 0x1431 -- 0x143F 0x1440 0x1441 -- 0x144F 0x1450 0x1451 -- 0x1501 PP_SFWSZ_SELR1 PP_SFWSZ_SELR2 -- 14 13 12 11 10 9 Signal Fail PP_SFWSZ_SELSET[0--7][1:0] PP_SFWSZ_SELCLR[0--7][1:0] Bit Number 8 7 6 5 4 3 2 1 0 PP_SFDR0 PP_SFDR1 PP_SFDR2 PP_SFDR3 PP_SFDR4 PP_SFDR5 PP_SFDR6 PP_SFDR7 PP_SFCLRR0 PP_SFCLRR1 PP_SFCLRR2 PP_SFCLRR3 PP_SFCLRR4 PP_SFCLRR5 PP_SFCLRR6 PP_SFCLRR7 PP_SFWSZR0 -- PP_SFCLR2[13:0] PP_SFCLR3[13:0] PP_SFCLR4[13:0] PP_SFCLR5[13:0] PP_SFCLR6[13:0] PP_SFCLR7[13:0] PP_SFWSZ0[15:0] PP_SFD2[13:0] PP_SFD3[13:0] PP_SFD4[13:0] PP_SFD5[13:0] PP_SFD6[13:0] PP_SFD7[13:0] PP_SFD0[8:0] PP_SFD1[8:0] PP_SFCLR0[8:0] PP_SFCLR1[8:0] PP_SFWSZR1 -- PP_SFWSZ1[15:0] PP_SFWSZR2 -- PP_SFWSZ2[15:0] PP_SFWSZR3 -- PP_SFWSZ3[15:0] Agere Systems Inc. 335 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x1502 0x1503 0x1504 0x1505 0x1506 0x1507 0x1508 0x1509 0x150A 0x150B -- 0x1511 0x1512 0x1513 0x1514 0x1515 0x1516 -- 0x1541 PP_ECNCTM_TSBSRA PP_ECNCTM_TSBSRB PP_ECNCTM_TSBSRC PP_ECNCTM_TSBSRD -- PP_CNCTCPREN_TSBSRA PP_CNCTCPREN_TSBSRB PP_CNCTCPREN_TSBSRC PP_CNCTCPREN_TSBSRD -- Software Concatenation Compare Enable Bytestream A PP_CNCTCPREN_TSBSA[1--12] Software Concatenation Compare Enable Bytestream B PP_CNCTCPREN_TSBSB[1--12] Software Concatenation Compare Enable Bytestream C PP_CNCTCPREN_TSBSC[1--12] Software Concatenation Compare Enable Bytestream D PP_CNCTCPREN_TSBSD[1--12] 14 13 12 11 10 9 Concatenation Expected Concatenation Map Bytestream A PP_ECNCT_STTSBSA[1--12] Expected Concatenation Map Bytestream B PP_ECNCT_STTSBSB[1--12] Expected Concatenation Map Bytestream C PP_ECNCT_STTSBSC[1--12] Expected Concatenation Map Bytestream D PP_ECNCT_STTSBSD[1--12] Bit Number 8 7 6 5 4 3 2 1 0 PP_RCNCTM_TSBSRA PP_RCNCTM_TSBSRB PP_RCNCTM_TSBSRC PP_RCNCTM_TSBSRD -- Received Concatenation Map Bytestream A PP_RCNCT_STTSBSA[1--12] Received Concatenation Map Bytestream B PP_RCNCT_STTSBSB[1--12] Received Concatenation Map Bytestream C PP_RCNCT_STTSBSC[1--12] Received Concatenation Map Bytestream D PP_RCNCT_STTSBSD[1--12] 336 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x1542 0x1543 0x1544 0x1545 0x1546 -- 0x157F 0x1580 0x1581 0x1582 0x1583 0x1584 0x1585 0x1586 0x1587 0x1588 0x1589 0x158A 0x158B PP_SWAIS_ISRTRA PP_SWAIS_ISRTRB PP_SWAIS_ISRTRC PP_SWAIS_ISRTRD -- 14 13 12 11 10 9 AIS Insert Control AIS Insert Bytestream A PP_SWAIS_ISRTA[1--12] AIS Insert Bytestream B PP_SWAIS_ISRTB[1--12] AIS Insert Bytestream C PP_SWAIS_ISRTC[1--12] AIS Insert Bytestream D PP_SWAIS_ISRTD[1--12] Bit Number 8 7 6 5 4 3 2 1 0 Pointer Processor Control PP_STS12_PINCDECR -- PP_TSSS_ISRTBSRA PP_TSSS_ISRTBSRB PP_TSSS_ISRTBSRC PP_TSSS_ISRTBSRD -- PP_TSE1F1_ISRTBSRA PP_TSE1F1_ISRTBSRB PP_TSE1F1_ISRTBSRC PP_TSE1F1_ISRTBSRD -- E1/F1 Insert Control Bytestream A PP_TSE1F1_ISRTBSA[1--12] E1/F1 Insert Control Bytestream B PP_TSE1F1_ISRTBSB[1--12] E1/F1 Insert Control Bytestream C PP_TSE1F1_ISRTBSC[1--12] E1/F1 Insert Control Bytestream D PP_TSE1F1_ISRTBSD[1--12] SS Bits Insert Control Bytestream A PP_TSSS_ISRTBSA[1--12] SS Bits Insert Control Bytestream B PP_TSSS_ISRTBSB[1--12] SS Bits Insert Control Bytestream C PP_TSSS_ISRTBSC[1--12] SS Bits Insert Control Bytestream D PP_TSSS_ISRTBSD[1--12] SONET/SDH Pointer Inc/Dec Rules PP_PINCDEC[A--D] Agere Systems Inc. 337 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x158C 0x158D 0x158E 0x158F 0x1590 0x1591 0x1592 0x1593 0x1594 0x1595 0x1596 0x1597 0x1598 -- 0x15A1 0x15A2 0x15A3 0x15A4 0x15A5 0x15A6 -- 0x15FF Symbol 15 PP_E2_ISRTCTLRA PP_E2_ISRTCTLRB PP_E2_ISRTCTLRC PP_E2_ISRTCTLRD PP_TS_INCDECBNRA PP_TS_INCDECBNRB PP_TS_INCDECBNRC PP_TS_INCDECBNRD PP_AISONTIM_ISRTRA PP_AISONTIM_ISRTRB PP_AISONTIM_ISRTRC PP_AISONTIM_ISRTRD -- TIM Insert Control Bytestream A PP_AISONTIM_ISRT_ A[1--12] TIM Insert Control Bytestream B PP_ AISONTIM_ISRT_B[1--12] TIM Insert Control Bytestream C PP_ AISONTIM_ISRT_C[1--12] TIM Insert Control Bytestream D PP_ AISONTIM_ISRT_D[1--12] 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 PP_E2_IS RTCTLA PP_E2_IS RTCTLB PP_E2_IS RTCTLC PP_E2_IS RTCTLD STS-1 Inc/Dec Binning Select Bytestream A PP_TS_INCDECBNA[3:0] STS-1 Inc/Dec Binning Select Bytestream B PP_TS_INCDECBNB[3:0] STS-1 Inc/Dec Binning Select Bytestream C PP_TS_INCDECBNC[3:0] STS-1 Inc/Dec Binning Select Bytestream D PP_TS_INCDECBND[3:0] PP_TSPDIVLD_CTLBSRA PP_TSPDIVLD_CTLBSRB PP_TSPDIVLD_CTLBSRC PP_TSPDIVLD_CTLBSRD -- PDI Validate Control Bytestream A PP_TSPDIVLD_CTLBSA[1--12] PDI Validate Control Bytestream B PP_TSPDIVLD_CTLBSB[1--12] PDI Validate Control Bytestream C PP_TSPDIVLD_CTLBSC[1--12] PDI Validate Control Bytestream D PP_TSPDIVLD_CTLBSD[1--12] 338 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 -- 0x1600 -- 0x1617 0x1618 0x1619 0x161A 0x161B 0x161C -- 0x161F 0x1620 0x1621 0x1622 0x1623 0x1624 0x1625 0x1626 0x1627 0x1628 0x1629 0x162A 0x162B 0x162C 0x162D 0x162F -- 0x164F -- PP_EXPC2_PVSNR[1--24] 14 13 12 11 10 9 Provisioning Time Slots 1, 3, 5, . . ., 47 Expected C2 Bytes PP_EXPC2[1, 3, 5, . . ., 47][7:0] Time Slot 2, 4, 6, . . ., 48 Expected C2 Bytes PP_EXPCP[2, 4, 6, . . ., 48][7:0] Bit Number 8 7 6 5 4 3 2 1 0 PP_TSCBB_ERRBSRA PP_TSCBB_ERRBSRB PP_TSCBB_ERRBSRC PP_TSCBB_ERRBSRD -- Count Bit/Block Errors Bytestream A PP_TSCBB_ERRBSA[1--12] Count Bit/Block Errors Bytestream B PP_TSCBB_ERRBSB[1--12] Count Bit/Block Errors Bytestream C PP_TSCBB_ERRBSC[1--12] Count Bit/Block Errors Bytestream D PP_TSCBB_ERRBSD[1--12] PP_TS1_6_SSBSRA PP_TS_SSA1[1:0] PP_TS7_12_SSBSRA PP_TS1_6_SSBSRB PP_TS_SSB1[1:0] PP_TS7_12_SSBSRB PP_TS1_6_SSBSRC PP_TS_SSC1[1:0] PP_TS7_12_SSBSRC PP_TS1_6_SSBSRD PP_TS_SSD1[1:0] PP_TS7_12_SSBSRD -- -- -- -- -- -- -- PP_ES_DEC_MAX[7:0] PP_ES_OVR_MAX[7:0] PP_TS_SSD7[1:0] PP_TS_SSD2[1:0] PP_TS_SSD8[1:0] PP_TS_SSC7[1:0] PP_TS_SSC2[1:0] PP_TS_SSC8[1:0] PP_TS_SSB7[1:0] PP_TS_SSB2[1:0] PP_TS_SSB8[1:0] PP_TS_SSA7[1:0] PP_TS_SSA2[1:0] PP_TS_SSA8[1:0] SS Bits Setting Bytestream A PP_TS_SSA3[1:0] PP_TS_SSA9[1:0] PP_TS_SSB3[1:0] PP_TS_SSB9[1:0] PP_TS_SSC3[1:0] PP_TS_SSC9[1:0] PP_TS_SSD3[1:0] PP_TS_SSD9[1:0] PP_TS_SSA4[1:0] PP_TS_SSA10[1:0] PP_TS_SSB4[1:0] PP_TS_SSB10[1:0] PP_TS_SSC4[1:0] PP_TS_SSC10[1:0] PP_TS_SSD4[1:0] PP_TS_SSD10[1:0] PP_TS_SSA5[1:0] PP_TS_SSA11[1:0] PP_TS_SSB5[1:0] PP_TS_SSB11[1:0] PP_TS_SSC5[1:0] PP_TS_SSC11[1:0] PP_TS_SSD5[1:0] PP_TS_SSD11[1:0] PP_TS_SSA6[1:0] PP_TS_SSA12[1:0] PP_TS_SSB6[1:0] PP_TS_SSB12[1:0] PP_TS_SSC6[1:0] PP_TS_SSC12[1:0] PP_TS_SSD6[1:0] PP_TS_SSD12[1:0] SS Bits Setting Bytestream B SS Bits Setting Bytestream C SS Bits Setting Bytestream D [A--D] [A--D] PP_ES_INC_MIN[7:0] PP_ES_OVR_MIN[7:0] Agere Systems Inc. 339 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr -- 0x1650 -- 0x1667 0x1668 0x1669 0x166A 0x166B 0x166C -- 0x1681 0x1682 -- 0x168F 0x1690 -- 0x16BF 0x16C0 -- 0x1701 Symbol 15 -- PP_TS_E1F1ISRTR[1--24] 14 13 12 11 10 9 Time Slots 1, 3, 5, . . ., 47 E1/F1 insert byte PP_TS_E1F1ISRT[1, 3, 5, . . ., 47][7:0] Bit Number 8 7 6 5 4 3 2 1 0 Time Slots 2, 4, 6, . . ., 48 E1/F1 insert byte PP_TS_E1F1ISRT[2, 4, 6, . . ., 48][7:0] PP_E2_ISRTBSRA PP_E2_ISRTBSRB PP_E2_ISRTBSRC PP_E2_ISRTBSRD -- Stream A E2 insert byte PP_E2_ISRTBSA[7:0] Stream B E2 insert byte PP_E2_ISRTBSB[7:0] Stream C E2 insert byte PP_E2_ISRTBSC[7:0] Stream D E2 insert byte PP_E2_ISRTBSD[7:0] Maintenance -- PP_TSMNTR[1--48] PP_TSSF_TH[1--48][2:0] -- 340 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x1702 0x1703 0x1704 0x1705 0x1706 -- 0x1711 0x1712 0x1713 0x1714 0x1715 0x1716 -- 0x1741 0x1742 0x1743 0x1744 0x1745 0x1746 -- 0x1751 0x1752 0x1753 0x1754 0x1755 0x1756 -- 0x177F PP_PI_LSECINCRA PP_PI_LSECINCRB PP_PI_LSECINCRC PP_PI_LSECINCRD -- 14 13 12 11 10 9 Interpreter Inc/Dec (PM) PP_PI_LSECINCA[10:0] PP_PI_LSECINCB[10:0] PP_PI_LSECINCC[10:0] PP_PI_LSECINCD[10:0] Bit Number 8 7 6 5 4 3 2 1 0 PP_PI_LSECDECRA PP_PI_LSECDECRB PP_PI_LSECDECRC PP_PI_LSECDECRD -- PP_PI_LSECDECA[10:0] PP_PI_LSECDECB[10:0] PP_PI_LSECDECC[10:0] PP_PI_LSECDECD[10:0] Generator Inc/Dec (PM) PP_PG_LSECINCRA PP_PG_LSECINCRB PP_PG_LSECINCRC PP_PG_LSECINCRD -- PP_PG_LSECINCA[10:0] PP_PG_LSECINCB[10:0] PP_PG_LSECINCC[10:0] PP_PG_LSECINCD[10:0] PP_PG_LSECDECRA PP_PG_LSECDECRB PP_PG_LSECDECRC PP_PG_LSECDECRD -- PP_PG_LSECDECA[10:0] PP_PG_LSECDECB[10:0] PP_PG_LSECDECC[10:0] PP_PG_LSECDECD[10:0] Agere Systems Inc. 341 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr Symbol 15 0x1780 0x1781 0x1782 0x1783 0x1784 0x1785 0x1786 -- 0x1790 0x1791 0x1792 0x1793 0x1794 0x1795 0x1796 -- 0x17A0 0x17A1 0x17A2 0x17A3 0x17A4 0x17A5 0x17A6 -- 0x17B0 PP_POH_ALMPMR PP_1BRDI_DPMBSR PP_TS1BRDI_DPMBSRA PP_TS1BRDI_DPMBSRB PP_TS1BRDI_DPMBSRC PP_TS1BRDI_DPMBSRD -- One Bit RDI Alarm PM per STS-1 Bytestream A PP_TS1BRDI_DPMBSA[1--12] One Bit RDI Alarm PM per STS-1 Bytestream B PP_TS1BRDI_DPMBSB[1--12] One Bit RDI Alarm PM per STS-1 Bytestream C PP_TS1BRDI_DPMBSC[1--12] One Bit RDI Alarm PM per STS-1 Bytestream D PP_TS1BRDI_DPMBSD[1--12] 14 13 12 11 10 9 Performance Monitoring PP_1BRDI PP_ERDI_ PP_ERDI_ PP_ERDI_ PP_UNEQ _DPM PDPM CDPM SDPM R_ALMPM PP_AIS_A LMPM PP_LOP_ ALMPM Bit Number 8 7 6 5 4 3 2 1 0 One Bit RDI Alarm PM PP_1BRDI_DPMBS[A--D] PP_ERDI_PDPMBSR PP_ERDI_PDPMBSRA PP_ERDI_PDPMBSRB PP_ERDI_PDPMBSRC PP_ERDI_PDPMBSRD -- ERDI Payload Alarm PM per STS-1 Bytestream A PP_TSERDI_PDPMBSA[1--12] ERDI Payload Alarm PM per STS-1 Bytestream B PP_TSERDI_PDPMBSB[1--12] ERDI Payload Alarm PM per STS-1 Bytestream C PP_TSERDI_PDPMBSC[1--12] ERDI Payload Alarm PM per STS-1 Bytestream D PP_TSERDI_PDPMBSD[1--12] ERDI Payload Alarm PM PP_ERDI_PDPMBS[A--D] PP_ERDI_CDPMBSR PP_TSERDI_CDPMBSRA PP_TSERDI_CDPMBSRB PP_TSERDI_CDPMBSRC PP_TSERDI_CDPMBSRD -- ERDI Connectivity Alarm PM per STS-1 Bytestream A PP_TSERDI_CDPMBSA[1--12] ERDI Connectivity Alarm PM per STS-1 Bytestream B PP_TSERDI_CDPMBSB[1--12] ERDI Connectivity Alarm PM per STS-1 Bytestream C PP_TSERDI_CDPMBSC[1--12] ERDI Connectivity Alarm PM per STS-1 Bytestream D PP_TSERDI_CDPMBSD[1--12] ERDI Connectivity Alarm PM PP_ERDI_CDPMBS[A--D] 342 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x17B1 0x17B2 0x17B3 0x17B4 0x17B5 0x17B6 -- 0x17C0 0x17C1 0x17C2 0x17C3 0x17C4 0x17C5 0x17C6 -- 0x17D0 0x17D1 0x17D2 0x17D3 0x17D4 0x17D5 0x17D6 -- 0x17E0 Symbol 15 PP_ERDI_SDPMBSR PP_TSERDI_SDPMBSRA PP_TSERDI_SDPMBSRB PP_TSERDI_SDPMBSRC PP_TSERDI_SDPMBSRD -- ERDI Server Alarm PM per STS-1 Bytestream A PP_TSERDI_SDPMBSA[1--12] ERDI Server Alarm PM per STS-1 Bytestream B PP_TSERDI_SDPMBSB[1--12] ERDI Server Alarm PM per STS-1 Bytestream C PP_TSERDI_SDPMBSC[1--12] ERDI Server Alarm PM per STS-1 Bytestream D PP_TSERDI_SDPMBSD[1--12] 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 ERDI Server Alarm PM PP_ERDI_SDPMBS[A--D] PP_UNEQR_PMBSR PP_TSUNEQR_PMBSRA PP_TSUNEQR_PMBSRB PP_TSUNEQR_PMBSRC PP_TSUNEQR_PMBSRD -- Unequipped Received Alarm PM per STS-1 Bytestream A PP_TSUNEQR_PMBSA[1--12] Unequipped Received Alarm PM per STS-1 Bytestream B PP_TSUNEQR_PMBSB[1--12] Unequipped Received Alarm PM per STS-1 Bytestream C PP_TSUNEQR_PMBSC[1--12] Unequipped Received Alarm PM per STS-1 Bytestream D PP_TSUNEQR_PMBSD[1--12] Unequipped Received Alarm PM PP_UNEQR_PMBS[A--D] PP_AIS_PMBSR PP_TSAIS_PMBSRA PP_TSAIS_PMBSRB PP_TSAIS_PMBSRC PP_TSAIS_PMBSRD -- Alarm Indicator Signal Alarm PM per STS-1 Bytestream A PP_TSAIS_PMBSA[1--12] Alarm Indicator Signal Alarm PM per STS-1 Bytestream B PP_TSAIS_PMBSB[1--12] Alarm Indicator Signal Alarm PM per STS-1 Bytestream C PP_TSAIS_PMBSC[1--12] Alarm Indicator Signal Alarm PM per STS-1 Bytestream D PP_TSAIS_PMBSD[1--12] Alarm Indicator Signal Alarm PM PP_AIS_PMBS[A--D] Agere Systems Inc. 343 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Pointer Processor (PP) (continued) PP Register Map (continued) Table 249. Pointer Processor Register Map (continued) Note: Shading denotes reserved bits. Addr 0x17E1 0x17E2 0x17E3 0x17E4 0x17E5 0x17E6 -- 0x17FF 0x1800 -- 0x182F 0x1830 -- 0x187F 0x1880 -- 0x18AF 0x18B0 -- 0x18FF 0x1900 -- 0x192F 0x1930 -- 0x1947 0x1948 -- 0x195F 0x1960 -- 0x1977 0x1968 -- 0x1FFF Symbol 15 PP_LOP_PMBSR PP_TSLOP_PMBSRA PP_TSLOP_PMBSRB PP_TSLOP_PMBSRC PP_TSLOP_PMBSRD -- Loss of Pointer Alarm PM per STS-1 Bytestream A PP_TSLOP_PMBSA[1--12] Loss of Pointer Alarm PM per STS-1 Bytestream B PP_TSLOP_PMBSB[1--12] Loss of Pointer Alarm PM per STS-1 Bytestream C PP_TSLOP_PMBSC[1--12] Loss of Pointer Alarm PM per STS-1 Bytestream D PP_TSLOP_PMBSD[1--12] 14 13 12 11 10 9 Bit Number 8 7 6 5 4 3 2 1 0 Loss of Pointer Alarm PM PP_LOP_PMBS[A--D] PP_LSECCVP_CPMR[1--48] Time Slots 1, 2, 3, 4, . . ., 48 CV Count PM PP_LSECCVP_CPM[1--48][15:0] -- PP_LSECREIP_CPMR[1--48] Time Slots 1, 2, 3, 4, . . ., 48 REI Count PM PP_LSECREIP_CPM[1--48][15:0] -- RDI, C2 Status PP_TSRDIPR[1--48] Time Slot 1--Time Slot 48 Received RDI Code PP_TS_RRDI[1--48][2:0] Time Slots 1, 3, 5, . . ., 47 Received C2 Byte PP_TSRC2[1, 3, 5, . . ., 47][7:0] Time Slots 2, 4, 6, . . ., 48 Received C2 Byte PP_TSRC2[2, 4, 6, . . ., 48][7:0] PP_TSC2R[1--24] -- PDI Status PP_TSPDIR[1--24] Time Slots 1, 3, 5, . . ., 47 Received PDI Byte PP_TSRPDI[1, 3, 5, . . ., 47][7:0] Time Slots 2, 4, 6, . . ., 48 Received PDI Byte PP_TSRPDI[2, 4, 6, . . ., 48][7:0] -- 344 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) Introduction This section describes the interfaces of the path terminator (PT) block, including the register map description. A block diagram showing the major subblocks is given. The PT has the following subblocks: Receive terminator (RXT) SPE mapper (SPE) Transpose block (TR) Microprocessor interface (PT_MP) PATH TERMINATOR (PT) TO CROSS CONNECT TRANSPOSE (TR) SPE_MAPPER FROM DS3 MAPPER LOOPBACK MPU REGISTER SIGNALS MPU PT_MP FROM CROSS CONNECT RECEIVE TERMINATOR (RXT) TRANSPOSE (TR) TO DS3 MAPPER 5-8706(F)r.3 Figure 38. Path Terminator Block Diagram Agere Systems Inc. 345 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) SPE Mapper PBIP x48 TOH/ POH INSERT x48 B3ERR TIM PLM UNEQ AIS LOP LCD TO CROSS CONNECT TRANSPOSE DS3/E3 MAPPER 4x8 SPE_FIFO DS3 MAPPER 5-8707(F).b Figure 39. Block Diagram of SPE Mapper Block Time-Slot Assignments The required STS-1 time-slot assignments for one STS-48 signal on a 32-bit data bus is summarized in Table 250. The time slots repeat every 12 clock cycles. Table 250. STS-48 Time-Slot Assignments Data Bus D[31:24] D[23:16] D[15:8] D[7:0] Control Port A Port B Port C Port D STS-48--32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->) 1 1* 13* 25* 37* 2 4* 16* 28* 40* 3 7* 19* 31* 43* 4 10* 22* 34* 46* 5 2 14 26 38 6 5 17 29 41 7 8 20 32 44 8 11 23 35 47 9 3 15 27 39 10 6 18 30 42 11 9 21 33 45 12 12 24 36 48 * Indicates valid starting time slots for concatenated signals from STS-3c to STS-48c. 346 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) SPE Mapper (continued) The required STS-1 time-slot assignment for four STS-12 signals on a 32-bit data bus is summarized in Table 251. The time slots repeat every 12 clock cycles. Each input stream is independent of the others. Table 251. STS-12 Time-Slot Assignments Data Bus D[31:24] D[23:16] D[15:8] D[7:0] Control Port A Port B Port C Port D STS-12--32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->) 1 1* 1* 1* 1* 2 4* 4* 4* 4* 3 7* 7* 7* 7* 4 10* 10* 10* 10* 5 2 2 2 2 6 5 5 5 5 7 8 8 8 8 8 11 11 11 11 9 3 3 3 3 10 6 6 6 6 11 9 9 9 9 12 12 12 12 12 * Indicates valid starting time slots for concatenated signals from STS-3c to STS-12c. The required STS-1 time-slot assignment for four STS-3 signals on a 32-bit data bus is summarized in Table 252. The time slots repeat three additional clock cycles. Each input stream is independent of the others. Table 252. STS-3 Time-Slot Assignments Data Bus D[31:24] D[23:16] D[15:8] D[7:0] Control Port A Port B Port C Port D STS-12--32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->) 1 1* 1* 1* 1* 2 1* 1* 1* 1* 3 1* 1* 1* 1* 4 1* 1* 1* 1* 5 2 2 2 2 6 2 2 2 2 7 2 2 2 2 8 2 2 2 2 9 3 3 3 3 10 3 3 3 3 11 3 3 3 3 12 3 3 3 3 * Indicates valid starting time slots for concatenated signals from STS-1c to STS-3c. Any combination of STS up to STS-48c can be generated using up to 16-logical channels. Valid starting positions are indicated by an *. Agere Systems Inc. 347 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) SPE Mapper (continued) Example of Channel-to-Time-Slot Mapping for a 16-Channel Configuration with Channel STS Sizes Indicated in Table 254 Table 253. Sequence Register Map TS[0--23]_PM_[A--D] Sequence Register Map TS[0--23]_PM_[A--D] Slot # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 ch_id Slot # ch_id Slot # ch_id Slot # ch_id 0 10 11 11 1 10 11 11 2 10 11 11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 3 10 11 11 4 10 11 11 5 10 11 11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 6 10 11 11 7 10 11 11 8 10 11 11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 9 10 11 11 9 10 11 11 9 10 11 11 Table 254. Logical 16-Channel Configuration Concatenation Register Map CH[0--15]_NC Logical 16-Channel Configuration Concatenation Register Map CH[0--15]_NC ch_id ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 348 Size 1 1 1 1 1 1 1 1 1 3 12 24 -- -- -- -- Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) Supported SPE Formats Direct Mapping into STS-1 SPE Figure 40 shows direct mapping into STS-1 SPE, as per GR-253 (R3-6). This mapping can be set per time slot (PT_TX_STS1_[A--D] (Table 292)). 1 COL 1 COL 28 COL'S 28 COL'S 1 COL 28 COL'S STUFF PAYLOAD PAYLOAD STUFF POH PAYLOAD 5-8298(F) Figure 40. Direct Mapping into STS SPE STS-Nc SPE Figure 41 shows the structure of an STS-Nc SPE, as per GR-353 (R3-9). N is valid for N = 3 to 48, where N is a multiple of 3. N/3-1 COL. FIXED STUFF (3N - 9 BYTES) STS POH (9 BYTES) 9 ROWS STS-NC PAYLOAD CAPACITY (N x 780 BYTES) N x 87 COLUMNS 5-8299(F)r.2 Figure 41. STS-Nc SPE Agere Systems Inc. 349 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) Supported SPE Formats (continued) Asynchronous Mapping of DS3 (44.736 Mbits/s) Payload into STS-1 The DS3 frame insertion into an SPE is done as per GR253, section 3.4.2.1. The overhead communication bits (O bits) and R bits are programmable to either 0 or 1 (PT_TX_MODE[7] (Table 263)). The stuff opportunity bit (S bit) will contain a data bit every third subframe, starting on the first subframe. During a row when the S bit is data the 5 C bits must be set to 1; otherwise, if the S bit is a justification bit, the 5 C bits are set to zero. A justification will always set the S bit to zero. The DS3 rate is 44,736,000 bits/s. This is equal to 5592 bits per 125 s frame. The mapping into DS3 gives 5589 bits per 125 s frame. Therefore, three extra bits are added per frame using the stuff opportunity bits. 28 BYTES R C1 25 I R C1 R C1 R C1 R C1 R C1 R C1 R C1 R C1 25 I 25 I 25 I 25 I 25 I 25 I 25 I 25 I FIXED STUFF 28 BYTES I 25 I I I I I I I I I 25 I FIXED STUFF 25 I 25 I 25 I 25 I 25 I 25 I 25 I 28 BYTES I 25 I I I I I I I I I 25 I 25 I 25 I 25 I 25 I 25 I 25 I 25 I 5-8300(F) R R R SPE POH R R R R R R Note: I = ii ii ii ii R = rr rr rr rr C1 = rr ci ii ii C2 = cc rr rr rr C3 = cc rr oo rs R C2 R C2 R C2 R C2 R C2 R C2 R C2 R C2 R C2 R C3 R C3 R C3 R C3 R C3 R C3 R C3 R C3 R C3 i = info bit. r = fixed stuff bit. c = stuff control bit. s = stuff opportunity bit. o = overhead common bit. Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE 350 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) Supported SPE Formats (continued) Asynchronous Mapping of E3 (34.368 Mbits/s) Payload into STS-1 The E3 frame insertion into an SPE is done as per ITU-T G.707, Section 10.1.2.2. The r bits are programmably set to either 0 or 1. The E3 rate is 34.368 Mbits/s. This is equal to 4293 bits per 125 s frame. The mapping into E3 gives 4296 bits per 125 s frame. Therefore, three extra bits must be added per frame using the stuff opportunity bits. The stuff opportunity bit S2 will always contain a data bit (i.e., every third subframe). Thus, C2 will always be set to 1. S1 will always contain a stuff bit, thus C1 will always be set to 0. 28 bytes R 3I R 3I R 3I R 3I R R 3I R 3I R 2I R 3I R 3I R 3I R 3I R R 3I R 3I R 2I FIXED STUFF R 3I R 3I R 3I R 3I R R 3I R 3I R 2I SPE POH R 3I R 3I R 3I R 3I R R 3I R 3I R 2I R 3I R 3I R 3I R 3I R R 3I R 3I R 2I R 3I R 3I R 3I R 3I R R 3I R 3I R 2I R 3I R 3I R 3I R 3I R R 3I R 3I R 2I R 3I R 3I R 3I R 3I R R 3I R 3I R 2I R 3I R 3I R 3I R 3I R R 3I R 3I R 2I 28 bytes I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I FIXED STUFF I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I I R 3I R 3I R C 3I R 3I R 3I R 3I R I 28 bytes 2I R R 3I R 3I R 3I R 3I R 3I R C 2I R R 3I R 3I R 3I R 3I R 3I R C 2I R R 3I R 3I R 3I R 3I R 3I R C 2I R R 3I R 3I R 3I R 3I R 3I R C 2I R R 3I R 3I R 3I R 3I R 3I R C 2I R R 3I R 3I R 3I R 3I R 3I R C 3I 3I 3I 3I 3I 3I 1623(F)r.1 2I R R 3I R 3I R 3I R 3I R 3I R R A B I 2I R R 3I R 3I R 3I R 3I R 3I R R A B I 2I R R 3I R 3I R 3I R 3I R 3I R R A B I Note: I = ii ii ii ii where i = information bit. R = rr rr rr rr where r = fixed stuff bit. C = rr rr rr c1c2 where c1 and c2 = stuff control bits. A = rr rr rr rr rs1 where s1 = first stuff opportunity bit. B = s2 ii ii ii i where s2 = second stuff opportunity bit. Figure 43. Asynchronous Mapping of E3 into STS-1 SPE Agere Systems Inc. 351 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) SPE Mapper Architecture SPE Generator The SPE generator block has the following functions: this block will send a complete frame with all the transport overhead bytes set to the appropriate default value based on the rate mode (PT_TX_MODE[4:3] (Table 263)) input signal and the H1, H2, H3, POH bytes, and SPE bytes set correctly. The SPE generator will accept data with the correct byte interleaving for the type of signal provisioned from the data engine. The SPE generator operates in three timing modes: one STS-48 signal, four STS-12 signals, or four STS-3 signals. Shown in Figure 44 below is the frame structure of the data sent out of the SPE mapper when in STS-48 mode. This figure indicates the various TOH locations, and the SPE location numbers. Each location consists of 48 octets, whose numbering is also indicated (see Table 250, STS-48 Time-Slot Assignments on page 346 for more information on how the 48 octets are mapped in time and space). When the SPE generator operates in STS-12 mode, the frame structure is shown in Figure 45, STS-12 Frame Structure on page 353. This figure indicates the various TOH locations and the SPE location numbers. Each location consists of 12 octets, whose numbering is also indicated (see Table 251, STS-12 Time-Slot Assignments on page 347 for more information on how the 12 octets are mapped in time and space). A1 (48 OCTETS TOTAL) 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 ... 27 30 33 36 39 42 45 48 A1 A2 J0 522 523 781 782 H1 H2 H3 0 1 520 521 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 ... 27 30 33 36 39 42 45 48 SPE LOCATION 521 (48 OCTETS TOTAL) 5-8301(F) Figure 44. STS-48 Frame Structure 352 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) SPE Mapper Architecture (continued) A1 (12 OCTETS TOTAL) 1 4 7 10 2 5 8 11 3 6 9 12 A1 A2 J0 522 523 781 782 H1 H2 H3 0 1 520 521 1 4 7 10 2 5 8 11 3 6 9 12 SPE LOCATION 521 (12 OCTETS TOTAL) 5-8303(F) Figure 45. STS-12 Frame Structure H1, H2 Pointer Value The generated H1, H2 value is determined by the time-slot configuration settings (PT_TX_Cnfg_[A--D] high/low (Table 293--Table 300). There are 48 settings, one per STS-48 location (in STS-12, the first 12 are used, and in STS-3, the first 3 are used). If the setting indicates normal pointer (00 encoding), an H1 value of 8'b0110_ss_10, and an H2 value of 8'b0000_1010 is sent, where ss is dependent on the SS setting configuration (there are 2 bits per channel, used to indicate SS bit insertion, 00 = SONET, 11 = SDH). This corresponds to a normal NDF, and an offset of 522 decimal. If the settings indicates concatenation (01 encoding), an H1 value of 8'b1001_ss_11 and an H2 value of 8'b1111_1111 is sent. If the settings indicates unequipped (10 encoding), an H1 value of 8'b0110_ss_00 and an H2 value of 8'b0000_0000 is sent. Additionally, the entire corresponding payload is set to 8'h00. If the settings indicate AIS (11 encoding), an H1 value of 8'b1111_11_11 and an H2 value of 8'b1111_1111 is sent. Agere Systems Inc. 353 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) SPE Mapper Architecture (continued) Selective STS-1 Path Insert Functions Sixteen path overheads can be inserted (one per channel). The valid starting locations for an STS-Nc are shown in Table 250, STS-48 Time-Slot Assignments on page 346, Table 251, STS-12 Time-Slot Assignments on page 347, and Table 252, STS-3 Time-Slot Assignments on page 347. J1 Byte Trace. The insertion of the path trace for a selected STS-1 for both SONET and SDH systems is provided. For SONET, a 64-byte microprocessor registers are provisioned to transmit the 64-byte path trace message. For SDH, a repeated 16-byte message is inserted from the 64-byte path trace microprocessor registers. Note: For simplicity, the 16-byte SDH message is repeated four times in the 64-byte path trace microprocessor registers. A control bit is used to start the insertion of the path trace message; otherwise, all 0s are inserted into the outgoing J1 byte. B3 Insertion. The SPE mapper calculates the BIP-8 even parity over all bits (783 bytes for an STS-1 SPE or Nx783 bytes for an STS-Nc SPE), regardless of any pointer adjustments of the previous STS SPE before scrambling, and inserts in the B3 byte location of the current STS SPE before scrambling. The calculated B3 values can be inverted per time slot for test purposes (PT_TX_RW1_[0--47][12] (Table 280)). Additionally, the B3 values can be disabled (i.e., forced to 0) per time slot for testing purposes (PT_TX_RW1_[0--47][14]). C2: Path Signal Label. The C2 byte is inserted per channel (PT_TX_RW2_[0--15][7:0] (Table 281)). If the unequipped value of 0x00 is programmed, the SPE mapper will generate an all 0s SPE with a valid payload pointer (H1 = 0110_SS00, H2 = 0000_0000, H3 = 0000_0000) and B3 value before scrambling. Table 255 shows the various codes for C2 as per (GR-253, Table 3.2). Table 255. C2 Path Signal Label Code 0x00 0x01 0x02 0x03 0x04 0x12 0x13 0x14 0x15 0x16 Content of the STS SPE Unequipped Equipped--Nonspecific Payload VT-Structured STS-1 SPE Locked VT Mode Asynchronous Mapping DS3 Asynchronous Mapping for DS4NA Mapping for ATM Mapping for DQDB Asynchronous Mapping for FDDI Mapping for HDLC--PPP Support Yes Yes No No No No Yes No No Yes 354 Agere Systems Inc. Data Sheet August 19, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) SPE Mapper Architecture (continued) G1: Path Status. The G1 byte is used to convey path condition and performance parameters back to the far end. G1[7:4]--known as the remote error indication-path (REI-P) are used to report the number of B3 BIP-8 errors seen by the current received frames. The valid values for these 4 bits are 0000--1000. This 4-bit REI-P can be software overridden, on a per-channel basis by setting a control bit (PT_TX_RW1_[47--0][4] (Table 280)) and provisioning the value (PT_TX_RW1_[47--0][3:0]). G1[3:1]--known as the path remote defect indication (RDI-P) are used to report the received defects as shown in Table 256. Note that when detecting two or more of the listed defects, the block generates the higher-priority RDI-P enhanced code based on the priorities listed in the table. It is required to generate the RDI-P signal for at least 20 frames before changing the value or terminating the generation. A 3-bit state is provided to monitor the status of RDI-P insertion (PT_TX_TS_[A--D][0--2] (Table 270--Table 272)). Each time this value changes, a delta bit is set (PT_TX_TS_DELTA[A--D][11:0]D (Table 268), PT_TX_TS_MASK[A--D][11:0]M (Table 262)): -- Hardware Control. The SPE mapper receives from the receive pointer interpreter four signals, on a per-port basis, used to configure the RDI-P bits. These are AIS, LOP, UNEQUIP, TIM_P (i.e., trace mismatch), and PLM. Additionally, the SPE mapper receives a loss of cell delineation (LCD) signal on a per-port basis, from the receive data engine processor. Each contribution to the generation of an RDI-P failure can be inhibited from contributing to the RDI-P generation, on a per time-slot basis. The SPE mapper must be provisioned to generate a 1-bit RDI-P or enhanced RDI-P on a per time-slot basis (PT_TX_RW1_[47--0][13]). -- Software Control. Insertion of a user-defined value is provided by setting control bit (PT_TX_RW1_[47--0][8]) and provisioning register bits (PT_TX_RW1_[47--0][7:5]) on a per time-slot basis. -- Trace Mismatch (TIM-P). As per ANSI T1.231, the TIM-P is supported via a programmable bit on a per timeslot basis. -- Enhanced or 1-bit RDI-P Mode. When PT_TX_RW1_[47--0][13] is set to 0, one bit RDI-P mode is selected; G1[3] = 1 when either AIS, LOP, UNEQUIP, TIM_P, or PLM is detected; otherwise, when no defects are detected, set to 0. Also, when 1-bit RDI-P mode is selected, G1[2:1] are undefined in GR-253, so these bits will be used to indicated SONET or SDH mode. Therefore, when PT_TX_MODE[0] (Table 263) = 0, G1[2:1] = 00. But in SDH_MODE, (PT_TX_MODE][0] = 1), G1[2:1] = 11. G1[0]--This is also set to 1 if SDH_MODE is set (PT_TX_MODE[0]); otherwise, set to 0. Table 256. G1 RDI-P Codes G1[3:1] Priority of Enhanced RDI-P Codes Not applicable Not applicable 4 3 1 2 Trigger Interpretation 0xx* 1xx* 001 010 101 110 No defects AIS-P, LOP-P, UNEQ-P No defects PLM-P, LCD-P AIS-P, LOP-P UNEQ-P, TIM-P No RDI-P defect RDI-P (1-bit RDI-P) No RDI-P defects RDI-P payload defect RDI-P server defect RDI-P connectivity defect * These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 2 and 1 must be set to the same value, and should be set to 00. This code is transmitted by STS PTE that support enhanced RDI-P. Agere Systems Inc. 355 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) Transpose Block Reorder STS-48 time-slot assignments for output processing. Input order is as shown in Table 257 below. Output order as shown in Table 250, STS-48 Time-Slot Assignments on page 346. It is recommended that the time slots be configured in SONET order (Table 257), transposed in the transmit direction, and sent out in time order (Table 250). In the receive direction, time slots can be received in time order and then transposed back into SONET order. Table 257. STS-48 Time-Slot Internal Ordering Data Bus D[31:24] D[23:16] D[15:8] D[7:0] Control Port A Port B Port C Port D STS-48--32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->) 1 1* 4* 7* 10* 2 13* 16* 19* 22* 3 25* 28* 31* 34* 4 37* 40* 43* 46* 5 2 5 8 11 6 14 17 20 23 7 26 29 32 35 8 38 41 44 47 9 3 6 9 12 10 15 18 21 24 11 27 30 33 36 12 39 42 45 48 * Indicates valid starting time slots for concatenated signals from STS-3c to STS-48c. 356 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions This section describes the MPU accessible registers in the PT block. Global Registers Table 258. (PT_TX_VERSION), Version Control (RO) Address 0x4000 Bit 15:8 7:0 Name -- VERSION Reserved. Version Number. Indicates version number of PT block. Function Reset Default -- 0x01 Table 259. (PT_TX_CH_INT), Tx Channel Composite Interrupt (RO) Address 0x4001 Bit 15:0 Name Ch_Int Function Transmit Channel Interrupt. Active-high interrupt bit on a per-channel basis. These bits are the ORing of all event and delta bits associated with a particular transmit channel. An event or delta bit contribution can be inhibited from contributing to the interrupt by setting the appropriate mask bit. Reset Default 0x0000 Table 260. (PT_TX_TS_[A--D]_INT), Tx Time-Slot Composite Interrupt (RO) Address Bit Names -- TX_TS_A_Int TX_TS_B_Int TX_TS_C_Int TX_TS_D_Int Reserved. Transmit Time-Slot Interrupt. Active-high interrupt, per time slot for slices A, B, C, and D. Function Reset Default 0x0000 0x4004-- 15:12 0x4007 11:0 Table 261. (PT_TX_CH_INTMASK), Tx Channel Composite Interrupt Mask (R/W) Address 0x4008 Bit 15:0 Name Ch[15:0] Function Composite Channel Interrupt Mask. If set, the interrupt will not occur for that channel. Reset Default 0xFFFF Table 262. (PT_TX_TS[A--D]_INTMASK), Tx Time-Slot Composite Interrupt Mask (R/W) Address Bit Name -- TS[11:0] Reserved. Composite Interrupt Mask. If set, the interrupt will not occur, per time slot, for slices A, B, C, and D. Function Reset Default 0xF 0xFFF 0x400B-- 15:12 0x400E 11:0 Agere Systems Inc. 357 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 263. (PT_TX_MODE), Mode (R/W) Address 0x400F Bit 15 Name STUFFBYTE_ FORCE Function Stuff Byte Force. If set to 0, the default is to put stuff bytes in the first four STS time slots of column 4. This is the recommended setting. If set to 1, stuff byte locations are programmed using the Stuffbyte_Config register. This may be used when configuring an STS-Nc, where N is not a multiple of 3. 14 Stuffbyte_1or0 Stuff Byte 1 or 0. 0 = All stuff bytes are set to 0 (i.e., SONET). 1 = All stuff bytes are set to 1 (i.e., SDH). 13 RX_TRANSPOSE_ Rx Transpose Enable. ENB 0 = Transpose disabled. 1 = Transpose enabled. TX_TRANSPOSE_ Tx Transpose Enable. ENB 0 = Transpose disabled. 1 = Transpose enabled. -- DS3_RO_VALUE CORWN Reserved. For Internal Use Only. DS3 RO Bit Values. This is the value that all R and O bits will be set to in DS3 mapped frames. Clear-On-Read/Write. 0 = Clear-on-write, writing a COW register will clear whatever bits were written with 1. 1 = Clear-on-read, reading a COR register will clear the entire register. 5 POF_ENB Packet-Over-Fiber Enable. 0 = POF disabled. 1 = POF enabled. 4:3 RATE_MODE Rate Mode. 00 = STS-3. 01 = STS-12. 10 = STS-48. 11 = STS-1. 2 1 0 LOOP_MODE -- SDH_MODE Loopback Mode. 1 = Loopback Tx output data to Rx input data. Reserved. SDH Mode. 0 = SONET; 1 = SDH. 0 0 0 0 0 0 0 Reset Default 0 12 0 11:8 7 6 -- 0 0 358 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 264. (PT_TX_BANKAorB), Tx_BANKAorB (R/W) Address 0x4010 Bit 15:1 0 Name -- BANKAorB_SEL Reserved. Tx BANKAorB_SEL Register. 0 = Bank A is selected for sequence map. 1 = Bank B is selected for sequence map. Table 265. (PT_TX_SCRATCH), SCRATCH (R/W) Address 0x4011 Bit 15:0 Name SCRATCH Function Tx Scratchpad Register. Diagnostic register used by microprocessor. Has no effect on the PT function. Reset Default 0x0000 Function Reset Default -- 0 Table 266. (PT_TX_SOFTRST), Tx Channel FIFO Reset (R/W) Address 0x4013 Bit 15:0 Name SOFTRST Function Channel FIFO, Soft Reset. Software reset is necessary whenever a channel is initialized, after all other setups have been performed. A software reset should be performed at the end of configuration for a channel. To perform this reset, write a 1 to reset and then write a 0 to release the reset. Reset Default 0 Agere Systems Inc. 359 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 267. (PT_TX_CH_DELTA [0--15]), Tx Channel Delta/Event (COR/W) Address 0x4016-- 0x4025 Bit 15:2 1 0 Name -- FIFO emptyD FIFO FullD Reserved. Delta Bit Indicating Change of Associated SPE FIFO Empty Status. Delta Bit Indicating Change of Associated SPE FIFO Full Status. Function Reset Default 0 1 0 Table 268. (PT_Tx_TS_[A--D]_Delta), Tx Delta/Event Register (COR/W) Address Bit Name -- RDIPD Reserved. Delta Bit Indicating Change of RDI-P, per Time Slot. Function Reset Default 0 0 0x4046-- 15:12 0x4049 11:0 Table 269. (PT_Tx_CH_Status_[0--15]), Transmit Status Register (RO) Address 0x404A-- 0x4059 Bit 15:2 1 0 Name -- FIFO empty FIFO Full Reserved. FIFO Empty Status. A 1 indicates that the SPE FIFO is empty. A 0 indicates that there is data in the FIFO. FIFO Full Status. A 1 indicates that the SPE FIFO is full. Function Reset Default 0 1 0 360 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 270. (PT_TX_TS_[A--D]0_Status), Transmit Status Register (RO) Address 0x407A, 0x407D, 0x4080, 0x4083 Bit 15 14:12 11 10:8 7 6:4 3 2:0 Name -- RDIP3 -- RDIP2 -- RDIP1 -- RDIP0 Function Reserved. RDIP Status, Time Slot 3. Reserved. RDIP Status, Time Slot 2. Reserved. RDIP Status, Time Slot 1. Reserved. RDIP Status, Time Slot 0. 0xx = No defects. 1xx = AIS, LOP, or UNEQ. 001 = No defects. 010 = PLM, LCD. 101 = AIS, LOP. 110 = UNEQ, TIM. Table 271. (PT_TX_TS_[A--D]1_Status), Transmit Status Register (RO) Address 0x407B, 0x407E, 0x4081, 0x4084 Bit 15 14:12 11 10:8 7 6:4 3 2:0 Name -- RDIP7 -- RDIP6 -- RDIP5 -- RDIP4 Function Reserved. RDIP Status, Time Slot 7. Reserved. RDIP Status, Time Slot 6. Reserved. RDIP Status, Time Slot 5. Reserved. RDIP Status, Time Slot 4. Reset Default 0 000 0 000 0 000 0 000 Reset Default 0 000 0 000 0 000 0 000 Table 272. (PT_TX_TS_[A--D]2_Status), Transmit Status Register (RO) Address 0x407C, 0x407F, 0x4082, 0x4085 Bit 15 14:12 11 10:8 7 6:4 3 2:0 Name -- RDIP11 -- RDIP10 -- RDIP9 -- RDIP8 Function Reserved. RDIP Status, Time Slot 11. Reserved. RDIP Status, Time Slot 10. Reserved. RDIP Status, Time Slot 9. Reserved. RDIP Status, Time Slot 8. Reset Default 0 000 0 000 0 000 0 000 Agere Systems Inc. 361 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 273. (PT_Tx_CH_Mask_[0--15]), Tx Channel Mask Register (R/W) Address 0x4086-- 0x4095 Bit 15:2 1 0 Name -- FIFO empty FIFO Full Reserved. SPE FIFO Empty Status Mask, Per Channel. A 1 will mask the associated delta bit from contributing to the interrupt signal. SPE FIFO Full Status Mask, Per Channel. A 1 will mask the associated delta bit from contributing to the interrupt signal. Function Reset Default 0xFFFF Table 274. (PT_Tx_TS_[A--D]_Mask), Tx Mask Register (COR/W) Address Bit Name -- RDIPM[11:0] Reserved. RDI-P Status Mask, per Time Slot. Function Reset Default 0 0 0x40B6-- 15:12 0x40B9 11:0 362 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 275. (PT_Tx_Mask_A_[1--6]), Transmit Provisioning Register (R/W) Address Bit Name -- RDIPM_TIM A[1, 3, 5, 7, 9, 11] RDIPM_LCD A[1, 3, 5, 7, 9, 11] RDIPM_PLM A[1, 3, 5, 7, 9, 11] RDIPM_UNEQ A[1, 3, 5, 7, 9, 11] RDIPM_LOP A[1, 3, 5, 7, 9, 11] RDIPM_AIS A[1, 3, 5, 7, 9, 11] -- RDIPM_TIM A[0, 2, 4, 6, 8, 10] RDIPM_LCD A[0, 2, 4, 6, 8, 10] RDIPM_PLM A[0, 2, 4, 6, 8, 10] RDIPM_UNEQ A[0, 2, 4, 6, 8, 10] RDIPM_LOP A[0, 2, 4, 6, 8, 10] RDIPM_AIS A[0, 2, 4, 6, 8, 10] Reserved. Mask TIMP, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Reserved. Mask TIMP, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Function Reset Default 0xFFFF 0x4112-- 15:14 0x4117 13 12 11 10 9 8 7:6 5 4 3 2 1 0 Agere Systems Inc. 363 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 276. (PT_Tx_Mask_B_[1--6]), Transmit Provisioning Register (R/W) Address Bit Name -- RDIPM_TIM B[1, 3, 5, 7, 9, 11] RDIPM_LCD B[1, 3, 5, 7, 9, 11] RDIPM_PLM B[1, 3, 5, 7, 9, 11] RDIPM_UNEQ B[1, 3, 5, 7, 9, 11] RDIPM_LOP B[1, 3, 5, 7, 9, 11] RDIPM_AIS B[1, 3, 5, 7, 9, 11] -- RDIPM_TIM B[0, 2, 4, 6, 8, 10] RDIPM_LCD B[0, 2, 4, 6, 8, 10] RDIPM_PLM B[0, 2, 4, 6, 8, 10] RDIPM_UNEQ B[0, 2, 4, 6, 8, 10] RDIPM_LOP B[0, 2, 4, 6, 8, 10] RDIPM_AIS B[0, 2, 4, 6, 8, 10] Reserved. Mask TIMP, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Reserved. Mask TIMP, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Function Reset Default 0xFFFF 0x4118-- 15:14 0x411D 13 12 11 10 9 8 7:6 5 4 3 2 1 0 364 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 277. (PT_Tx_Mask_C_[1--6]), Transmit Provisioning Register (R/W) Address Bit Name -- RDIPM_TIM C[1, 3, 5, 7, 9, 11] RDIPM_LCD C[1, 3, 5, 7, 9, 11] RDIPM_PLM C[1, 3, 5, 7, 9, 11] RDIPM_UNEQ C[1, 3, 5, 7, 9, 11] RDIPM_LOP C[1, 3, 5, 7, 9, 11] RDIPM_AIS C[1, 3, 5, 7, 9, 11] -- Reserved. Mask TIMP, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Reserved. Function Reset Default 0xFFFF 0x411E-- 15:14 0x4123 13 12 11 10 9 8 7:6 5 RDIPM_TIM Mask TIMP, slice C time slots [0, 2, 4, 6, 8, 10], from contribC[0, 2, 4, 6, 8, 10] uting to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. RDIPM_LCD Mask LCD, slice C time slots [0, 2, 4, 6, 8, 10], from contributC[0, 2, 4, 6, 8, 10] ing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. RDIPM_PLM Mask PLM, slice C time slots [0, 2, 4, 6, 8, 10], from contribC[0, 2, 4, 6, 8, 10] uting to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. RDIPM_UNEQ Mask UNEQ, slice C time slots [0, 2, 4, 6, 8, 10], from conC[0, 2, 4, 6, 8, 10] tributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. RDIPM_LOP Mask LOP, slice C time slots [0, 2, 4, 6, 8, 10], from contributC[0, 2, 4, 6, 8, 10] ing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. RDIPM_AIS Mask AIS, slice C time slots [0, 2, 4, 6, 8, 10], from contributC[0, 2, 4, 6, 8, 10] ing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. 4 3 2 1 0 Agere Systems Inc. 365 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 278. (PT_Tx_Mask_D_[1--6]), Transmit Provisioning Register (R/W) Address Bit Name -- RDIPM_TIM D[1, 3, 5, 7, 9, 11] RDIPM_LCD D[1, 3, 5, 7, 9, 11] RDIPM_PLM D[1, 3, 5, 7, 9, 11] RDIPM_UNEQ D[1, 3, 5, 7, 9, 11] RDIPM_LOP D[1, 3, 5, 7, 9, 11] RDIPM_AIS D[1, 3, 5, 7, 9, 11] -- RDIPM_TIM D[0, 2, 4, 6, 8, 10] RDIPM_LCD D[0, 2, 4, 6, 8, 10] RDIPM_PLM D[0, 2, 4, 6, 8, 10] RDIPM_UNEQ D[0, 2, 4, 6, 8, 10] RDIPM_LOP D[0, 2, 4, 6, 8, 10] RDIPM_AIS D[0, 2, 4, 6, 8, 10] Reserved. Mask TIMP, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Reserved. Mask TIMP, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P. Mask LCD, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P. Mask PLM, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P. Mask UNEQ, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable UNEQ from contributing to RDI-P. Mask LOP, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P. Mask AIS, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P. Function Reset Default 0xFFFF 0x4124-- 15:14 0x4129 13 12 11 10 9 8 7:6 5 4 3 2 1 0 366 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 279. (PT_Tx_RW4_[0--15]), Transmit Provisioning Register 4 (R/W) Address 0x4132-- 0x4141 Bit 15:8 7:0 Name Z4_Byte Z3_Btye Function Value of Z4 byte to insert. Value of Z3 byte to insert. Reset Default 0x0000 Table 280. (PT_Tx_RW1_[0--47]), Transmit Provisioning Register, Per Time Slot (R/W) Note: RW1_[0] is slice A, time slot 0; RW1_[47] is slice D, time slot 11. Address 0x4142-- 0x4171 Bit 15 14 13 12 11:9 8 7:5 4 3:0 Name -- B3_Disable RDIP_Enh_Mode B3_Invert -- RDIP_Force RDIP_Bits REIP_Force REIP_Bits Reserved. 1 = B3 POH byte is set to 0. 0 = RDI_P 1-bit mode. 1 = RDI_P enhanced mode. 1 = Invert B3 POH byte. Reserved. When RDIP_Force = 1, override RDI_P value with RDIP_Bits. When REIP_Force = 1, override REI_P value with REIP_Bits. Function Reset Default 0x0000 Table 281. (PT_Tx_RW2_[0--15]), Transmit Provisioning Register, Per Channel (R/W) Address Bit Name -- ss_bits -- J1_enb C2_Byte Reserved. ss value (i.e., H1[3:2]). Reserved. 1 = Enable J1 message. Value of C2 byte to insert. Function Reset Default 0 0 0 0 0 0x4172-- 15:14 0x4181 13:12 11:9 8 7:0 Table 282. (PT_Tx_RW3_[0--15]), Transmit Provisioning Register 3 (R/W) Address 0x4182-- 0x4191 Bit 15:8 7:0 Name Z5_Byte H4_Byte Function Value of Z5 byte to insert. Value of H4 byte to insert. Reset Default 0x0000 Agere Systems Inc. 367 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 283. (PT_Tx_alarm_[A--D]_[1]]), TX Alarm Mapper Register 1 (R/W) Note: The Rx alarm addresses per time slot are slice A = 0--11, B = 12--23, C = 24--35, D = 36--47. Address Bit Name -- sel_alarm1 Reserved. Rx Alarm Which Maps to Slot 1. Function Reset Default 0x0 A: 0x01, B: 0x0D, C: 0x19, D: 0x25 0x0 A: 0x00, B: 0x0C, C: 0x18, D: 0x24 0x4192-- 15:14 0x4195 13:8 7:6 5:0 -- sel_alarm0 Reserved. Rx Alarm Which Maps to Slot 0. Table 284. (PT_Tx_alarm_[A--D]_[2]]), TX Alarm Mapper Register 2 (R/W) Note: The Rx alarm addresses per time slot are slice A = 0--11, B = 12--23, C = 24--35, D = 36--47. Address Bit Name -- sel_alarm3 Reserved. Rx Alarm Which Maps to Slot 3. Function Reset Default 0x0 A: 0x03, B: 0x0F, C: 0x01B, D: 0x27 0x0 A: 0x02, B: 0x0E, C: 0x1A, D: 0x26 0x4196-- 15:14 0x4199 13:8 7:6 5:0 -- sel_alarm2 Reserved. Tx Alarm Which Maps to Slot 2. 368 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 285. (PT_Tx_alarm_[A--D]_[3]]), TX Alarm Mapper Register 3 (R/W) Note: The Rx alarm addresses per time slot are slice A = 0--11, B = 12--23, C = 24--35, D = 36--47. Address Bit Name -- sel_alarm5 Reserved. Rx Alarm Which Maps to Slot 5. Function Reset Default 0x0 A: 0x05, B: 0x11, C: 0x1D, D: 0x29 0x0 A: 0x04, B: 0x10, C: 0x1C, D: 0x28 0x419A-- 15:14 0x419D 13:8 7:6 5:0 -- sel_alarm4 Reserved. Rx Alarm Which Maps to Slot 4. Table 286. (PT_Tx_alarm_[A--D]_[4]]), TX Alarm Mapper Register 4 (R/W) Note: The Rx alarm addresses per time slot are slice A = 0--11, B = 12--23, C = 24--35, D = 36--47. Address Bit Name -- sel_alarm7 Reserved. Rx Alarm Which Maps to Slot 7. Function Reset Default 0x0 A: 0x07, B: 0x13, C: 0x1F, D: 0x2B 0x0 A: 0x06, B: 0x12, C: 0x1E, D: 0x2A 0x419E-- 15:14 0x41A1 13:8 7:6 5:0 -- sel_alarm6 Reserved. Rx Alarm Which Maps to Slot 6. Agere Systems Inc. 369 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 287. (PT_Tx_alarm_[A--D]_[5]]), TX Alarm Mapper Register 5 (R/W) Note: The Rx alarm addresses per time slot are slice A = 0--11, B = 12--23, C = 24--35, D = 36--47. Address Bit Name -- sel_alarm9 Reserved. Rx Alarm Which Maps to Slot 9. Function Reset Default 0x0 A: 0x09, B: 0x15, C: 0x21, D: 0x2D 0x0 A: 0x08, B: 0x14, C: 0x20, D: 0x2C 0x41A2-- 15:14 0x41A5 13:8 7:6 5:0 -- sel_alarm8 Reserved. Rx Alarm Which Maps to Slot 8. Table 288. (PT_Tx_alarm_[A--D]_[6]]), TX Alarm Mapper Register 6 (R/W) Note: The Rx alarm addresses per time slot are slice A = 0--11, B = 12--23, C = 24--35, D = 36--47. Address Bit Name -- sel_alarm11 Reserved. Rx Alarm Which Maps to Slot 11. Function Reset Default 0x0 A: 0x0B, B: 0x17, C: 0x23, D: 0x2F 0x0 A: 0x0A, B: 0x16, C: 0x22, D: 0x2E 0x41A6-- 15:14 0x41A9 13:8 7:6 5:0 -- sel_alarm10 Reserved. Rx Alarm Which Maps to Slot 10. 370 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 289. (PT_Tx_RW5_[0--15]), Transmit Provisioning Register 5 (R/W) Address Bit Name -- FIFO_Over_Value Reserved. Channel FIFO Overthreshold Value. When the SPE FIFO is over threshold, backpressure will be sent upstream to the DS3 block to prevent an overflow. Backpressure will be released once the SPE FIFO has less words than the overthreshold value. This value should always be programmed to 0x16. Note: The reset default value of 0x18 needs to be overwritten with 0x16 after powerup. 7:5 4:0 -- Reserved. FIFO_Under_Value Channel FIFO Underthreshold Value. When the SPE FIFO is underthreshold, the FIFO will not be read. This allows the FIFO to fill up to the underthreshold value before being read after initialization. This value should always be programmed to 0x02. Table 290. (PT_Tx_TIMP_[A--D]), TX TIMP Alarm Register, Per Time Slot (R/W) Address Bit Name -- TIMP[11:0] Reserved. Tx TIMP is used to insert a trace mismatch error into RDI-P. This is because the Rx path doesn't automatically relay a trace mismatch to the Tx path. Tx TIMP must be set/unset within 30 seconds of a trace mismatch/match. A trace mismatch occurs when J1 mismatches for more than 2.5 seconds, and a trace mismatch error can be cleared when a match occurs for more than 10 seconds. 1 = TIMP alarm is set, per channel. Function Reset Default 0x0000 Function Reset Default 0x1802 0x41B2-- 15:13 0x41C1 12:8 0x41E6-- 15:12 0x41E9 11:0 Agere Systems Inc. 371 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 291. (PT_Tx_DS3E3_[A--B]), Transmit Provisioning Register (R/W) Address Bit Name -- DS3E3[11:0] Reserved. If TX_SEQMAP[PType] is set to 1, this bit selects to either map a DS3 or E3 signal to an STS-1. 0 = DS3. 1 = E3. Table 292. (PT_Tx_STS1_[A--D]), Transmit Provisioning Register (R/W) Address Bit Name -- STS1[11:0] Reserved. This bit must be set for an STS-1 or DS3 signal, per time slot. This will force the stuff bytes to be in columns 33 and 62, instead of columns 2--4. Function Reset Default 0x0000 Function Reset Default 0x0000 0x41EE-- 15:12 0x41EF 11:0 0x41FA-- 15:12 0x41FD 11:0 372 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 293. (PT_Tx_Cnfg_Alow), Transmit STS Configuration, Time Slots 0--5 (R/W) Address 0x4276 Bit 15:12 11:10 Name -- TS_A0 Reserved. STS Configuration for Time Slot 0. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_A1 TS_A2 TS_A3 TS_A4 TS_A5 STS Configuration for Time Slot 1. STS Configuration for Time Slot 2. STS Configuration for Time Slot 3. STS Configuration for Time Slot 4. STS Configuration for Time Slot 5. 00 00 00 00 00 Function Reset Default -- 00 Table 294. (PT_Tx_Cnfg_Ahigh), Transmit STS Configuration, Time Slots 6--11 (R/W) Address 0x4277 Bit 15:12 11:10 Name -- TS_A6 Reserved. STS Configuration for Time Slot 6. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_A7 TS_A8 TS_A9 TS_A10 TS_A11 STS Configuration for Time Slot 7. STS Configuration for Time Slot 8. STS Configuration for Time Slot 9. STS Configuration for Time Slot 10. STS Configuration for Time Slot 11. 00 00 00 00 00 Function Reset Default -- 00 Agere Systems Inc. 373 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 295. (PT_Tx_Cnfg_Blow), Transmit STS Configuration, Time Slots 0--5 (R/W) Address 0x4278 Bit 15:12 11:10 Name -- TS_B0 Reserved. STS Configuration for Time Slot 0. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_B1 TS_B2 TS_B3 TS_B4 TS_B5 STS Configuration for Time Slot 1. STS Configuration for Time Slot 2. STS Configuration for Time Slot 3. STS Configuration for Time Slot 4. STS Configuration for Time Slot 5. 00 00 00 00 00 Function Reset Default -- 00 Table 296. (PT_Tx_Cnfg_Bhigh), Transmit STS Configuration, Time Slots 6--11 (R/W) Address 0x4279 Bit 15:12 11:10 Name -- TS_B6 Reserved. STS Configuration for Time Slot 6. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_B7 TS_B8 TS_B9 TS_B10 TS_B11 STS Configuration for Time Slot 7. STS Configuration for Time Slot 8. STS Configuration for Time Slot 9. STS Configuration for Time Slot 10. STS Configuration for Time Slot 11. 00 00 00 00 00 Function Reset Default -- 00 374 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 297. (PT_Tx_Cnfg_Clow), Transmit STS Configuration, Time Slots 0--5 (R/W) Address 0x427A Bit 15:12 11:10 Name -- TS_C0 Reserved. STS Configuration for Time Slot 0. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_C1 TS_C2 TS_C3 TS_C4 TS_C5 STS Configuration for Time Slot 1. STS Configuration for Time Slot 2. STS Configuration for Time Slot 3. STS Configuration for Time Slot 4. STS Configuration for Time Slot 5. 00 00 00 00 00 Function Reset Default -- 00 Table 298. (PT_Tx_Cnfg_Chigh), Transmit STS Configuration, Time Slots 6--11 (R/W) Address 0x427B Bit 15:12 11:10 Name -- TS_C6 Reserved. STS Configuration for Time Slot 6. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_C7 TS_C8 TS_C9 TS_C10 TS_C11 STS Configuration for Time Slot 7. STS Configuration for Time Slot 8. STS Configuration for Time Slot 9. STS Configuration for Time Slot 10. STS Configuration for Time Slot 11. 00 00 00 00 00 Function Reset Default -- 00 Agere Systems Inc. 375 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 299. (PT_Tx_Cnfg_Dlow), Transmit STS Configuration, Time Slots 0--5 (R/W) Address 0x427C Bit 15:12 11:10 Name -- TS_D0 Reserved. STS Configuration for Time Slot 0. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_D1 TS_D2 TS_D3 TS_D4 TS_D5 STS Configuration for Time Slot 1. STS Configuration for Time Slot 2. STS Configuration for Time Slot 3. STS Configuration for Time Slot 4. STS Configuration for Time Slot 5. 00 00 00 00 00 Function Reset Default -- 00 Table 300. (PT_Tx_Cnfg_Dhigh), Transmit STS Configuration, Time Slots 6--11 (R/W) Address 0x427D Bit 15:12 11:10 Name -- TS_D6 Reserved. STS Configuration for Time Slot 6. 00 = Normal. 01 = CONC. 10 = UNEQ. 11 = AIS. 9:8 7:6 5:4 3:2 1:0 TS_D7 TS_D8 TS_D9 TS_D10 TS_D11 STS Configuration for Time Slot 7. STS Configuration for Time Slot 8. STS Configuration for Time Slot 9. STS Configuration for Time Slot 10. STS Configuration for Time Slot 11. 00 00 00 00 00 Function Reset Default -- 00 376 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 301. (PT_Tx_Stuffbyte_cnfg]), Tx Stuff Byte Configuration Register (R/W) Note: If STUFFBYTE_FORCE = 1 (i.e., tx_mode[15] = 1), then stuff byte locations in time slots 0--3 will be determined by this register; otherwise, stuff bytes are per SONET GR-253. Address 0x429F Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name TS_A_0 TS_A_1 TS_A_2 TS_A_3 TS_B_0 TS_B_1 TS_B_2 TS_B_3 TS_C_0 TS_C_1 TS_C_2 TS_C_3 TS_D_0 TS_D_1 TS_D_2 TS_D_3 Function 1 = Put stuff byte in time slot 0, slice A. 1 = Put stuff byte in time slot 1, slice A. 1 = Put stuff byte in time slot 2, slice A. 1 = Put stuff byte in time slot 3, slice A. 1 = Put stuff byte in time slot 0, slice B. 1 = Put stuff byte in time slot 1, slice B. 1 = Put stuff byte in time slot 2, slice B. 1 = Put stuff byte in time slot 3, slice B. 1 = Put stuff byte in time slot 0, slice C. 1 = Put stuff byte in time slot 1, slice C. 1 = Put stuff byte in time slot 2, slice C. 1 = Put stuff byte in time slot 3, slice C. 1 = Put stuff byte in time slot 0, slice D. 1 = Put stuff byte in time slot 1, slice D. 1 = Put stuff byte in time slot 2, slice D. 1 = Put stuff byte in time slot 3, slice D. Reset Default 0x0000 Agere Systems Inc. 377 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 302. (PT_TX_SEQMAP_A_AB[0--11]), Sequence Map, Bank A, Slices A and B, Per Time Slot (R/W) Address Bit Name Function Reset Default 0x0000 Bank A Is Active Whenever PT_TX_MODE[0] = 0. 0x4300-- 0x430B 15 BankA_Ptype_B Payload Type, Slice B. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 14 BankA_PM_B Payload Marker, Slice B. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice B. Indicates which channel [0--15] gets mapped to this time slot. Payload Type, Slice A. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 6 BankA_PM_A Payload Marker, Slice A. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice A. Indicates which channel [0--15] gets mapped to this time slot. 13:8 7 BankA_CHID_B BankA_Ptype_A 5:0 BankA_CHID_A 378 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 303. (PT_TX_SEQMAP_B_AB[0--11]), Sequence Map, Bank B, Slices A and B, Per Time Slot (R/W) Address Bit Name Function Reset Default 0x0000 Bank B Is Active Whenever PT_TX_MODE[0] = 1. 0x4310-- 0x431B 15 BankB_Ptype_B Payload Type, Slice B. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 14 BankB_PM_B Payload Marker, Slice B. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice B. Indicates which channel [0--15] gets mapped to this time slot. Payload Type, Slice A. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 6 BankB_PM_A Payload Marker, Slice A. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice A. Indicates which channel [0--15] gets mapped to this time slot. 13:8 7 BankB_CHID_B BankB_Ptype_A 5:0 BankB_CHID_A Agere Systems Inc. 379 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 304. (PT_TX_SEQMAP_A_CD[0--11]), Sequence Map, Bank A, Slices C and D, Per Time Slot (R/W) Address Bit Name Function Reset Default 0x0000 Bank A Is Active Whenever PT_TX_MODE[0] = 0. 0x4320-- 0x432B 15 BankA_Ptype_D Payload Type, Slice D. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 14 BankA_PM_D Payload Marker, Slice D. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice D. Indicates which channel [0--15] gets mapped to this time slot. Payload Type, Slice C. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 6 BankA_PM_C Payload Marker, Slice C. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice C. Indicates which channel [0--15] gets mapped to this time slot. 13:8 7 BankA_CHID_D BankA_Ptype_C 5:0 BankA_CHID_C 380 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 305. (PT_TX_SEQMAP_B_CD[0--11]), Sequence Map, Bank B, Slices C and D, Per Time Slot (R/W) Address Bit Name Function Reset Default 0x0000 Bank B Is Active Whenever PT_TX_MODE[0] = 0. 0x4330-- 0x433B 15 BankB_Ptype_D Payload Type, Slice D. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 14 BankB_PM_D Payload Marker, Slice D. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice D. Indicates which channel [0--15] gets mapped to this time slot. Payload Type, Slice C. 0 = STS-Nc. 1 = DS3 or E3, determined by TX_DS3E3 register. 6 BankB_PM_C Payload Marker, Slice C. Valid/invalid indicator, i.e., if set to 0, then that time slot is not expected to contain data, e.g., in the case where the payload is not completely full, e.g., when there is only one STS-12c within an STS-48. Channel ID, Slice C. Indicates which channel [0--15] gets mapped to this time slot. 13:8 7 BankB_CHID_D BankB_Ptype_C 5:0 BankB_CHID_C Agere Systems Inc. 381 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 306. (PT_Tx_J1Byte_start_0_[0--31]), Transmit J1 Byte Message Channel 0 (R/W) Address 0x4380-- 0x439F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 307. (PT_Tx_J1Byte_start_1_[0--31]), Transmit J1 Byte Message Channel 1 (R/W) Address 0x43A0-- 0x43BF Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 308. (PT_Tx_J1Byte_start_2_[0--31]), Transmit J1 Byte Message Channel 2 (R/W) Address 0x43C0-- 0x43DF Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 309. (PT_Tx_J1Byte_start_3_[0--31]), Transmit J1 Byte Message Channel 3 (R/W) Address 0x43E0-- 0x43FF Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 310. (PT_Tx_J1Byte_start_4_[0--31]), Transmit J1 Byte Message Channel 4 (R/W) Address 0x4400-- 0x441F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 382 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 311. (PT_Tx_J1Byte_start_5_[0--31]), Transmit J1 Byte Message Channel 5 (R/W) Address 0x4420-- 0x443F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 312. (PT_Tx_J1Byte_start_6_[0--31]), Transmit J1 Byte Message Channel 6 (R/W) Address 0x4440-- 0x445F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 313. (PT_Tx_J1Byte_start_7_[0--31]), Transmit J1 Byte Message Channel 7 (R/W) Address 0x4460-- 0x447F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 314. (PT_Tx_J1Byte_start_8_[0--31]), Transmit J1 Byte Message Channel 8 (R/W) Address 0x4480-- 0x449F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 315. (PT_Tx_J1Byte_start_9_[0--31]), Transmit J1 Byte Message Channel 9 (R/W) Address 0x44A0-- 0x44BF Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 316. (PT_Tx_J1Byte_start_10_[0--31]), Transmit J1 Byte Message Channel 10 (R/W) Address 0x44C0-- 0x44DF Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Agere Systems Inc. 383 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Descriptions (continued) Table 317. (PT_Tx_J1Byte_start_11_[0--31]), Transmit J1 Byte Message Channel 11 (R/W) Address 0x44E0-- 0x44FF Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 318. (PT_Tx_J1Byte_start_12_[0--31]), Transmit J1 Byte Message Channel 12 (R/W) Address 0x4500-- 0x451F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 319. (PT_Tx_J1Byte_start_13_[0--31]), Transmit J1 Byte Message Channel 13 (R/W) Address 0x4520-- 0x453F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 320. (PT_Tx_J1Byte_start_14_[0--31]), Transmit J1 Byte Message Channel 14 (R/W) Address 0x4540-- 0x455F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 Table 321. (PT_Tx_J1Byte_start_15_[0--31]), Transmit J1 Byte Message Channel 15 (R/W) Address 0x4560-- 0x457F Bit 15:8 7:0 Name J1_Byte_1 J1_Byte_0 Function J1 byte, odd bytes 1, 3, 5, . . . , 63. J1 byte, even bytes 0, 2, 4, . . . , 62. Reset Default 0x0000 384 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Map (Entire PT Except RXT Block) Table 322. PT Register Map Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 Version Register 0x4000 TX_VERSION RO Composite Interrupts 0x4001 0x4002 0x4003 0x4004 0x4005 0x4006 0x4007 TX_CH_INT -- -- TX_TS_A_INT TX_TS_B_INT TX_TS_C_INT TX_TS_D_INT RO -- -- RO RO RO RO TS11 TS11 TS11 TS11 TS10 TS10 TS10 TS10 TS9 TS9 TS9 TS9 TS8 TS8 TS8 TS8 TS7 TS7 TS7 TS7 TS6 TS6 TS6 TS6 TS5 TS5 TS5 TS5 TS4 TS4 TS4 TS4 TS3 TS3 TS3 TS3 TS2 TS2 TS2 TS2 TS1 TS1 TS1 TS1 TS0 TS0 TS0 TS0 Ch15 Ch14 Ch13 Ch12 Ch11 Ch10 Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 VERSION[7:0] 8 7 6 5 4 3 2 1 0 Composite Interrupt Masks 0x4008 0x4009 0x400A 0x400B 0x400C 0x400D 0x400E TX_CH_INTMASK -- -- TX_TS_A_INTMASK TX_TS_B_INTMASK TX_TS_C_INTMASK TX_TS_D_INTMASK R/W -- -- R/W R/W R/W R/W TS11 TS11 TS11 TS11 TS10 TS10 TS10 TS10 TS9 TS9 TS9 TS9 TS8 TS8 TS8 TS8 TS7 TS7 TS7 TS7 TS6 TS6 TS6 TS6 TS5 TS5 TS5 TS5 TS4 TS4 TS4 TS4 TS3 TS3 TS3 TS3 TS2 TS2 TS2 TS2 TS1 TS1 TS1 TS1 TS0 TS0 TS0 TS0 Ch15 Ch14 Ch13 Ch12 Ch11 Ch10 Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 Mode, Scratch, and GPO Select Registers 0x400F TX_MODE R/W STUFFBYT E_FORCE Stuffbyte_ 1or0 RX_ TRNSPOS E_ENB TX_ TRNSPOS E_ENB DS3_RO_ VALUE CORWN POF_ENB RATE_MODE LOOPBAC K_MODE SDH_ MODE BankAorB_ SEL SCRATCH 0x4010 0x4011 0x4012 0x4013 0x4014 TX_BANKAORB TX_SCRATCH -- TX_SOFTRST -- R/W R/W -- R/W -- Ch15 Ch14 Ch13 Ch12 Ch11 Ch10 Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 Agere Systems Inc. 385 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Map (Entire PT Except RXT Block) (continued) Table 322. PT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Delta/Event Registers 0x4016 -- 0x4025 0x4026 -- 0x4045 0x4046 0x4047 0x4048 0x4049 TX_CH_DELTA_0-- TX_CH_DELTA_15] -- COR/W FIFO_ EmptyD FIFO_ FullD -- TX_TS_A_Delta TX_TS_B_Delta TX_TS_C_Delta TX_TS_D_Delta COR/W COR/W COR/W COR/W RDIPD11 RDIPD11 RDIPD11 RDIPD11 RDIPD10 RDIPD10 RDIPD10 RDIPD10 RDIPD9 RDIPD9 RDIPD9 RDIPD9 RDIPD8 RDIPD8 RDIPD8 RDIPD8 RDIPD7 RDIPD7 RDIPD7 RDIPD7 RDIPD6 RDIPD6 RDIPD6 RDIPD6 RDIPD5 RDIPD5 RDIPD5 RDIPD5 RDIPD4 RDIPD4 RDIPD4 RDIPD4 RDIPD3 RDIPD3 RDIPD3 RDIPD3 RDIPD2 RDIPD2 RDIPD2 RDIPD2 RDIPD1 RDIPD1 RDIPD1 RDIPD1 RDIPD0 RDIPD0 RDIPD0 RDIPD0 Status Registers 0x404A -- 0x4059 0x405A -- 0x4079 0x407A 0x407B 0x407C 0x407D 0x407E 0x407F 0x4080 0x4081 0x4082 0x4083 0x4084 0x4085 TX_CH_STATUS_0-- TX_CH_STATUS_15] -- RO FIFO_ Empty FIFO_ Full -- TX_TS_A0_STATUS TX_TS_A1_STATUS TX_TS_A2_STATUS TX_TS_B0_STATUS TX_TS_B1_STATUS TX_TS_B2_STATUS TX_TS_C0_STATUS TX_TS_C1_STATUS TX_TS_C2_STATUS TX_TS_D0_STATUS TX_TS_D1_STATUS TX_TS_D2_STATUS RO RO RO RO RO RO RO RO RO RO RO RO RDIP3 RDIP7 RDIP11 RDIP3 RDIP7 RDIP11 RDIP3 RDIP7 RDIP11 RDIP3 RDIP7 RDIP11 RDIP2 RDIP6 RDIP10 RDIP2 RDIP6 RDIP10 RDIP2 RDIP6 RDIP10 RDIP2 RDIP6 RDIP10 RDIP1 RDIP5 RDIP9 RDIP1 RDIP5 RDIP9 RDIP1 RDIP5 RDIP9 RDIP1 RDIP5 RDIP9 RDIP0 RDIP4 RDIP8 RDIP0 RDIP4 RDIP8 RDIP0 RDIP4 RDIP8 RDIP0 RDIP4 RDIP8 386 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Map (Entire PT Except RXT Block) (continued) Table 322. PT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 Mask Registers 0x4086 -- 0x4095 0x4096 -- 0x40B5 0x40B6 0x40B7 0x40B8 0x40B9 0x40BA -- 0x4111 TX_CH_Mask_0-- TX_CH_Mask_15 -- R/W FIFO_ EmptyM FIFO_ FullM 8 7 6 5 4 3 2 1 0 -- TX_TS_A_Mask TX_TS_B_Mask TX_TS_C_Mask TX_TS_D_Mask -- R/W R/W R/W R/W -- RDIPM11 RDIPM11 RDIPM11 RDIPM11 RDIPM10 RDIPM10 RDIPM10 RDIPM10 RDIPM9 RDIPM9 RDIPM9 RDIPM9 RDIPM8 RDIPM8 RDIPM8 RDIPM8 RDIPM7 RDIPM7 RDIPM7 RDIPM7 RDIPM6 RDIPM6 RDIPM6 RDIPM6 RDIPM5 RDIPM5 RDIPM5 RDIPM5 RDIPM4 RDIPM4 RDIPM4 RDIPM4 RDIPM3 RDIPM3 RDIPM3 RDIPM3 RDIPM2 RDIPM2 RDIPM2 RDIPM2 RDIPM1 RDIPM1 RDIPM1 RDIPM1 RDIPM0 RDIPM0 RDIPM0 RDIPM0 Channel Provisioning Registers 0x4112 -- 0x4117 0x4118 -- 0x411D 0x411E -- 0x4123 0x4124 -- 0x4129 0x412A -- 0x4131 0x4132 -- 0x4141 0x4142 -- 0x4171 0x4172 -- 0x4181 0x4182 -- 0x4191 TX_Mask_A_1-- TX_Mask_A_6 TX_Mask_B_1 tiTX_Mask_B_6 TX_Mask_C_1-- TX_Mask_C_6 TX_Mask_D_1-- TX_Mask_D_6 -- R/W RDIPM_TI MA[1, 3, 5, 7, 9, 11] RDIPM_TI MB[1, 3, 5, 7, 9, 11] RDIPM_TI MC[1, 3, 5, 7, 9, 11] RDIPM_TI MD[1, 3, 5, 7, 9, 11] RDIPM_LC DA[1, 3, 5, 7, 9, 11] RDIPM_LC DB[1, 3, 5, 7, 9, 11] RDIPM_LC DC[1, 3, 5, 7, 9, 11] RDIPM_LC DD[1, 3, 5, 7, 9, 11] RDIPM_PL MA[1, 3, 5, 7, 9, 11] RDIPM_PL MB[1, 3, 5, 7, 9, 11] RDIPM_PL MC[1, 3, 5, 7, 9, 11] RDIPM_PL MD[1, 3, 5, 7, 9, 11] RDIPM_UN EQA[1, 3, 5, 7, 9, 11] RDIPM_UN EQB[1, 3, 5, 7, 9, 11] RDIPM_UN EQC[1, 3, 5, 7, 9, 11] RDIPM_UN EQD[1, 3, 5, 7, 9, 11] RDIPM_LO PA[1, 3, 5, 7, 9, 11] RDIPM_LO PB[1, 3, 5, 7, 9, 11] RDIPM_LO PC[1, 3, 5, 7, 9, 11] RDIPM_LO PD[1, 3, 5, 7, 9, 11] RDIPM_AIS A[1, 3, 5, 7, 9, 11] RDIPM_AIS B[1, 3, 5, 7, 9, 11] RDIPM_AIS C[1, 3, 5, 7, 9, 11] RDIPM_AIS D[1, 3, 5, 7, 9, 11] RDIPM_TI MA[0, 2, 4, 6, 8, 10] RDIPM_TI MB[0, 2, 4, 6, 8, 10] RDIPM_TI MC[0, 2, 4, 6, 8, 10] RDIPM_TI MD[0, 2, 4, 6, 8, 10] RDIPM_LC DA[0, 2, 4, 6, 8, 10] RDIPM_LC DB[0, 2, 4, 6, 8, 10] RDIPM_LC DC[0, 2, 4, 6, 8, 10] RDIPM_LC DD[0, 2, 4, 6, 8, 10] RDIPM_PL MA[0, 2, 4, 6, 8, 10] RDIPM_PL MB[0, 2, 4, 6, 8, 10] RDIPM_PL MC[0, 2, 4, 6, 8, 10] RDIPM_PL MD[0, 2, 4, 6, 8, 10] RDIPM_UN EQA[0, 2, 4, 6, 8, 10] RDIPM_UN EQB[0, 2, 4, 6, 8, 10] RDIPM_UN EQC[0, 2, 4, 6, 8, 10] RDIPM_UN EQD[0, 2, 4, 6, 8, 10] RDIPM_LO PA[0, 2, 4, 6, 8, 10] RDIPM_LO PB[0, 2, 4, 6, 8, 10] RDIPM_LO PC[0, 2, 4, 6, 8, 10] RDIPM_LO PD[0, 2, 4, 6, 8, 10] RDIPM_AI SA[0, 2, 4, 6, 8, 10] RDIPM_AI SB[0, 2, 4, 6, 8, 10] RDIPM_AI SC[0, 2, 4, 6, 8, 10] RDIPM_AI SD[0, 2, 4, 6, 8, 10] R/W R/W R/W -- TX_RW4_0-- TX_RW4_15 TX_RW1_0-- TX_RW1_47 TX_RW2_0-- TX_RW2_15 TX_RW3_0-- TX_RW3_15 R/W Z4_Byte Z3_Byte R/W B3_disable RDIP_Enh _Mode B3_Invert RDIP_Force RDIP_Bits REIP_Force REIP_Bits R/W SS_Bits J1_Enb C2_Byte R/W Z5_Byte H4_Byte Agere Systems Inc. 387 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Map (Entire PT Except RXT Block) (continued) Table 322. PT Register Map (continued) Note: Shading denotes reserved bits. Address 0x4192 -- 0x4195 0x4196 -- 0x4199 0x419A -- 0x419D 0x419E -- 0x41A1 0x41A2 -- 0x41A5 0x41A6 -- 0x41A9 0x41AA -- 0x41B1 0x41B2 -- 0x41C1 0x14C2 -- 0x41E5 0x41E6 -- 0x41E9 0x41EA -- 0x41ED 0x41EE -- 0x41EF 0x41F0 -- 0x41F9 0x41FA -- 0x41FD Symbol TX_alarm_A_1 TX_alarm_B_1 TX_alarm_C_1 TX_alarm_D_1 TX_alarm_A_2 TX_alarm_B_2 TX_alarm_C_2 TX_alarm_D_2 TX_alarm_A_3 TX_alarm_B_3 TX_alarm_C_3 TX_alarm_D_3 TX_alarm_A_4 TX_alarm_B_4 TX_alarm_C_4 TX_alarm_D_4 TX_alarm_A_5 TX_alarm_B_5 TX_alarm_C_5 TX_alarm_D_5 TX_alarm_A_6 TX_alarm_B_6 TX_alarm_C_6 TX_alarm_D_6 -- Type R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 sel_alarm_0 2 1 0 sel_alarm_1 R/W sel_alarm_3 sel_alarm_2 R/W sel_alarm_5 sel_alarm_4 R/W sel_alarm_7 sel_alarm_6 R/W sel_alarm_9 sel_alarm_8 R/W sel_alarm_11 sel_alarm_10 -- TX_RW5_0-- TX_RW5_15 -- R/W FIFO_Over_Value FIFO_Under_Value -- TX_TIMP_A--D R/W TIMP11 TIMP10 TIMP9 TIMP8 TIMP7 TIMP6 TIMP5 TIMP4 TIMP3 TIMP2 TIMP1 TIMP0 -- -- PT_Tx_DS3E3_[A--B] R/W DS3E3[11] DS3E3[10] DS3E3[9] DS3E3[8] DS3E3[7] DS3E3[6] DS3E3[5] DS3E3[4] DS3E3[3] DS3E3[2] DS3E3[1] DS3E3[0] -- -- TX_STS1_A--D R/W STS1_11 STS1_10 STS1_9 STS1_8 STS1_7 STS1_6 STS1_5 STS1_4 STS1_3 STS1_2 STS1_1 STS1_0 388 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Path Terminator (PT) (continued) PT Register Map (Entire PT Except RXT Block) (continued) Table 322. PT Register Map (continued) Note: Shading denotes reserved bits. Address 0x41FE -- 0x4275 Symbol -- Type -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Time-Slot Configuration Registers 0x4276 0x4277 0x4278 0x4279 0x427A 0x427B 0x427C 0x427D 0x427E -- 0x429E TX_Cnfg_Alow TX_Cnfg_Ahigh TX_Cnfg_Blow TX_Cnfg_Bhigh TX_Cnfg_Clow TX_Cnfg_Chigh TX_Cnfg_Dlow TX_Cnfg_Dhigh -- R/W R/W R/W R/W R/W R/W R/W R/W -- TS_A0 TS_A6 TS_B0 TS_B6 TS_C0 TS_C6 TS_D0 TS_D6 TS_A1 TS_A7 TS_B1 TS_B7 TS_C1 TS_C7 TS_D1 TS_D7 TS_A2 TS_A8 TS_B2 TS_B8 TS_C2 TS_C8 TS_D2 TS_D8 TS_A3 TS_A9 TS_B3 TS_B9 TS_C3 TS_C9 TS_D3 TS_D9 TS_A4 TS_A10 TS_B4 TS_B10 TS_C4 TS_C10 TS_D4 TS_D10 TS_A5 TS_A11 TS_B5 TS_B11 TS_C5 TS_C11 TS_D5 TS_D11 Stuffbyte Configuration Register 0x429F TX_Stuffbyte_Cnfg R/W TS_A_0 TS_A_1 TS_A_2 TS_A_3 TS_B_0 TS_B_1 TS_B_2 TS_B_3 TS_C_0 TS_C_1 TS_C_2 TS_C_3 TS_D_0 TS_D_1 TS_D_2 TS_D_3 Transmit Sequence Map Registers (Bank A) 0x4300 -- 0x430B 0x4310 -- 0x431B PT_TX_SEQMAP_A_AB _[0--11] PT_TX_SEQMAP_B_AB _[0--11] R/W PType_B PM_B CHID_B PType_A PM_A CHID_A R/W PType_B PM_B CHID_B PType_A PM_A CHID_A Transmit Sequence Map Registers (Bank B) 0x4320 -- 0x432B 0x4330 -- 0x433B 0x433C -- 0x437F PT_TX_SEQMAP_A_CD _[0--11] PT_TX_SEQMAP_B_CD _[0--11] -- R/W PType_D PM_D CHID_D PType_C PM_C CHID_C R/W PType_D PM_D CHID_D PType_C PM_C CHID_C -- Agere Systems Inc. 389 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Path Terminator (PT) (continued) PT Register Map (Entire PT Except RXT Block) (continued) Table 322. PT Register Map (continued) Note: Shading denotes reserved bits. Address 0x4380 -- 0x439F 0x43A0 -- 0x43BF 0x43C0 -- 0x43DF 0x43E0 -- 0x43FF 0x4400 -- 0x441F 0x4420 -- 0x443F 0x4440 -- 0x445F 0x4460 -- 0x447F 0x4480 -- 0x449F 0x44A0 -- 0x44BF 0x44C0 -- 0x44DF 0x44E0 -- 0x44FF 0x4500 -- 0x451F 0x4520 -- 0x453F 0x4540 -- 0x455F 0x4560 -- 0x457F 0x4580 -- 0x4587 Symbol Tx_J1Byte_0_[0--31] Type R/W 15 14 13 12 J1_Byte_1 11 10 9 8 7 6 5 4 J1_Byte_0 3 2 1 0 J1 Message Registers Tx_J1Byte_1_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_2_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_3_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_4_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_5_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_6_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_7_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_8_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_9_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_10_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_11_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_12_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_13_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_14_[0--31] R/W J1_Byte_1 J1_Byte_0 Tx_J1Byte_15_[0--31] R/W J1_Byte_1 J1_Byte_0 -- -- 390 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block Introduction This section describes the functions of the receive terminator block in the MARS2G5 P-Pro device. It is designed to handle one STS-48 stream (single-channel mode) or four STS-12 or STS-3 streams (quad-channel mode) and pass the data to the data engine block of the MARS2G5 P-Pro. The RXT contains all the functionality of a pointer interpreter including path alarms, signal-fail detection, performance monitoring, and path trace. In OC-3 mode, the RXT still operates at an STS-12 rate and data bytes are replicated four times to achieve this as shown in Figure 46. STS-3 #1 STS-1 #2 STS-1 #3 STS-1 #1 STS-1 STS-12 1111222233331111 #1 STS-1s #2 STS-1s #3 STS-1s 5-8151(F)r.2 Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator The RXT block requires a frame pulse for each input stream. In the MARS2G5 P-Pro device, these four signals are provided from the pointer processor block. The RXT block performs performance monitoring of the input stream(s), and can interrupt the host microprocessor with alarms and make available the collected results through a register set. The RXT is SONET and SDH compliant. The pointer interpreter extracts the SONET synchronous payload envelope (SPE) from the incoming data by interpreting the H1 and H2 pointer bytes of the line overhead. The SPE is then provided as an output of the RXT block as a 32-bit bus. Since the RXT terminates the path, performance monitoring is performed and the RDI and ERDI codes are passed to the SPE block (which accompanies the RXT block in MARS2G5 P-Pro) for insertion in the outgoing stream. A detailed block diagram of the RXT is shown in Figure 47 on page 392. A brief description of each block follows the diagram. For more detail on each block, refer to the appropriate section detailing the block. Agere Systems Inc. 391 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Introduction (continued) PATH MONITOR ALL 1s DATA IN POINTER INTERPRETER DATA OUT AIS INSERT J1 MARKER SYNC PULSE RECEIVE TIMING MICROPROCESSOR INTERFACE PERFORMANCE MONITORING 5-8708(F)r.1 Figure 47. STS Receive Terminator (RXT) Functional Block Diagram The pointer interpreter interprets the H1 and H2 bytes and determined the offset of each STS-1, as well as the state of the STS-1 (AIS, LOP, concatenated, normal). The receive timing block extracts the H1, H2, and H3 bytes from the incoming data for the pointer interpreter, and uses the offset determined by the interpreter to create signals that are used to extract the SPE and the path overhead from the incoming data. The path monitor implements the performance monitoring on the path overhead. The AIS insert block allows AIS insertion under microprocessor control. The microprocessor interface provides microprocessor registers to control the operation of the RXT and to read the performance monitor data and RXT status. 392 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Receive Timing Functions The timing block generates the signals required by the pointer interpreter, elastic store, and performancemonitoring blocks. This block uses the frame pulse to create H1, H2, and STS indicators for the pointer interpreter. The pointer interpreter provides increment, decrement, valid, and current pointer information for each STS which allows the timing block to produce multiplexed POH indicators (i.e., J1, B3, etc.) and the associated valid SPE signal for all STSs (SPE_VLD). The timing block has no indications of concatenation and thus produces POH indicators for all STSs regardless of their concatenation state. The path overhead bytes are extracted by subtracting the offset value for an STS-1 from an SPE byte counter (that counts from 0 to 782) to produce an 11-bit signed number that indicates how far from J1 the current byte is. This value is compared to predetermined values to find the individual overhead bytes. The compare values for each overhead byte are shown in Table 323 below. Table 323. Path Overhead Extraction Compare Values Overhead Byte J1 B3 C2 G1 F2 H4 Z3 Z4 Z5 Compare Value (SPE byte offset) 0 +87 or -696 +174 or -609 +261 or -522 +348 or -435 +435 or -348 +522 or -261 +609 or -174 +696 or -87 The receive timing block also generates a POH byte signal, indicating that the current byte is part of the path overhead. Because the drop interface may need indications of SPE and path overhead even when an STS-1 is in AIS (to keep a FIFO from overrunning, for example), generic indications of SPE and POH are created. The generic SPE indication is asserted for bytes in columns 4 through 90 inclusive and the generic POH indication is asserted for bytes in column 4. The AIS insert block determines whether the actual or generic indications will be used for a particular STS-1. If the pointer generator is not being bypassed, the equivalent signals will be created in the pointer generator. Agere Systems Inc. 393 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Pointer Interpreter Functions The STS pointer interpreter interprets the H1 and H2 bytes for each incoming STS-1. The interpreter has four states: loss of pointer (LOP), alarm indication signal (AIS), normal (NORM), and concatenation indication (CONC). The state diagram is shown in Figure 48 on page 394. 3xAIS CONC 3xCONC AIS 3x CO NC 3x AI S 3xNORM 3xCONC 8x I RM OF x N ND 3x 1 nv al id 8xINVALID 8xNDF NORM 3xNORM 5-8709(F) LOP Figure 48. Interpreter State Machine 394 8xInvalid 3xAIS Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Pointer Interpreter Functions (continued) Incoming pointers are categorized into one or more of the following categories: 1. 2. 3. 4. 5. 6. 7. 8. 9. Normal pointer (NDF is not set and the offset is in range). Normal pointer (offset = validated offset). Normal pointer (offset = old offset--i.e., the same offset as in the last frame). Valid NDF pointer (NDF set and offset is in range). Concatenation indicator (NDF set with an all ones offset). AIS pointer (all ones). Increment indicator (compared to validated offset). Decrement indicator (compared to validated offset). Other (unrecognized pointer). Note: A given pointer can be classified as belonging to more than one of the above groups. There are only a few valid combinations: 1 and 2 1 and 3 1, 2, and 3 1 and 7 1 and 8 1, 3, and 7 (if the same pointer that created (1 and 7) repeats the next frame) 1, 3, and 8 (if the same pointer that created (1 and 8) repeats the next frame) Increments and decrements can be evaluated in either SONET or SDH modes. In SONET mode, the 8 of 10 rule is used, where 8 of the 10 I and D bits must be evaluated to be an increment or decrement for the pointer to be considered an increment or decrement. In SDH mode, the 3 of 5 rule is used, where 3 of the 5 I bits and 3 of the 5 D bits must be evaluated to be an increment or decrement for the pointer to be considered and increment or decrement. Note: In SDH mode, it is possible for a stuck input pointer to cause a repeating increment then decrement pattern. To avoid this situation, increment and decrement pointers that are not perfect (10 of 10) are considered invalid. See the description of the invalid counter for more details. Agere Systems Inc. 395 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Pointer Interpreter Functions (continued) Five counters are used in conjunction with the pointer categories to determine the state of the state machine. These counters are the following: norm_cnt--counts how many consecutive times condition 3 occurs (condition (1 and !3) will preset this counter to 1). ndf_cnt--counts how many consecutive times condition 4 occurs. ais_cnt--counts how many consecutive times condition 6 occurs. invalid_cnt--counts how many consecutive times conditions. (next state is NORM and !2 and !4 and !6 and !7* and !8* and !((norm_cnt ==2) and 3)) or (next state is AIS and !6) or (next state is CONC and !5 and !6) occurs. concat_cnt--counts how many consecutive times condition 5 occurs. * See details below. The norm_cnt counter will be preset to 1 when condition 1 occurs and condition 3 doesn't occur. In other words, if a normal pointer is received that is not the same offset as the last pointer received, the norm_cnt is set to 1. Note: Invalid_cnt counts increments and decrements as being invalid while in the NORM state if there is less than a 10 of 10 match in the I and D bits. For example, a pointer with all of the I bits inverted and 4 of the D bits not inverted would be counted as an invalid pointer, and an increment would be performed. NDF pointers are considered valid while in the NORM state. NDF pointers are counted separately with ndf_cnt. In AIS state, any pointer that is not an AIS pointer is considered invalid. In CONC state, any pointer that is not a concatenation indication or an AIS pointer is considered invalid. The count condition is evaluated at the same time as the state is evaluated. Therefore, the counter is not actually incremented or cleared until after the state has been evaluated. Thus, the pointer condition must also be used to evaluate the state. If any of the conditions for a counter do not occur, the counter is cleared. The state machine will change states based on the following conditions. Note: If the conditions indicate that there are two possible states to change to, the one listed first will be taken. 396 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Pointer Interpreter Functions (continued) The state changes from LOP to: AIS--when (ais_cnt == 2) and condition 6 occurs. NORM--when (norm_cnt == 2) and condition 3 occurs. CONC--when (concat_cnt == 2) and condition 5 occurs. The state changes from AIS to: NORM--when (norm_cnt == 2) and condition 3 occurs or condition 4 occurs. CONC--when (concat_cnt == 2) and condition 5 occurs. LOP--when (invalid_cnt == 7) and condition 6 does not occur. The state changes from NORM to: AIS--when (ais_cnt == 2) and condition 6 occurs. CONC--when (concat_cnt == 2) and condition 5 occurs. LOP--when (invalid_cnt == 7) and condition 2 does not occur or (ndf_cnt == 7) and condition 4 occurs. The state changes from CONC to: AIS--when (ais_cnt == 2) and condition 6 occurs. NORM--when (norm_cnt == 2) and condition 3 occurs. LOP--when (invalid_cnt == 7) and condition 5 does not occur. Note: When changing states, NORM, CONC, and AIS always take precedence over LOP (NORM, CONC, and AIS being mutually exclusive). The pointer interpreter provides outputs to indicate the following: AIS-P and LOP-P defect indications on a per-STS-1 basis (RAW_AIS_P, RAW_LOP_P). A per-STS-1 indication of CONC state (RECD_CONC_MAP). A per-STS-1 indication of pointer state (STS_OK)--indicates that an STS-1 is in NORM state, or if it is in CONC state and the first STS-1 in the concatenated STS-Nc is in NORM state. A per-STS-1 indication of receipt of an all 1s pointer--this is used by the pointer generator to generate and allones pointer in order to meet the all-ones pointer relay objective in GR-253. Agere Systems Inc. 397 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation In the diagrams, the squares represent bytes coming into the RXT. Each diagram represents a different RXT configuration. The numbers in the squares represent the order in which the bytes are received. The numbers to the left of each square represent the SONET ordering. Each byte belongs to a separate STS-1 signal. The shaded squares represent the possible starting points for concatenated STS signals (these are the N,1 STS-1 numbers shown in GR-253 in Chapter 5). 1 1 4 2 7 3 10 4 STS-12 POINTER 2 5 5 6 8 7 11 8 3 9 6 10 9 11 12 12 5-8710(F) Figure 49. STS-12 RXT Concatenated Offset Passing 1 1 4 2 STS-6 POINTER 2 3 5 4 3 5 6 6 5-8711(F) Figure 50. STS-6 RXT Concatenated Offset Passing 398 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) 1 1 STS-3 POINTER 1 1 STS-1 POINTER 2 2 3 3 5-8712(F) Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing The arrows indicate how offsets are propagated between concatenated STS-1s. Offsets are propagated during the H2 time. If an STS-1 is in concatenation state, it will use the offset from the STS-1 indicated by the arrow. For example, if an STS-6c were constructed in an STS-12 RXT starting with STS-1 number 4 (SONET ordering) in the STS-12 diagram, then STS-1 number 4 will be in NORM state, and STS-1 numbers 5, 6, 7, 8, and 9 would be in CONC state. STS-1 numbers 5 and 7 would get their offset from STS-1 number 4. STS-1 number 8 would get its offset from STS-1 number 7. STS-1 number 6 would get its offset from STS-1 number 5 and STS-1 number 9 would get its offset from STS-1 number 8. This example is shown in Figure 52 below. Note that in this situation, offsets are always passed to STS-1s that arrive later in time. This method will work for constructing any size and number of concatenated streams within an STS-12. 1 1 4 2 7 3 10 4 STS-12 POINTER 2 5 5 6 8 7 11 8 3 9 6 10 9 11 12 12 5-8713(F)r.1 Figure 52. STS-6c Offset Passing in an STS-12 RXT Agere Systems Inc. 399 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) The propagated offset for an STS-1 in the CONC state is stored in the same register as the validated offset is stored if the STS-1 is in the NORM state. In addition to the offset itself, increment, decrement, and valid offset indications are propagated to concatenated STS-1s. If any STS-1s are concatenated with STS-1s from a different STS-12 processing block, the offset must be passed between blocks. Also, if any STS-1s from other blocks are concatenated to STS-1s in this block, an offset must be passed to the next block. More specifically, if STS-1 number 1 is concatenated, it will receive its offset from STS-1 number 10 (SONET ordering) from the previous block. Note that the offset for STS-1 number 10 is not valid until after the fourth clock of the H2 byte, which occurs after the state machine for STS-1 number 1 of the next STS-12 block has been processed. Thus, the offset for STS-1 number 1 and any subsequent concatenated STS-1s cannot be processed until after the fourth byte. This means that the offsets of concatenated STS-1s must be updated after that STS-1s state machine has been processed. This is accomplished by enabling the register that stores the propagated offset just before the H3 byte of that STS-1. This means the offset must be able to reach all STS-1s in the concatenation in at least two thirds of a byte time (approximately 100 ns). RXTs configured as STS-1 or STS-3 will have a whole byte time (approximately 150 ns). A further problem occurs when several STS-12 blocks contain one large STS-Nc signal. Each block after the first would have to wait until the previous block has a valid offset for STS-1 number 10, then propagate the offset through to the next STS-12 block, which would take another four clocks (to propagate from STS-1 number 1 to STS-1 number 10 and out). For an STS-192c, it would take 66 clocks to propagate the offset to the last STS-1, using an STS-12 RXT. This is considerably more than the 12 clocks during which the H2 byte is being received for all STS-1s. To alleviate this problem, a MUX is added such that if all possible STS-1s are concatenated in a block (numbers 1, 4, 7, and 10 for an STS-12 block or 1 and 4 for an STS-6 block), the output offset comes directly from the concatenation input offset rather than from STS-1 number 10. This way, once the fourth STS-1 state machine is processed in each STS-12 block (STS-1 number 10), the offset is made available to all subsequent STS-12 blocks. This does, however, result in significant combinational logic between flip-flops; the offset may go through up to 14 2:1 MUXes. Thus, in the actual implementation, a 4:1 MUX is used, which can take the output offset from any one of the previous three RXTs. This results in a maximum of five 4:1 MUXes the offset may go through for an STS192c, using STS-12 RXTs. The passing of the offsets for concatenation is illustrated in Figure 53. The MUXes are selected to pass the offset from as close to the head of the concatenation as possible. RXT N RXT N + 1 RXT N + 2 RXT N + 3 5-8714(F)r.2 Figure 53. Concatenated Offset Passing 400 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) To ensure that concatenated payloads go through the elastic store in the correct order, the address counter of a concatenated STS-1 is synchronized to the address counter of the STS-1 at the head of the concatenation. Within an RXT, the address of the head of the concatenation is simply passed to the concatenated STS-1s. When the STS-1 at the head of the concatenation is in a different RXT, a synchronization signal is passed from the last STS1 of the previous RXT (actually, the last STS-1 on an STS-3 boundary) that indicates that the first STS-1 in the RXT should go to address 0 on the next byte. In this way, all of the STS-1s in the concatenation will have the same elastic store address at the same time. The synchronization signal is passed through a 4:1 MUX structure in the same way that concatenation offsets are passed in the pointer interpreter. Path Trace (J1) The path trace byte carries a repeating message that is defined in SONET as 64 bytes (ASCII, Agere Systems Inc. 401 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Signal Fail Alarms. Each of the 48 STS-1s entering the RXT can be automatically monitored for B3 errors against a programmable threshold. Concatenated payloads are supported by programming the threshold values for the head STS-1. Each STS-1 or head of an STS-NC has a select to choose which threshold group's parameters to compare against. There are eight threshold groups available, each group consisting of: Set Threshold. If the B3 errors is equal or greater than this value in the given time window, the signal fail alarm for this STS-1 is set. The B3 count in subsequent window times must be less than the clear threshold listed below to clear this error condition. Set Threshold Window Select. There are four time windows available between the eight groups. The set threshold window select can be set to one of these window sizes. Clear Threshold. If the signal fail alarm has been previously set, it will be cleared if an entire clear window time goes past with the B3 error count less than this value. Clear Threshold Window Select. If the signal fail alarm has been previously set, this window size will be used to measure B3 errors. Each STS-1 has a 9-bit B3 counter, which is incremented every time a B3 error appears. If STSs are part of an STS-Nc, there is one 14-bit counter for the entire concatenation. This counter is cleared at the end of the window selected for the threshold group for which this STS-1 or STS-Nc is set to. This counter (9 or 14 bits) can be incremented by 0 (if no B3 errors occurred) or up to eight counts (if all the bits in the B3's BIP-8 calculation are opposite from expected). Note there are no bit/block issues with the signal fail counters; only bit errors are counted. Bit/block is only an option for the B3 counters in the path monitoring (PM). The signal fail alarm is set if the number of B3 errors for an STS-1 or STS-Nc is above the set threshold within this window time. The B3 error counter for each STS-1 or STS-Nc is cleared at the end of each window and counts up again in the next window. One can set an individual STS-1/STS-Nc to set an alarm on one BER and clear this alarm on another. For this, a threshold count value and timing window is provided for both set and clear. For each STS-1 or STS-Nc, its B3 counter is running for either the time set by the set threshold window or the time set by the clear threshold window. If this STS-1/STS-Nc is in the clear state (the alarm bit is clear), then the signal fail circuitry will be looking for the case when the number of B3 errors equals or exceeds the set threshold. The counter will be running for the duration of the set threshold window. If this condition is reached, the alarm will be set immediately and the system will switch to watching the desired clear window. It will wait until the clear window has completed its current cycle and will start counting B3 errors again in the next cycle. The B3 counter will be cleared and B3 errors will be added, and at the end of this window time (now the clear window time), the decision will be made to clear the alarm condition or not. If the number of B3 errors in the counter is less than the clear threshold, the alarm will be cleared and during the next window of length = set threshold window size the counter will be compared to the set threshold. Otherwise, this error condition will remain set and another window of duration = clear threshold window size will commence. The signal fail alarm can be set anywhere during the window, but can only be cleared at the end of a window time. The RXT is either checking for the set or clear condition for an STS-1/STS-Nc at a given time. One implication of this is that if the clear threshold was set for a BER higher than the set threshold and an incoming signal of a constant BER between the two was present, the signal fail alarm would oscillate, set, and clear with a period of zero to one times the set window threshold window time plus one to two times the period of the clear window threshold window time. 402 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) There are eight threshold groups available (see Table 413--Table 416); two are labelled as being used for STS-1s (group 0 and 1) and six (groups 2--7) are labelled for use as STS-Ncs. Group 0 and 1 have set and clear thresholds of 9 bits (0--511) whereas groups 2--7 have set and clear thresholds of up to 14 bits (0--16383). This is to accommodate the higher data rate of a concatenated payload and thus the higher number of bit errors one would see in the same time window for the same BER. However, one could point an STS-1 to group 2--7 as long as the thresholds are set to 511 or less to stay within the 9-bit size of an individual STS-1s counter. There are four threshold window size registers, each 16 bits, in increments of 0.5 ms (for a maximum of window size of 32 seconds). The table below shows the recommended set/clear threshold and window values for the BER they are intended for. Table 324. Set/Clear Threshold and Window Settings Intended for STS-1 or STS-Nc STS-1 Threshold Type Set Clear STS-1 Set Clear STS-1 Set Clear STS-3c Set Clear STS-3c Set Clear STS-3c Set Clear STS-6c Set Clear STS-6c Set Clear STS-6c Set Clear Desired BER to Detect BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 Threshold Threshold Window Select 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0x6C 0x22 0xC9 0x27 0xCF 0x24 0x8A 0x49 0x226 0x59 0x2B0 0x60 0x89 0x76 0x39B 0xA8 0x53A 0xAC Agere Systems Inc. 403 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Table 324. Set/Clear Threshold and Window Settings (continued) Intended for STS-1 or STS-Nc STS-9c Threshold Type Set Clear STS-9c Set Clear STS-9c Set Clear STS-12c Set Clear STS-12c Set Clear STS-12c Set Clear STS-15c Set Clear STS-15c Set Clear STS-15c Set Clear STS-18c Set Clear STS-18c Set Clear STS-18c Set Clear Desired BER to Detect BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 Threshold Threshold Window Select 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0x8D 0x89 0x47E 0xED 0x7CA 0x103 0x8D 0x9D 0x50B 0x139 0xA3F 0x14C 0x8E 0xA4 0x573 0x178 0xC92 0x199 0x89 0xA9 0x5A4 0x1B5 0xEE2 0x1E5 404 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Table 324. Set/Clear Threshold and Window Settings (continued) Intended for STS-1 or STS-Nc STS-21c Threshold Type Set Clear STS-21c Set Clear STS-21c Set Clear STS-24c Set Clear STS-24c Set Clear STS-24c Set Clear STS-27c Set Clear STS-27c Set Clear STS-27c Set Clear STS-30c Set Clear STS-30c Set Clear STS-30c Set Clear Desired BER to Detect BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 Threshold Threshold Window Select 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0x8E 0xB2 0x5C8 0x1E8 0x10F8 0x23F 0x8D 0xB0 0x5D1 0x224 0x1317 0x280 0x8C 0xAF 0x5F2 0x253 0x151B 0x2C0 0x8C 0xB0 0x5E9 0x27E 0x16D6 0x316 Agere Systems Inc. 405 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Table 324. Set/Clear Threshold and Window Settings (continued) Intended for STS-1 or STS-Nc STS-33c Threshold Type Set Clear STS-33c Set Clear STS-33c Set Clear STS-36c Set Clear STS-36c Set Clear STS-36c Set Clear STS-39c Set Clear STS-39c Set Clear STS-39c Set Clear STS-42c Set Clear STS-42c Set Clear STS-42c Set Clear Desired BER to Detect BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 Threshold Threshold Window Select 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0x8C 0xB2 0x5FC 0x2CC 0x189C 0x366 0x90 0xB0 0x603 0x2DB 0x1A65 0x3AF 0x8B 0xB4 0x601 0x312 0x1BC9 0x3EF 0x93 0xB6 0x601 0x336 0x1D5F 0x436 406 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Table 324. Set/Clear Threshold and Window Settings (continued) Intended for STS-1 or STS-Nc STS-45c Threshold Type Set Clear STS-45c Set Clear STS-45c Set Clear STS-48c Set Clear STS-48c Set Clear STS-48c Set Clear Desired BER to Detect BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 BER = 10-3 BER = 10-4 BER = 10-4 BER = 10-5 BER = 10-5 BER = 10-6 Threshold Threshold Window Select 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0xA 0xA 0x64 0x64 0x3E8 0x3E8 0x8A 0xB3 0x607 0x363 0x1EEF 0x488 0x8E 0xB3 0x5FF 0x38D 0x3E8 0x4C8 Agere Systems Inc. 407 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Below are the default threshold window sizes. Table 325. Default Signal Fail Window Size Settings Window Size Register Window Size 0 Window Size 1 Window Size 2 Window Size 3 Time 5 ms 50 ms 500 ms 5s Register Setting 0x000A 0x0064 0x03e8 0x2710 Note 1: If the window size is set to 0x0000, it will provide a 0.5 ms window, the same as if it was set to 0x0001. Note 2: If a window size register is changed, each current window will be cut short and will finish from one to two time units (0.5 ms to 1 ms if the block is running in 90 columns) before the new window size is loaded. For example, if the column size is 90, and window size 3 was changed, it will not take from 0 to up to 5 seconds to start running with the new window size, but rather 0.5 ms to 1 ms. Note 3: The unit of time in the window size register is 0.5 ms if the block is running in 90 column mode. This unit of time is equal to four STS-frame sizes (4 x 125 s = 0.5 ms). If the user is operating with a number of columns other than 90, such as the so-called short frame mode (where the number of columns in a frame is less than 90 columns for reduced simulation and testing time), then the unit of time for the window size registers is no longer 0.5 ms, but rather four times the frame size. B3 Calculation. The B3 is calculated on the TDM data stream coming from the pointer interpreter. It is calculated using a continuously cycling 8-bit wide shift register that is N bytes deep (where N is the number of STS-1s being handled by the RXT). Incoming data is XORed with the value coming out the end of the shift register, if the SPE_VLD signal from the receive timing module is asserted, and loaded into the input of the shift register. If SPE_VLD is not asserted, the value coming out of the end of the shift register is not modified before loading it into the input of the shift register. If the J1 indication is present from the receive timing module, the data value (J1 byte) is loaded directly into the input of the shift register to begin the calculation for the next frame, and the value coming out of the shift register is loaded into a holding register. This is the calculated BIP-8 for the last SPE frame. In the case of concatenation, each STS-1 in the STS-Nc stream calculates a BIP-8 for its part of the concatenated SPE. After the J1 byte, the last STS-1 in the concatenation will pass its BIP calculation to the previous STS-1 in the concatenation, which will XOR the incoming BIP with its own and pass the result on to the next previous STS-1, and so on. When the first STS-1 in the concatenation is reached, the BIP is not passed on. The concatenation is determined by the pointer interpreter received concatenation map. Thus, if an STS-1 erroneously enters the CONC state, the B3 calculation will cause errors on the previous STS-1, which is assumed to be the first STS-1 in the concatenation. When the B3 byte arrives in the next SPE, it is compared to the calculated B3 and the result is loaded back into the holding register. The contents of the holding register are then shifted out serially to be used as the enable for the binning counter. 408 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Path Signal Label (C2) The path signal label byte is used to indicate either the type of payload carried in the STS SPE or the status of the payload. Of the 256 possible values, only the codes 0x01 to 0x04 and 0x12 to 0x15 are currently defined to identify payload types, while the codes 0xE1 to 0xFC are defined to indicate payload defects (see STS Path Signal Label Assignments, Table 326, on page 410). The code 0xFF is a special reserved code due to its appearance in an STS AIS and is treated as a don't care during any defect detection or clearing. The C2 byte is extracted each frame and stored in the receive signal label registers. If the locally provisioned value, configured in the expected signal label registers, is any equipped value (i.e., not 0x00), the extracted signal label is also processed for the following defects: Payload Label Mismatch (PLM). Detected if the extracted signal label is a valid payload specific code and does not match the locally provisioned value in the expected signal label registers for five consecutive frames. Cleared if the extracted signal label matches the locally provisioned value, the equipped nonspecific code (0x01), or a valid PDI code for five consecutive frames. If the locally provisioned value is the equipped nonspecific code, then it matches any valid equipped code. The valid payload specific codes are by default 0x02 to 0xE0, 0xFD and 0xFE, with the codes 0xE1 to 0xFB also included if the locally provisioned payload is VT-structured (0x02 or 0x03). If payload defect indication detection is disabled, 0xE1 to 0xFC are always included. Detection of a PLM defect is indicated by a latched alarm status bit in the memory map, and could result in AIS insertion if provisioned through software. Path Unequipped (UNEQ). Detected if the extracted signal label matches the unequipped code (0x00) for five consecutive frames. Cleared if the extracted signal label does not match the unequipped code for five consecutive frames. Detection of an UNEQ defect is indicated by a latched alarm status bit and a one second PM in the memory map, and could result in AIS insertion if provisioned through software. Payload Defect Indication (PDI). Detected if the extracted signal label matches a valid PDI code for five consecutive frames. Cleared if the extracted signal label does not match a valid PDI code for five consecutive frames. Valid PDI codes are 0xE1 to 0xFC when the locally provisioned payload label is 0x01, 0x02, or 0x03 (VT-structured STS) or just 0xFC otherwise. PDI detection can be disabled per STS through the microprocessor interface. Update. The C2 value is dumped into an MPU register. Each time the captured value changes, a delta bit is set. Agere Systems Inc. 409 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Table 326. STS Path Signal Label Assignments Code (Hex) 0x00 0x01 0x02 0x03 0x04 0xE1 Content of the STS SPE Unequipped Equipped--nonspecific payload VT-structured STS-1 SPE Locked VT mode Asynchronous mapping DS3 VT-structured STS-1 SPE with 1 VTx payload defect (STS-1 w/1 VTx PD) Code (Hex) 0x12 0x13 0x14 0x15 0x16 0xEF 0xF0 0xF1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE STS-1 w/2 VTx PDs STS-1 w/3 VTx PDs STS-1 w/4 VTx PDs STS-1 w/5 VTx PDs STS-1 w/6 VTx PDs STS-1 w/7 VTx PDs STS-1 w/8 VTx PDs STS-1 w/9 VTx PDs STS-1 w/10 VTx PDs STS-1 w/11 VTx PDs STS-1 w/12 VTx PDs STS-1 w/13 VTx PDs STS-1 w/14 VTx PDs 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC Content of the STS SPE Asynchronous mapping for DS4NA Mapping for ATM Mapping for DQDB Asynchronous mapping for FDDI Mapping for HDLC-PPP (proposed) STS-1 w/15 VTx PDs STS-1 w/16 VTx PDs STS-1 w/17 VTx PDs STS-1 w/18 VTx PDs STS-1 w/19 VTx PDs STS-1 w/20 VTx PDs STS-1 w/21 VTx PDs STS-1 w/22 VTx PDs STS-1 w/23 VTx PDs STS-1 w/24 VTx PDs STS-1 w/25 VTx PDs STS-1 w/26 VTx PDs STS-1 w/27 VTx PDs VT-structured STS-1 SPE with 28 VT1.5 payload defects, or a nonVT-structured STS-1 or STS-Nc SPE with a payload defect 410 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Below is a table detailing the conditions and alarms created by different states of the provisioned (expected) and received (incoming) path label found in the C2 byte. Table 327. Payload Label Conditions Expected C2 Value Set in Microprocessor Register -- 0x00 Received C2 Value (incoming) 0x00 0x01 0x02 or 0x03 0x04--0xE0 0xFD--0xFE 0xE1--0xFB 0xFC 0xFF Unequipped 0x01 Nonspecific equipped UNEQ-P Match Match Match PDI-P PDI-P Hold 0x02 or 0x03 VT structured payload UNEQ-P Match Match or PLM-P PLM-P PDI-P PDI-P Hold Incoming C2 Byte 0x04--0xE0 0xE1--0xFB 0xFD--0xFE Non-VT structured payload UNEQ-P Match PLM-P Match or PLM-P PLM-P PDI-P Hold 1--27 VT path defects 0xFC 28-VT path defects 0xFF AIS None None None None None None None Nonsensical provisioning Note: The expected C2 byte is only used as a programming mode, i.e., changing the value does not reset the validation counters (unequipped and payload mismatch). Agere Systems Inc. 411 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Path Status (G1) The path status byte is used to convey the path termination status and performance back to the originating STS PTE. This allows the performance of the full-duplex path to be monitored from any single point along the path. Bits 1 to 4 are used as a remote error indication (formerly far end block error or FEBE), while bits 5 to 7 are used as a remote defect indication. The G1 byte is extracted each frame and processed for these functions as described below. Remote Error Indication (REI-P). Indicates the count of bit errors detected at the far-end STS PTE using the path BIP-8. The error count is a binary number from 0 to 8 (values above 8 are invalid and interpreted as 0) and is accumulated in an internal 16-bit counter based on either bit or block errors as provisioned per channel through the microprocessor interface. If bit error mode is enabled for the channel, the counter is incremented by the actual error count. If block error mode is enabled for the channel, the counter is only incremented by one, when the error count is not 0, regardless the actual value. The value in the counter accumulates until it is transferred to the REI-P registers on the positive edge of the performance-monitoring strobe (PMSTB input) at which point the counter is cleared. Remote Defect Indication (RDI-P). Indicates the detection of a defect at the far-end STS PTE. Initially, RDI-P was defined as a one-bit value in bit 5, but has since been expanded to a 3-bit enhanced value (ERDI-P). Table 328 shows the valid codes and interpretation for both the 1-bit and enhanced RDI schemes. As can be seen, bits 6 and 7 are always set to opposite values for ERDI while they are set to the same value for 1-bit RDI. The POH uses this fact to determine which RDI scheme is being used on a per STS basis. An RDI-P defect is then detected if a valid defect code for one of the RDI schemes is received for ten consecutive frames. The RDIP defect is cleared when the no defects code for that scheme is received for ten consecutive frames. The value of the last validated 3-bit RDI code is stored in the ERDI-P registers in the memory map. In addition, detection of a 1-bit RDI defect or each of the three ERDI defects is indicated by a one second PM bit in the memory map. Table 328. RDI-P Codes and Interpretation G1[5:7] 0xx* 1xx* 001 010 101 110 Priority of Enhanced RDI-P Codes Not applicable Not applicable 4 3 1 2 Trigger No defects AIS-P, LOP-P No defects PLM-P, LCD-P AIS-P, LOP-P UNEQ-P, TIM-P Interpretation No RDI-P defect 1-bit RDI-P defect No ERDI-P defects ERDI-P payload defect ERDI-P server defect ERDI-P connectivity defect * These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 2 and 1 must be set to the same value, and should be set to 00. These codes are transmitted by STS PTE that support enhanced RDI-P. 412 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) Concatenation (continued) Interrupt Alarms and Masks The following path conditions create alarms and set bits in the alarm registers. There is a bit for each STS-1. Path LOP. Path AIS. Path UNEQ--unequipped alarm. Path PLM--path label mismatch. Path RDI--remote defect indicator. SF--path signal fail. Elastic store overrun, underrun. The following conditions also create alarms: Concatenation mismatch--the received concatenation map does not match the expected map. Unsupported concatenation. J1 validated--a new path trace message has come in and is validated. This occurs when the stream is set to receive mode. J1 mismatch--the path trace message that has come in does not match the provisioned one. This alarm occurs when the stream is set to provision mode. There is a control bit that sets whether the alarm registers are cleared by writing a one to that bit or by just reading the register. This control bit is in the clear on read/write register. The alarms can be masked so they do not cause an interrupt by setting the corresponding interrupt alarm mask bit to 1. A 0 in the mask bit allows the interrupt to be generated. The interrupt registers are categorized into three levels, a base level, and two levels of binning registers, which accumulate alarm conditions that were not masked from the previous level. These binning registers facilitate a faster identification of the alarm condition by the controlling software. Each level has a corresponding interrupt mask register. On the bottom level, there are alarm registers which have a bit per STS-1 for each path status condition. There is a matching alarm mask to mask out individual bits. If the alarm condition for that STS-1 occurs and the alarm mask bit is not set, then an interrupt is generated and the bit in the binning register above will read set. If the interrupt mask is not set for that binning register, then the condition will appear in the top-level register. Only the bottom-level registers have storage, and to remove the alarm flag, it is necessary only to clear the bottomlevel register (either with a write-one-clear or a read depending on the clear read/write control bit). If the interrupt alarm mask bits are set for the bottom level, then no interrupts can be caused, but that condition can be detected by polling this bottom-level register. Note: If an error condition occurs for an STS-Nc, the condition will be reflected in the head STS-1 of the concatenation. Agere Systems Inc. 413 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions 0x8000 ID REGISTER 0x800F INTERRUPTS 0x820F MASKS 0x8300 PATH TRACE 0x8382 PERSISTENCY STATE 0x83C2 0x8400 SF DETECT/CLEAR CONCATENATION MAP AIS-P GENERAL CONTROL 0x8580 PP CONTROL 0x8600 PATH PROVISIONING 0x8502 0x8542 0x8690 PATH MAINTENANCE 0x8702 INTERPRETER INCREMENT/DECREMENT (PM) 0x8780 POH PM 0x8800 CV COUNT PM 0x8880 REI COUNT PM 0x8900 RESERVED RDI, C2, PDI 1699(F).ar.1 Figure 54. Overview of RXT Register Map 414 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 329. RXT_IDR, RXT Identification Register (RO, Fixed Value) Address 0x8000 Bit 15:0 Name RXT_ID[15:0] Function RXT Identification Register. Reset Default 0001 Table 330. PP_CORWR, PP Clear on Read/Write Register (R/W, Control) Address 0x8001 Bit 15:1 0 Name -- RXT_CORW Reserved. RXT Clear on Read/Write. Sets the mode for clearing alarm bit in the RXT block. 0 = Clear interrupt bits by writing 1 to that bit in the alarm register. 1 = Clear all alarm bits in an interrupt alarm register by reading that register. Note: This affects only the RXT interrupt alarms, i.e., only the ones listed in this section (RXT) of the data sheet. Function Reset Default 0 0 Agere Systems Inc. 415 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Interrupts Table 331. RXT_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) Address 0x800F Bit 15:3 2 Name -- Reserved. 0 = PDI alarm delta has not been detected for any STS-1 in any bytestream. 1 = PDI alarm delta has been detected for one or more STS-1s in one or more bytestreams. Payload Defect Indicator (PDI) Alarm Binning. 0 = PDI alarm has not been detected for any STS-1 in any bytestream. 1 = PDI alarm has been detected for one or more STS-1s in one or more bytestreams. J1 Access Complete Alarm Binning. The alarm can be masked from contributing to the RXT interrupt by either registers 0x820F bit 0 (Table 363) or 0x82E0 bit 0 (Table 392). 0 = J1 access complete alarm has not been detected for any STS-1 in any bytestream. 1 = J1 access complete alarm has been detected for one or more STS-1s in one or more bytestreams. Function Reset Default 0 0 RXT_PDI_ALMDBN Payload Defect Indicator (PDI) Alarm Delta Binning. 1 RXT_PDI_ALMBN 0 0 RXT_J1ACCMP_ ALMBN 0 416 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 331. RXT_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) (continued) Address 0x8010 Bit 15 Name Function Reset Default 0 RXT_RDI_ALMDBN Remote Defect Indicator Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. Payload Label Mismatch Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. Unequipped Received Alarm Delta Binning. 14 RXT_PLM_ ALMDBN 0 13 12 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. RXT_AIS_ALMDBN Alarm Indicator Signal Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. Loss of Pointer Alarm Delta Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. J1 Mismatch Alarm Binning. 0 = J1 buffer access not complete. 1 = J1 buffer access complete. J1 Validated Alarm Binning. 0 = J1 buffer access not complete. 1 = J1 buffer access complete. Unsupported Concatenation Alarm Binning. 0 = None of the four bytestreams has an unsupported concatenation. 1 = One of the four bytestreams has an unsupported concatenation. Concatenation Mismatch Alarm Binning. 0 = None of the four bytestreams has a concatenation mismatch. 1 = One of the four bytestreams has a concatenation mismatch. RXT_UNEQR_ ALMDBN 0 0 11 RXT_LOP_ ALMDBN 0 10 RXT_J1MM_ ALMBN RXT_J1VLD_ ALMBN RXT_USCNCT_ ALMBN 0 9 0 8 0 7 RXT_CNCTMM_ ALMBN 0 Agere Systems Inc. 417 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 331. RXT_POH_ALMBNR[1--2], Path Overhead Alarm Status Binning Register (RO) (continued) Address 0x8010 Bit 6 5 Name -- RXT_SF_ALMBN Reserved. Signal Fail Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 4 RXT_RDI_ALMBN Remote Defect Indicator Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 3 RXT_PLM_ALMBN Payload Label Mismatch Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 2 RXT_UNEQR_ ALMBN Unequipped Received Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. Alarm Indicator Signal Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 RXT_LOP_ALMBN Loss of Pointer Alarm Binning. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 0 0 0 0 Function Reset Default -- 0 1 RXT_AIS_ALMBN 418 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 332. RXT_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A--D (RO) Address 0x8031 Bit 15:4 3:0 Name -- RXT_SF_ ALMBNBS[A--D] Reserved. Signal Fail Binning Bytestream A--D. 0 = Signal fail has not been detected for any STS-1s in bytestream A--D. 1 = Signal fail has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 333. RXT_TSSF_ALMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSSF_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Signal Fail Bytestream A--D. 0 = Signal fail has not been detected. 1 = Signal fail has been detected. Table 334. RXT_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A--D (RO) Address 0x8041 Bit 15:4 3:0 Name -- RXT_RDI_ ALMBNBS[A--D] Reserved. Remote Defect Indicator Binning Bytestream A--D. 0 = Remote defect indicator has not been detected for any STS-1s in bytestream A--D. 1 = Remote defect indicator has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x8032, 15:12 0x8033, 11:0 0x8034, 0x8035 Table 335. RXT_TSRDI_ALMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSRDI_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Bytestream A--D. 0 = Remote defect indicator has not been detected. 1 = Remote defect indicator has been detected. Function Reset Default 0 0 0x8042, 15:12 0x8043, 11:0 0x8044, 0x8045 Agere Systems Inc. 419 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 336. RXT_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A--D (RO) Address 0x8051 Bit 15:4 3:0 Name -- RXT_PLM_ ALMBNBS[A--D] Reserved. Payload Label Mismatch Binning Bytestream A--D. 0 = Payload label mismatch has not been detected for any STS-1s in bytestream A--D. 1 = Payload label mismatch has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 337. RXT_TSPLM_ALMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSPLM_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Bytestream A--D. 0 = Payload label mismatch has not been detected. 1 = Payload label mismatch has been detected. Table 338. RXT_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A--D (RO) Address 0x8061 Bit 15:4 3:0 Name -- RXT_UNEQR_ ALMBNBS[A--D] Reserved. Unequipped Received Binning Bytestream A--D. 0 = Unequipped received has not been detected for any STS-1s in bytestream A--D. 1 = Unequipped received has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x8052, 15:12 0x8053, 11:0 0x8054, 0x8055 Table 339. RXT_TSUNEQR_ALMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Bytestream A-- D (RO, COR/COW) Address Bit Name Function Reset Default 0 0 -- Reserved. 0x8062, 15:12 0x8063, 11:0 RXT_TSUNEQR_ALMBS Time Slot 1--Time Slot 12 Unequipped Received 0x8064, [A--D][1--12] Bytestream A--D. 0x8065 0 = Unequipped received has not been detected. 1 = Unequipped received has been detected. 420 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 340. RXT_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A--D (RO) Address 0x8071 Bit 15:4 3:0 Name -- RXT_AIS_ ALMBNBS[A--D] Reserved. Alarms Indicator Signal Binning Bytestream A--D. 0 = Alarms indicator signal has not been detected for any STS-1s in bytestream A--D. 1 = Alarms indicator signal has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 341. PP_TSAIS_ALMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- PP_TSAIS_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarms Indicator Signal Bytestream A--D. 0 = Alarms indicator signal has not been detected. 1 = Alarms indicator signal has been detected. Table 342. RXT_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A--D (RO) Address 0x8081 Bit 15:4 3:0 Name -- RXT_LOP_ ALMBNBS[A--D] Reserved. Loss of Pointer Binning Bytestream A--D. 0 = Loss of pointer has not been detected for any STS-1s in bytestream A--D. 1 = Loss of pointer has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 1 0x8072, 15:12 0x8073, 11:0 0x8074, 0x8075 Table 343. RXT_TSLOP_ALMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSLOP_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Bytestream A--D. 0 = Loss of pointer has not been detected. 1 = Loss of pointer has been detected. Function Reset Default 0 1 0x8082, 15:12 0x8083, 11:0 0x8084, 0x8085 Agere Systems Inc. 421 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 344. RXT_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW) Address 0x8091 Bit 15:4 3:0 Name -- RXT_CNCTMM_ ALMBNBS[A--D] Reserved. Concatenation Map Mismatch Binning Bytestream A--D. 0 = No expected/received concatenation state mismatches on any time slot. 1 = Expected/received concatenation state mismatch in at least one time slot. Table 345. RXT_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning Bytestream A--D (RO, COR/COW) Address 0x80A1 Bit 15:4 3:0 Name -- RXT_USCNCTM_ ALMBNBS[A--D] Reserved. Unsupported Concatenation Map Binning Bytestream A--D. 0 = No path alarm. 1 = Alarm detected. Table 346. RXT_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning Bytestream A--D (RO, COR/COW) Address 0x80C1 Bit 15:4 3:0 Name -- RXT_J1NVLDMSG_ ALMBNBS[A--D] Reserved. J1 New Validated Message Binning Bytestream A--D. 0 = No path alarm. 1 = Alarm detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 Table 347. RXT_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW) Address 0x80D1 Bit 15:4 3:0 Name -- RXT_J1MSGMM_ ALMBNBS[A--D] Reserved. J1 Message Mismatch Binning Bytestream A--D. 0 = No path alarm. 1 = Alarm detected. Function Reset Default 0 0 422 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 348. RXT_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A--D (RO) Address 0x8101 Bit 15:4 3:0 Name -- RXT_PDI_ ALMBNBS[A--D] Reserved. Payload Defect Indicator Binning Bytestream A--D. 0 = Payload defect indicator has not been detected for any STS-1s in bytestream A--D. 1 = Payload defect indicator has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 349. RXT_TSPDI_ALMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSPDI_ALMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Bytestream A--D. 0 = Payload defect indicator has not been detected. 1 = Payload defect indicator has been detected. Table 350. RXT_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) Address 0x8111 Bit 15:4 3:0 Name -- RXT_RDI_ALMDBNBS [A--D] Reserved. Remote Defect Indicator Delta Binning Bytestream A--D. 0 = Remote defect indicator delta has not been detected for any STS-1s in bytestream A--D. 1 = Remote defect indicator delta has been detected for one or more STS-1s in bytestream A--D. Table 351. RXT_TSRDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSRDI_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Delta Bytestream A--D. 0 = Remote defect indicator delta has not been detected. 1 = Remote defect indicator delta has been detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 0x8102, 15:12 0x8103, 11:0 0x8104, 0x8105 0x8112, 15:12 0x8113, 11:0 0x8114, 0x8115 Agere Systems Inc. 423 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 352. RXT_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Bytestream A--D (RO) Address 0x8121 Bit 15:4 3:0 Name -- RXT_PLM_ALMDBNBS [A--D] Reserved. Payload Label Mismatch Delta Binning Bytestream A--D. 0 = Payload label mismatch delta has not been detected for any STS-1s in bytestream A--D. 1 = Payload label mismatch delta has been detected for one or more STS-1s in bytestream A--D. Table 353. RXT_TSPLM_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSPLM_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Delta Bytestream A--D. 0 = Payload label mismatch delta has not been detected. 1 = Payload label mismatch delta has been detected. Table 354. RXT_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Bytestream A--D (RO) Address 0x8131 Bit 15:4 3:0 Name -- RXT_UNEQR_ ALMDBNBS[A--D] Reserved. Unequipped Received Delta Binning Bytestream A--D. 0 = Unequipped received delta has not been detected for any STS-1s in bytestream A--D. 1 = Unequipped received delta has been detected for one or more STS-1s in bytestream A--D. Table 355. RXT_TSUNEQR_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSUNEQR_ ALMDBS[A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Unequipped Received Delta Bytestream A--D. 0 = Unequipped received delta has not been detected. 1 = Unequipped received delta has been detected. 424 Agere Systems Inc. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 6 0x8122, 15:12 0x8123, 11:0 0x8124, 0x8125 0x8132, 15:12 0x8133, 11:0 0x8134, 0x8135 Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 356. RXT_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Bytestream A--D (RO) Address 0x8141 Bit 15:4 3:0 Name -- RXT_AIS_ ALMDBNBS[A--D] Reserved. Alarm Indicator Signal Delta Binning Bytestream A--D. 0 = Alarm indicator signal delta has not been detected for any STS-1s in bytestream A--D. 1 = Alarm indicator signal delta has been detected for one or more STS-1s in bytestream A--D. Table 357. RXT_TSAIS_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSAIS_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarm Indicator Signal Delta Bytestream A--D. 0 = Alarm indicator signal delta has not been detected. 1 = Alarm indicator signal delta has been detected. Table 358. RXT_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Bytestream A--D (RO) Address 0x8151 Bit 15:4 3:0 Name -- RXT_LOP_ ALMDBNBS[A--D] Reserved. Loss of Pointer Delta Binning Bytestream A--D. 0 = Loss of pointer delta has not been detected for any STS-1s in bytestream A--D. 1 = Loss of pointer delta has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 1 Function Reset Default 0 0 0x8142, 15:12 0x8143, 11:0 0x8144, 0x8145 Table 359. RXT_TSLOP_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSLOP_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Delta Bytestream A--D. 0 = Loss of pointer delta has not been detected. 1 = Loss of pointer delta has been detected. Function Reset Default 0 1 0x8152, 15:12 0x8153, 11:0 0x8154, 0x8155 Agere Systems Inc. 425 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 360. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW) Address 0x8160 Bit 15:1 0 Name -- RXT_J1BFACCMPI Reserved. J1 Buffer Access Complete Interrupt. 0 = No alarm. 1 = Alarm detected. Table 361. RXT_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Bytestream A--D (RO) Address 0x8171 Bit 15:4 3:0 Name -- RXT_PDI_ ALMDBNBS[A--D] Reserved. Payload Defect Indicator Delta Binning Bytestream A--D. 0 = Payload defect indicator delta has not been detected for any STS-1s in bytestream A--D. 1 = Payload defect indicator delta has been detected for one or more STS-1s in bytestream A--D. Table 362. RXT_TSPDI_ALMDBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Bytestream A--D (RO, COR/COW) Address Bit Name -- RXT_TSPDI_ALMDBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Delta Bytestream A--D. 0 = Payload defect indicator delta has not been detected. 1 = Payload defect indicator delta has been detected. Function Reset Default 0 0 Function Reset Default 0 0 Function Reset Default 0 0 0x8172, 15:12 0x8173, 11:0 0x8174, 0x8175 426 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Masks Table 363. RXT_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) Address 0x820F Bit 15:3 2 Name -- RXT_PDI_ALMDBNM Reserved. Payload Defect Indicator (PDI) Alarm Delta Binning Mask. 0 = PDI delta alarm is passed through. 1 = PDI delta alarm masked. 1 RXT_PDI_ALMBNM Payload Defect Indicator (PDI) Alarm Binning Mask. 0 = PDI alarm is passed through. 1 = PDI alarm masked. 0 RXT_J1ACCMP_ ALMBNM J1 Access Complete Alarm Binning Mask. Setting this bit to a 1 masks the interrupt from contributing to the RXT interrupt. Setting this bit to a 0 and register 0x82E0 bit 0 (Table 392) to a 0 allows the interrupt to contribute to the RXT interrupt. 0 = J1 access complete alarm is passed through. 1 = J1 access complete alarm masked. 1 1 Function Reset Default -- 1 Agere Systems Inc. 427 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 363. RXT_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) (continued) Address 0x8210 Bit 15 Name RXT_RDI_ALMDBNM Function Remote Defect Indicator Alarm Delta Binning Mask. 0 = Remote defect indicator delta alarm is passed through. 1 = Remote defect indicator delta alarm masked. 14 RXT_PLM_ALMDBNM Payload Label Mismatch Alarm Delta Binning Mask. 0 = Payload label mismatch delta alarm is passed through. 1 = Payload label mismatch delta alarm masked. 13 RXT_UNEQR_ALMDBNM Unequipped Received Alarm Delta Binning Mask. 0 = Unequipped received delta alarm is passed through. 1 = Unequipped received delta alarm masked. 12 RXT_AIS_ALMDBNM Alarm Indicator Signal Alarm Delta Binning Mask. 0 = Alarm indicator signal delta alarm is passed through. 1 = Alarm indicator signal delta alarm masked. 11 RXT_LOP_ALMDBNM Loss of Pointer Alarm Delta Binning Mask. 0 = Loss of pointer delta alarm is passed through. 1 = Loss of pointer delta alarm masked. 10 RXT_J1MM_ALMBNM J1 Mismatch Alarm Binning Mask. 0 = J1 mismatch alarm is passed through. 1 = J1 mismatch alarm masked. 9 RXT_J1VLD_ALMBNM J1 Validated Alarm Binning Mask. 0 = J1 validated alarm is passed through. 1 = J1 validated alarm masked. 8 RXT_USCNCT_ALMM Unsupported Concatenation Alarm Binning Mask. 0 = Unsupported concatenation alarm is passed through. 1 = Unsupported concatenation alarm masked. 7 RXT_CNCTMM_ALMBNM Concatenation Mismatch Alarm Binning Mask. 0 = Concatenation mismatch alarm is passed through. 1 = Concatenation mismatch alarm masked. 6 5 -- RXT_SF_ALMBNM Reserved. Signal Fail Alarm Binning Mask. 0 = Signal fail alarm is passed through. 1 = Signal fail alarm masked. -- 1 1 1 1 1 1 1 1 1 Reset Default 1 428 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 363. RXT_POH_ALMBNMR[1--2], Path Overhead Alarm Status Binning Masks (R/W) (continued) Address 0x8210 Bit 4 Name RXT_RDI_ALMBNM Function Remote Defect Indicator Alarm Binning Mask. 0 = Remote defect indicator alarm is passed through. 1 = Remote defect indicator alarms masked. 3 RXT_PLM_ALMBNM Payload Label Mismatch Alarm Binning Mask. 0 = Payload label mismatch alarm is passed through. 1 = Payload label mismatch alarms masked. 2 RXT_UNEQR_ALMBNM Unequipped Received Alarm Binning Mask. 0 = Unequipped received alarm is passed through. 1 = Unequipped received alarms masked. 1 RXT_AIS_ALMBNM Alarm Indicator Signal Alarm Binning Mask. 0 = Alarm indicator signal alarm is passed through. 1 = Alarm indicator signal alarms masked. 0 RXT_LOP_ALMBNM Loss of Pointer Alarm Binning Mask. 0 = Loss of pointer alarm is passed through. 1 = Loss of pointer alarms masked. Table 364. RXT_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8221 Bit 15:4 3:0 Name -- RXT_SF_ ALMBNMBS[A--D] Reserved. Signal Fail Binning Masks Bytestream A--D. 0 = Signal fail alarms in bytestream A are passed through. 1 = Signal fail alarms in bytestream A are masked. Function Reset Default -- 1111 1 1 1 1 Reset Default 1 Table 365. RXT_TSSF_ALMMBSR[A--D], Time Slots 1--12 Signal Fail Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSSF_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Signal Fail Masks Bytestream A--D. Function Reset Default -- 1 0x8222, 15:12 0x8223, 11:0 0x8224, 0x8225 Agere Systems Inc. 429 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 366. RXT_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8231 Bit 15:4 3:0 Name -- RXT_RDI_ ALMBNMBS[A--D] Reserved. Remote Defect Indicator Binning Masks Bytestream A--D. 0 = Remote defect indicator alarms in bytestream A--D are passed through. 1 = Remote defect indicator alarms in bytestream A--D are masked. Table 367. RXT_TSRDI_ALMMBSR[A--D], Time Slots 1--12 Remote Defect Indicator Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSRDI_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x8232, 15:12 0x8233, 11:0 0x8234, 0x8235 Table 368. RXT_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8241 Bit 15:4 3:0 Name -- RXT_PLM_ ALMBNMBS[A--D] Reserved. Payload Label Mismatch Binning Masks Bytestream A--D. 0 = Payload label mismatch alarms in bytestream A--D are passed through. 1 = Payload label mismatch alarms in bytestream A--D are masked. Table 369. RXT_TSPLM_ALMMBSR[A--D], Time Slots 1--12 Payload Label Mismatch Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSPLM_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Label Mismatch Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x8242, 15:12 0x8243, 11:0 0x8244, 0x8245 430 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 370. RXT_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8251 Bit 15:4 3:0 Name -- RXT_UNEQR_ ALMBNMBS[A--D] Reserved. Unequipped Received Binning Masks Bytestream A--D. 0 = Unequipped received alarms in bytestream A--D are passed through. 1 = Unequipped received alarms in bytestream A--D are masked. Table 371. RXT_TSUNEQR_ALMMBSR[A--D], Time Slots 1--12 Unequipped Received Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSUNEQR_ ALMMBS[A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Unequipped Received Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x8252, 15:12 0x8253, 11:0 0x8254, 0x8255 Table 372. RXT_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8261 Bit 15:4 3:0 Name -- RXT_AIS_ ALMBNMBS[A--D] Reserved. Alarms Indicator Signal Binning Masks Bytestream A--D. 0 = Alarms indicator signal alarms in bytestream A--D are passed through. 1 = Alarms indicator signal alarms in bytestream A--D are masked. Table 373. RXT_TSAIS_ALMMBSR[A--D], Time Slots 1--12 Alarms Indicator Signal Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSAIS_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarms Indicator Signal Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x8262, 15:12 0x8263, 11:0 0x8264, 0x8265 Agere Systems Inc. 431 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 374. RXT_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8271 Bit 15:4 3:0 Name -- RXT_LOP_ ALMBNMBS[A--D] Reserved. Loss of Pointer Binning Masks Bytestream A--D. 0 = Loss of pointer alarms in bytestream A--D are passed through. 1 = Loss of pointer alarms in bytestream A--D are masked. Function Reset Default -- 1 Table 375. RXT_TSLOP_ALMMBSR[A--D], Time Slots 1--12 Loss of Pointer Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSLOP_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer Masks Bytestream A--D. Function Reset Default -- 1 0x8272, 15:12 0x8273, 11:0 0x8274, 0x8275 Table 376. RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A--D (R/W) Address 0x8277 Bit 15:4 3:0 Name -- RXT_CNCTMM_ ALMMBS[A--D] Reserved. Concatenation Map Mismatch Mask Bytestream A--D. 0 = Path alarm is passed through. 1 = Path alarm is masked. Function Reset Default -- 1 Table 377. RXT_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks Bytestream A--D (R/W) Address 0x8279 Bit 15:4 3:0 Name -- RXT_USCNCTM_ ALMMBS[A--D] Reserved. Unsupported Concatenation Map Mask Bytestream A--D. 0 = Alarm is passed through. 1 = Alarm is masked. Function Reset Default -- 1 432 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 378. RXT_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks Bytestream A--D (R/W) Address 0x827B Bit 15:4 3:0 Name -- RXT_J1NVLDMSG ALMMBS[A--D] Reserved. J1 New Validated Message Mask Bytestream A--D. 0 = Alarm is passed through. 1 = Alarm is masked. Function Reset Default -- 1 Table 379. RXT_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks Bytestream A--D (R/W) Address 0x827D Bit 15:4 3:0 Name -- RXT_J1MSGMM_ ALMMBS[A--D] Reserved. J1 Message Mismatch Mask Bytestream A--D. 0 = Alarm is passed through. 1 = Alarm is masked. Function Reset Default -- 1 Table 380. RXT_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks Bytestream A--D (R/W) Address 0x8281 Bit 15:4 3:0 Name -- RXT_PDI_ ALMBNMBS[A--D] Reserved. Payload Defect Indicator Binning Masks Bytestream A--D. 0 = Payload defect indicator alarms in bytestream A--D are passed through. 1 = Payload defect indicator alarms in bytestream A--D are masked. Table 381. RXT_TSPDI_ALMMBSR[A--D], Time Slots 1--12 Payload Defect Indicator Alarm Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSPDI_ALMMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Masks Bytestream A--D. Function Reset Default 0 1 Function Reset Default 0 1 0x8282, 15:12 0x8283, 11:0 0x8284, 0x8285 Agere Systems Inc. 433 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 382. RXT_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x8291 Bit 15:4 3:0 Name -- Reserved. Function Reset Default -- 1 RXT_RDI_ALMDBNMBS Remote Defect Indicator Delta Binning Masks [A--D] Bytestream A--D. 0 = Remote defect indicator delta alarms in bytestream A--D are passed through. 1 = Remote defect indicator delta alarms in bytestream A--D are masked. Table 383. RXT_TSRDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Remote Defect Indicator Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSRDI_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Remote Defect Indicator Delta Masks Bytestream A--D. Function Reset Default -- 1 0x8292, 15:12 0x8293, 11:0 0x8294, 0x8295 Table 384. RXT_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x82A1 Bit 15:4 3:0 Name -- Reserved. Function Reset Default -- 1 RXT_PLM_ALMDBNMBS Payload Label Mismatch Delta Binning Masks [A--D] Bytestream A--D. 0 = Payload label mismatch delta alarms in bytestream A--D are passed through. 1 = Payload label mismatch delta alarms in bytestream A--D are masked. Table 385. RXT_TSPLM_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Label Mismatch Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name Function Reset Default -- 1 -- Reserved. 0x82A2, 15:12 0x82A3, 11:0 RXT_TSPLM_ALMDMBS Time Slot 1--Time Slot 12 Payload Label Mismatch 0x82A4, [A--D][1--12] Delta Masks Bytestream A--D. 0x82A5 434 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 386. RXT_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x82B1 Bit 15:4 3:0 Name -- RXT_UNEQR_ ALMDBNMBS[A--D] Reserved. Unequipped Received Delta Binning Masks Bytestream A--D. 0 = Unequipped received delta alarms in bytestream A--D are passed through. 1 = Unequipped received delta alarms in bytestream A--D are masked. Table 387. RXT_TSUNEQR_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Unequipped Received Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- Reserved. Function Reset Default -- 1 Function Reset Default -- 1 0x82B2, 15:12 0x82B3, 11:0 0x82B4, 0x82B5 RXT_TSUNEQR_ Time Slot 1--Time Slot 12 Unequipped Received Delta ALMDMBS[A--D][1--12] Masks Bytestream A--D. Table 388. RXT_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x82C1 Bit 15:4 3:0 Name -- RXT_AIS_ ALMDBNMBS[A--D] Reserved. Alarm Indicator Signal Delta Binning Masks Bytestream A--D. 0 = Alarm indicator signal delta alarms in bytestream A--D are passed through. 1 = Alarm indicator signal delta alarms in bytestream A--D are masked. Table 389. RXT_TSAIS_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Alarm Indicator Signal Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSAIS_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarm Indicator Signal Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x82C2, 15:12 0x82C3, 11:0 0x82C4, 0x82C5 Agere Systems Inc. 435 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 390. RXT_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x82D1 Bit 15:4 3:0 Name -- RXT_LOP_ ALMDBNMBS[A--D] Reserved. Loss of Pointer Delta Binning Masks Bytestream A--D. 0 = Loss of pointer delta alarms in bytestream A--D are passed through. 1 = Loss of pointer delta alarms in bytestream A--D are masked. Table 391. RXT_TSLOP_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Loss of Pointer Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name Function Reset Default -- 1 Function Reset Default -- 1 -- Reserved. 0x82D2, 15:12 0x82D3, 11:0 RXT_TSLOP_ALMDMBS Time Slot 1--Time Slot 12 Loss of Pointer Delta Masks 0x82D4, [A--D][1--12] Bytestream A--D. 0x82D5 Table 392. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W) Address 0x82E0 Bit 15:1 0 Name -- RXT_J1BFACCMPIM Reserved. J1 Buffer Access Complete Mask. Setting this bit to a 1 masks the interrupt from contributing to the RXT interrupt. Setting this bit to a 0 and register 0x820F bit 0 (Table 363) to a 0 allows the interrupt to contribute to the RXT interrupt. 0 = Alarm is passed through. 1 = Alarm is masked. Function Reset Default -- 1 436 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 393. RXT_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning Masks Bytestream A--D (R/W) Address 0x82E9 Bit 15:4 3:0 Name -- RXT_PDI_ ALMDBNMBS[A--D] Reserved. Payload Defect Indicator Delta Binning Masks Bytestream A--D. 0 = Payload defect indicator delta alarms in bytestream A--D are passed through. 1 = Payload defect indicator delta alarms in bytestream A--D are masked. Table 394. RXT_TSPDI_ALMDMBSR[A--D], Path Overhead STS-1 Time Slots 1--12 Payload Defect Indicator Alarm Delta Masks Bytestream A--D (R/W) Address Bit Name -- RXT_TSPDI_ALMDMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Payload Defect Indicator Delta Masks Bytestream A--D. Function Reset Default -- 1 Function Reset Default -- 1 0x82EA, 15:12 0x82EB, 11:0 0x82EC, 0x82ED Agere Systems Inc. 437 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Path Trace Table 395. RXT_PTRBFR[1--32], Path Trace Buffer Registers 1--32 (R/W) Address 0x8300 -- 0x831F Bit 15:8 7:0 Name RXT_J1BYTE1[7:0] RXT_J1BYTE0[7:0] Function J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer. J1 Byte 0, 2, 6, . . . , 62 Path Trace Buffer. Reset Default 0 0 Table 396. RXT_PTRACCTLR1, Path Trace Access Control Register 1 (R/W) Address 0x8330 Bit 15:2 1:0 Name -- Reserved. 00 = Bytestream A. 01 = Bytestream B. 10 = Bytestream C. 11 = Bytestream D. Table 397. RXT_PTRACCTLR2, Path Trace Access Control Register 2 (R/W) Address 0x8331 Bit 15:1 0 Name -- RXT_J1BF_MSGSEL Reserved. J1 Buffer Message Type Select (Compare/ Received Message). Function Reset Default 0 0 Function Reset Default 0 0 RXT_J1TS1_CHSEL[1:0] J1 Time Slots 1 Channel Select. Table 398. RXT_PTRACCTLR3, Path Trace Access Control Register 3 (R/W) Address 0x8332 Bit 15:1 0 Name -- RXT_J1BF_ACTYP Reserved. J1 Buffer Access Type (Read/ Write). 0 = read, 1 = write. Function Reset Default 0 0 Table 399. RXT_PTRACBGR, Path Trace Access Begin (WO) Address 0x8333 Bit 15:1 0 Name -- RXT_J1_ACBG Reserved. J1 Access Begin. A J1 access complete interrupt, through the RXT interrupt chain, will be generated from 823 ns to 8 ms after writing this bit to a 1. This bit will return 0 after the access is complete. Function Reset Default 0 0 438 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 400. RXT_STS12PTRCTLR[1--6], STS-12 Channel Path Trace Control Registers 1--6 (R/W) Address 0x8338 Bit 15:4 3:0 0x8339 15:4 3:0 Name -- RXT_J1MSG_MSEL [A--D] -- RXT_J1MSG_TYPSEL [A--D] Reserved. J1 Message Mode Select (Validated/Provisioned) Bytestream A--D. Reserved. J1 Message Type Select (SDH/SONET) Bytestream A--D. 0 = SONET. 1 = SDH. 0x833C, 0x833D, 0x833E, 0x833F 15:4 3:0 -- RXT_TSSEL_J1 [A--D][3:0] Reserved. Time Slots 1--12 Select for J1 Accumulation Bytestream A--D. 1111 = Reserved. 1110 = Reserved. 1101 = Reserved. 1100 = STS-1 #12 time slot 12. 1011 = STS-1 #11 time slot 8. 1010 = STS-1 #10 time slot 4. 1001 = STS-1 #9 time slot 11. 1000 = STS-1 #8 time slot 7. 0111 = STS-1 #7 time slot 3. 0110 = STS-1 #6 time slot 10. 0101 = STS-1 #5 time slot 6. 0100 = STS-1 #4 time slot 2. 0011 = STS-1 #3 time slot 9. 0010 = STS-1 #2 time slot 5. 0001 = STS-1 #1 time slot 1. 0000 = Reserved. 0 0 Function Reset Default 0 1 0 0 Agere Systems Inc. 439 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Persistency Table 401. RXT_TSRDI_ALMPSBSR[A--D], Time Slots 1--12 RDI Alarm Persistency Bytestream A--D (RO) Address Bit Name -- RXT_TSRDI_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 RDI Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x8382, 15:12 0x8383, 11:0 0x8384, 0x8385 Table 402. RXT_TSPLM_ALMPSBSR[A--D], Time Slots 1--12 PLM Alarm Persistency Bytestream A--D (RO) Address Bit Name Function Reset Default 0 0 -- Reserved. 0x838A, 15:12 0x838B, 11:0 RXT_TSPLM_ALMPSBS Time Slots 1--12 Payload Label Mismatch Alarm 0x838C, [A--D][1--12] Persistency Bytestream A--D. 0x838D Table 403. RXT_TSPUNEQ_ALMPSBSR[A--D], Time Slots 1--12 Path Unequipped Alarm Persistency Bytestream A--D (RO) Address Bit Name -- RXT_TSPUNEQ_ ALMPSBS[A--D][1--12] Reserved. Time Slots 1--12 Path Unequipped Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x8392, 15:12 0x8393, 11:0 0x8394, 0x8395 440 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 404. RXT_TSAIS_ALMPSBSR[A--D], Time Slots 1--12 AIS Alarm Persistency Bytestream A--D (RO) Address Bit Name -- RXT_TSAIS_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 AIS Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x839A, 15:12 0x839B, 11:0 0x839C, 0x839D Table 405. RXT_TSLOP_ALMPSBSR[A--D], Time Slots 1--12 LOP Alarm Persistency Bytestream A--D (RO) Address Bit Name -- Reserved. Function Reset Default 0 0 0x83A2, 15:12 0x83A3, 11:0 0x83A4, 0x83A5 RXT_TSLOP_ALMPSBS Time Slots 1--12 LOP Alarm Persistency Bytestream [A--D][1--12] A--D. Table 406. RXT_TSPDI_ALMPSBSR[A--D], Time Slots 1--12 PDI Alarm Persistency Bytestream A--D (RO) Address Bit Name -- RXT_TSPDI_ALMPSBS [A--D][1--12] Reserved. Time Slots 1--12 PDI Alarm Persistency Bytestream A--D. Function Reset Default 0 0 0x83AA, 15:12 0x83AB, 11:0 0x83AC, 0x83AD Agere Systems Inc. 441 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) State Table 407. RXT_TSRDI_STBSR[A--D], Time Slots 1--12 RDI State Bytestream A--D (RO) Address Bit Name -- RXT_TSRDI_STBS [A--D][1--12] Reserved. Time Slots 1--12 RDI State Bytestream A--D. Function Reset Default 0 0 0x83C2, 15:12 0x83C3, 11:0 0x83C4, 0x83C5 Table 408. RXT_TSPLM_STBSR[A--D], Time Slots 1--12 PLM State Bytestream A--D (RO) Address Bit Name -- RXT_TSPLM_STBS [A--D][1--12] Reserved. Time Slots 1--12 Payload Label Mismatch State Bytestream A--D. Function Reset Default 0 0 0x83CA, 15:12 0x83CB, 11:0 0x83CC, 0x83CD Table 409. RXT_TSPUNEQ_STBSR[A--D], Time Slots 1--12 Path Unequipped State Bytestream A--D (RO) Address Bit Name -- RXT_TSRDI_STBS [A--D][1--12] Reserved. Time Slots 1--12 Path Unequipped State Bytestream A--D. Function Reset Default 0 0 0x83D2, 15:12 0x83D3, 11:0 0x83D4, 0x83D5 442 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 410. RXT_TSAIS_STBSR[A--D], Time Slots 1--12 AIS State Bytestream A--D (RO) Address Bit Name -- RXT_TSAIS_STBS [A--D][1--12] Reserved. Time Slots 1--12 AIS State Bytestream A--D. Function Reset Default 0 0 0x83DA, 15:12 0x83DB, 11:0 0x83DC, 0x83DD Table 411. RXT_TSLOP_STBSR[A--D], Time Slots 1--12 LOP State Bytestream A--D (RO) Address Bit Name -- RXT_TSLOP_STBS [A--D][1--12] Reserved. Time Slots 1--12 LOP State Bytestream A--D. Function Reset Default 0 0 0x83E2, 15:12 0x83E3, 11:0 0x83E4, 0x83E5 Table 412. RXT_TSPDI_STBSR[A--D], Time Slots 1--12 PDI State Bytestream A--D (RO) Address Bit Name -- RXT_TSPDI_STBS [A--D][1--12] Reserved. Time Slots 1--12 PDI State Bytestream A--D. Function Reset Default 0 0 0x83EA, 15:12 0x83EB, 11:0 0x83EC, 0x83ED Agere Systems Inc. 443 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Signal Fail Table 413. RXT_SFWSZ_SELR[1--2], Signal Fail Window Size Select Registers 1--2 (R/W, Control) Address 0x8400 Bit 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Name RXT_SFWSZ_SELSET [0--7][1:0] Function Window Size Select Set Threshold 0--7. 00 = Window size 0. 01 = Window size 1. 10 = Window size 2. 11 = Window size 3. Reset Default 0x1 0x2 0x1 0x2 0x1 0x2 0x1 0x2 0x2 0x3 0x2 0x3 0x2 0x3 0x2 0x3 0x8401 RXT_SFWSZ_SELCLR [0--7][1:0] Window Size Select Clear Threshold 0--7. 00 = Window size 0. 01 = Window size 1. 10 = Window size 2. 11 = Window size 3. 444 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 414. RXT_SFDR[0--7], Signal Fail Detect Threshold Registers 0--7 (R/W, Control) Address 0x8410 Bit 15:9 8:0 Name -- RXT_SFD0[8:0] Reserved. STS-1 Signal Fail Detect Threshold 0. Number of bit/block errors within detection window required to trigger a signal fail. 0x8411 0x8412 0x8413 0x8414 0x8415 0x8416 0x8417 15:9 8:0 15:14 13:0 15:14 13:0 15:14 13:0 15:14 13:0 15:14 13:0 15:14 13:0 -- RXT_SFD1[8:0] -- RXT_SFD2[13:0] -- RXT_SFD3[13:0] -- RXT_SFD4[13:0] -- RXT_SFD5[13:0] -- RXT_SFD6[13:0] -- RXT_SFD7[13:0] Reserved. STS-1 Signal Fail Detect Threshold 1. Reserved. STS-Nc Signal Fail Detect Threshold 2. Reserved. STS-Nc Signal Fail Detect Threshold 3. Reserved. STS-Nc Signal Fail Detect Threshold 4. Reserved. STS-Nc Signal Fail Detect Threshold 5. Reserved. STS-Nc Signal Fail Detect Threshold 6. Reserved. STS-Nc Signal Fail Detect Threshold 7. 0 0x0DE 0 0x0233 0 0x02B2 0 0x3A3 0 0x055E 0 0x51D 0 0x0A62 Function Reset Default 0 0x0CF Agere Systems Inc. 445 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 415. RXT_SFCLRR[0--7], Signal Fail Clear Threshold Registers 0--7 (R/W, Control) Address 0x8418 Bit 15:9 8:0 Name -- RXT_SFCLR0[8:0] Reserved. STS-1 Signal Fail Clear Threshold 0. Number of bit/block errors within detection window permitted when clearing a signal fail. 0x8419 15:9 8:0 0x841A 15:14 13:0 0x841B 15:14 13:0 0x841C 15:14 13:0 0x841D 15:14 13:0 0x841E 15:14 13:0 0x841F 15:14 13:0 -- RXT_SFCLR1[8:0] -- RXT_SFCLR2[13:0] -- RXT_SFCLR3[13:0] -- RXT_SFCLR4[13:0] -- RXT_SFCLR5[13:0] -- RXT_SFCLR6[13:0] -- RXT_SFCLR7[13:0] Reserved. STS-1 Signal Fail Clear Threshold 1. Reserved. STS-Nc Signal Fail Clear Threshold 2. Reserved. STS-Nc Signal Fail Clear Threshold 3. Reserved. STS-Nc Signal Fail Clear Threshold 4. Reserved. STS-Nc Signal Fail Clear Threshold 5. Reserved. STS-Nc Signal Fail Clear Threshold 6. Reserved. STS-Nc Signal Fail Clear Threshold 7. 0 0x115 0 0x030B 0 0x031B 0 0x5D8 0 0x0618 0 0x0B08 0 0x0BFC Function Reset Default 0 0x113 446 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 416. RXT_SFWSZR[0--3], Signal Fail Window Size 0--3 Registers (R/W, Control) Address 0x8420 Bit 15:0 Name RXT_SFWSZ0[15:0] Function Signal Fail Window Size 0 (in 0.5 ms Increments). A setting of zero is the same as 1, will produce a 0.5 ms window size. Signal Fail Window Size 1 (in 0.5 ms Increments). A setting of zero is the same as 1, will produce a 0.5 ms window size. Signal Fail Window Size 2 (in 0.5 ms Increments). A setting of zero is the same as 1, will produce a 0.5 ms window size. Signal Fail Window Size 3 (in 0.5 ms Increments). A setting of zero is the same as 1, will produce a 0.5 ms window size. Reset Default 0x000A 0x8430 15:0 RXT_SFWSZ1[15:0] 0x0064 0x8440 15:0 RXT_SFWSZ2[15:0] 0x03E8 0x8450 15:0 RXT_SFWSZ3[15:0] 0x2710 Signal Fail Window Size Registers: Above are the settings for the length of the four free-running windows that are used in conjunction with the set and clear thresholds for the signal fail detection. This time unit depends on the number of columns in a frame setting. The time unit is four times an STS-frame size, which is 0.5 ms for a system setting of 90 columns. After changing one of these window registers, it will take two time unit pules to occur before this new value is used, i.e., the old window will come to a halt and the new one will begin from 0.5 ms to 1 ms (assuming 90 columns). Agere Systems Inc. 447 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Concatenation The expected concatenation map register is programmed via programmable registers (Table 417) on a per timeslot (STS-1) basis. The concatenation state of each time slot can be read from the received concatenation map register (RXT_RCNCTM_TSBSR[A--D], Received Concatenation Map Time Slots 1--12 in Bytestream A--D (RO), Table 419). Comparison of the expected and received concatenation state is enabled on a per time-slot basis by software setting of the concatenation compare enable register (RXT_CNCTCPREN_TSBSR[A--D], Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D (R/W, Control), Table 418). Alarms are binned on a per bytestream (STS-12) basis in the concatenation map mismatch register (RXT_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A--D (RO, COR/COW), Table 344), and resulting interrupts can be masked by the concatenation map mismatch mask register (see RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A--D (R/W), Table 376); mismatches in the first time slot of a bytestream are special cases. When the expected state of a bytestream is concatenation and the received state is normal, the mismatch status bit for the previous bytestream will be set since the errored time slot is trying to concatenate to an STS-1 in the previous bytestream. Table 417. RXT_ECNCTM_TSBSR[A--D], Expected Concatenation Map Time Slots 1--12 in Bytestream A--D (R/W, Control) Address Bit Name -- RXT_ECNCT_STTSBS [A--D][1--12] Reserved. Expected Concatenation State for Time Slots 1--12 in Bytestream A--D. 0 = Time slot not expected to be in concatenation. 1 = Time slot expected to be in concatenation. Function Reset Default 0 0 0x8502, 15:12 0x8503, 11:0 0x8504, 0x8505 Table 418. RXT_CNCTCPREN_TSBSR[A--D], Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D (R/W, Control) Address Bit Name -- RXT_CNCTCPREN_ TSBS[A--D][1--12] Reserved. Concatenation Compare Enable Time Slots 1--12 in Bytestream A--D. 0 = Inhibit comparison of received and expected concatenation states. 1 = Compare received and expected concatenation states. Function Reset Default 0 0 0x8507, 15:12 0x8508, 11:0 0x8509, 0x850A Table 419. RXT_RCNCTM_TSBSR[A--D], Received Concatenation Map Time Slots 1--12 in Bytestream A--D (RO) Address Bit Name -- RXT_RCNCT_STTSBS [A--D][1--12] Reserved. Received Concatenation State for Time Slots 1--12 in Bytestream A--D. 0 = Concatenation state not detected. 1 = Concatenation state detected. 448 Agere Systems Inc. Function Reset Default 0 0 0x8512, 15:12 0x8513, 11:0 0x8514, 0x8515 Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) AIS Insert Control Table 420. RXT_SWAIS_ISRTR, Software AIS Insert (R/W, Control) Address Bit Name -- RXT_SWAIS_ISRT [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 STS AIS Insert Bytestream A--D. 0 = No AIS insert. 1 = AIS insert. AIS Insert on UNEQ Control Table 421. RXT_AISONUNEQ_PR[A--D], Time Slot 1--Time Slot 12 AIS Insert on UNEQ-P Bytestream A--D (R/W, Control) Address 0x8547, 0x8548, 0x8549, 0x854A Bit 15:12 11:0 Name -- RXT_AISONUNEQ_P [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 AIS Insert on UNEQ-P Bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x8542, 15:12 0x8543, 11:0 0x8544, 0x8545 AIS Insert on PLM Control Table 422. RXT_AISONPLM_PR[A--D], Time Slot 1--Time Slot 12 AIS Insert on PLM-P Bytestream A--D (R/W, Control) Address 0x854C, 0x854D, 0x854E, 0x854F Bit 15:12 11:0 Name -- RXT_AISONPLM_P [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 AIS Insert on PLMP Bytestream A--D. Function Reset Default 0 0 AIS Insert on TIM Control Table 423. RXT_AISONTIM_PR[A--D], Time Slot 1--Time Slot 12 Software AIS Insert on TIM-P Bytestream A--D (R/W, Control) Address 0x8551, 0x8552, 0x8553, 0x8554 Bit 15:12 11:0 Name -- RXT_AISONTIM_P [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 AIS Insert on TIM-P Bytestream A--D. Function Reset Default 0 0 Agere Systems Inc. 449 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Pointer Processor Control Table 424. RXT_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W, Control) Address 0x8580 Bit 15:4 3:0 Name -- RXT_PINCDEC[A--D] Reserved. Pointer Increment/Decrement Rules to Use (SONET/ SDH) Bytestream A--D. Function Reset Default -- 1111 Table 425. RXT_TS_INCDECBNR[A--D], Time Slots 1--12 Increment/Decrement Binning Select Bytestream A--D (R/W, Control) Address 0x8590, 0x8591, 0x8592, 0x8593 Bit 15:4 3:0 Name -- RXT_TS_INCDECBN [A--D][3:0] Reserved. Time Slots 1--12 Increment/Decrement Binning Select Bytestream A--D. 1111 = None selected counter disabled (see note below). 1110 = None selected counter disabled (see note below). 1101 = None selected counter disabled (see note below). 1100 = STS-1 #12 time slot 12. 1011 = STS-1 #11 time slot 8. 1010 = STS-1 #10 time slot 4. 1001 = STS-1 #9 time slot 11. 1000 = STS-1 #8 time slot 7. 0111 = STS-1 #7 time slot 3. 0110 = STS-1 #6 time slot 10. 0101 = STS-1 #5 time slot 6. 0100 = STS-1 #4 time slot 2. 0011 = STS-1 #3 time slot 9. 0010 = STS-1 #2 time slot 5. 0001 = STS-1 #1 time slot 1. 0000 = None selected counter disabled (see note below). Note: Selecting 0, 13, 14, 15 will cause the increment/ decrement counter to remain at its last count until the next PM 1-second pulse when it will clear and remain at 0 thereafter. Function Reset Default -- 0000 (Disabled) 450 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 426. RXT_TSPDIVLD_CTLBSR[A--D], Time Slot 1--Time Slot 12 PDI Validate Control Bytestream A--D (R/W, Control) Address Bit Name Function Reset Default Note: There are four PM increment/decrement counters, increment and decrement for both the interpreter and generator, for each STS-12 group. For a concatenation spanning STS-12 blocks, the select should be set to the head of the concatenation. It is suggested for clarity that counters not being used be disabled by setting them to 0; for example, in an STS-48c, bytestream A increment/decrement binning select should be set to STS-1 #1 and the selects for streams B, C, and D should be set to 0. The increments and decrements for the entire concatenation should then be read from the stream A registers. -- Reserved. 0x85A2, 15:12 0x85A3, 11:0 RXT_TSPDIVLD_CTLBS Time Slot 1--Time Slot 12 PDI Validate Control 0x85A4, [A--D][1--12] Bytestream A--D. 0x85A5 0 = Disables PDI codes. 1 = Enables PDI codes to affect path status byte. -- 0 Agere Systems Inc. 451 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Provisioning Table 427. RXT_EXPC2_PVSNR[1--24], Expected C2 Byte Provisioning (R/W, Control) Address 0x8600 -- 0x8617 Bit 15:8 7:0 Name RXT_EXPC2 [1, 3, 5, . . . , 47][7:0] RXT_EXPC2 [2, 4, 6, . . . , 48][7:0] Function Time Slots 1, 3, 5, 7, 9, . . . , 47 Expected C2 Byte. Time Slots 2, 4, 6, 8, 10, . . . , 48 Expected C2 Byte. Reset Default 0 0 Note: The expected C2 byte is only a programming mode and changing them does not affect the validation counters. Table 428. RXT_TSCBB_ERRBSR[A--D], Time Slot 1--Time Slot 12 Count Block/Bit Errors Bytestream A--D Address Bit Name -- RXT_TSCBB_ERRBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Count Block/Bit Errors Bytestream A--D. Function Reset Default -- 0 0x8618, 15:12 0x8619, 11:0 0x861A, 0x861B 452 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Maintenance Table 429. RXT_TSMNTR[1--48], Time Slots 1--48 Maintenance (R/W, Control) Address 0x8690 -- 0x86BF Bit 15:3 2:0 Name -- RXT_TSSF_TH [1--48][2:0] Reserved. Time Slot 1--Time Slot 48 Signal Fail Threshold Select. This value sets the signal fail threshold for the respective time slot. Function Reset Default 0 0 Interpreter Increment/Decrement PM Table 430. RXT_PI_LSECINCR[A--D], Pointer Interpreter Last Second Increments Bytestream A--D (RO) Address Bit Name -- RXT_PI_LSECINC [A--D][10:0] Reserved. Last Second Increments in Pointer Interpreter Bytestream A--D. Function Reset Default 0 0 0x8702, 15:11 0x8703, 10:0 0x8704, 0x8705 Table 431. RXT_PI_LSECDECR[A--D], Pointer Interpreter Last Second Decrements Bytestream A--D (RO) Address Bit Name -- RXT_PI_LSECDEC [A--D][10:0] Reserved. Last Second Decrements in Pointer Interpreter Bytestream A--D. Function Reset Default 0 0 0x8712, 15:11 0x8713, 10:0 0x8714, 0x8715 Agere Systems Inc. 453 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Performance Monitoring Table 432. RXT_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO) Address 0x8780 Bit 15:7 6 Name -- RXT_1BRDI_DPM Reserved. One-Bit RDI Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 5 RXT_ERDI_PDPM ERDI Payload Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 4 RXT_ERDI_CDPM ERDI Connectivity Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 3 RXT_ERDI_SDPM ERDI Server Defect PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 2 RXT_UNEQR_ALMPM Unequipped Received Alarm PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 1 RXT_AIS_ALMPM Alarm Indicator Signal Alarm PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 RXT_LOP_ALMPM Loss of Pointer Alarm PM. 0 = Alarm has not been detected for any STS-1 in any bytestream. 1 = Alarm has been detected for one or more STS-1s in one or more bytestreams. 0 0 0 0 0 0 Function Reset Default 0 0 454 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 433. RXT_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A--D (RO) Address 0x8781 Bit 15:4 3:0 Name -- RXT_1BRDI_DPMBS [A--D] Reserved. One-Bit RDI Defect PM Bytestream A--D. 0 = One-bit RDI defect PM has not been detected for any STS-1s in bytestream A--D. 1 = One-bit RDI defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 434. RXT_TS1BRDI_DPMBSR[A--D], Path Overhead Time Slots 1--12 One-Bit RDI Defect PM Bytestream A--D (RO) Address Bit Name -- RXT_TS1BRDI_DPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 One-Bit RDI Defect PM Bytestream A--D. Function Reset Default 0 0 0x8782, 15:12 0x8783, 11:0 0x8784, 0x8785 Table 435. RXT_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A--D (RO) Address 0x8791 Bit 15:4 3:0 Name -- RXT_ERDI_PDPMBS [A--D] Reserved. ERDI Payload Defect PM Bytestream A--D. 0 = ERDI payload defect PM has not been detected for any STS-1s in bytestream A--D. 1 = ERDI payload defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 436. RXT_TSERDI_PDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Payload Defect PM Bytestream A--D (RO) Address Bit Name -- RXT_TSERDI_PDPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 ERDI Payload Defect PM Bytestream A--D. Function Reset Default 0 0 0x8792, 15:12 0x8793, 11:0 0x8794, 0x8795 Agere Systems Inc. 455 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 437. RXT_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A--D (RO) Address 0x87A1 Bit 15:4 3:0 Name -- RXT_ERDI_CDPMBS [A--D] Reserved. ERDI Connectivity Defect PM Bytestream A--D. 0 = ERDI connectivity defect PM has not been detected for any STS-1s in bytestream A--D. 1 = ERDI connectivity defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 438. RXT_TSERDI_CDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Connectivity Defect PM Bytestream A--D (RO) Address Bit Name -- RXT_TSERDI_CDPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 ERDI Connectivity Defect PM Bytestream A--D. Function Reset Default 0 0 0x87A2, 15:12 0x87A3, 11:0 0x87A4, 0x87A5 Table 439. RXT_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A--D (RO) Address 0x87B1 Bit 15:4 3:0 Name -- RXT_ERDI_SDPMBS [A--D] Reserved. ERDI Server Defect PM Bytestream A--D. 0 = ERDI server defect PM has not been detected for any STS-1s in bytestream A--D. 1 = ERDI server defect PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 440. RXT_TSERDI_SDPMBSR[A--D], Path Overhead Time Slots 1--12 ERDI Server Defect PM Bytestream A--D (RO) Address Bit Name -- RXT_TSERDI_SDPMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 ERDI Server Defect PM Bytestream A--D. Function Reset Default 0 0 0x87B2, 15:12 0x87B3, 11:0 0x87B4, 0x87B5 456 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 441. RXT_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A--D (RO) Address 0x87C1 Bit 15:4 3:0 Name -- RXT_UNEQR_PMBS [A--D] Reserved. Unequipped Received PM Bytestream A--D. 0 = Unequipped received PM has not been detected for any STS-1s in bytestream A--D. 1 = Unequipped received PM has been detected for one or more STS-1s in bytestream A--D. Function Reset Default 0 0 Table 442. RXT_TSUNEQR_PMBSR[A--D], Path Overhead Time Slots 1--12 Unequipped Received PM Bytestream A--D (RO) Address Bit Name -- RXT_TSUNEQR_PMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Unequipped Received PM Bytestream A--D. Function Reset Default 0 0 0x87C2, 15:12 0x87C3, 11:0 0x87C4, 0x87C5 Table 443. RXT_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A--D (RO) Address 0x87D1 Bit 15:4 3:0 Name -- RXT_AIS_PMBS[A--D] Reserved. Alarm Indicator Signal PM Bytestream A--D. 0 = Alarm indicator signal PM has not been detected for any STS-1s in bytestream A--D. 1 = Alarm indicator signal PM has been detected for one or more STS-1s in bytestream A--D. Table 444. RXT_TSAIS_PMBSR[A--D], Path Overhead Time Slots 1--12 Alarm Indicator Signal PM Bytestream A--D (RO) Address Bit Name -- RXT_TSAIS_PMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Alarm Indicator Signal PM Bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 0x87D2, 15:12 0x87D3, 11:0 0x87D4, 0x87D5 Agere Systems Inc. 457 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) Table 445. RXT_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A--D (RO) Address 0x87E1 Bit 15:4 3:0 Name -- Reserved. 0 = Loss of pointer PM has not been detected for any STS-1s in bytestream A--D. 1 = Loss of pointer PM has been detected for one or more STS-1s in bytestream A--D. Table 446. RXT_TSLOP_PMBSR[A--D], Path Overhead Time Slots 1--12 Loss of Pointer PM Bytestream A--D (RO) Address Bit Name -- RXT_TSLOP_PMBS [A--D][1--12] Reserved. Time Slot 1--Time Slot 12 Loss of Pointer PM Bytestream A--D. Function Reset Default 0 0 Function Reset Default 0 0 RXT_LOP_PMBSR[A--D] Loss of Pointer PM Bytestream A--D. 0x87E2, 15:12 0x87E3, 11:0 0x87E4, 0x87E5 Table 447. RXT_LSECCVP_CPMR[1--48], Last Second CV-P Count Time Slot 1--Time Slot 48 PM (RO) Address 0x8800 -- 0x882F Bit 15:0 Name RXT_LSECCVP_CPM [1--48][15:0] Function Time Slot 1--Time Slot 48 CV Count PM. Reset Default 0 Table 448. RXT_LSECREIP_CPMR[1--48], Last Second REI-P Count Time Slot 1--Time Slot 48 PM (RO) Address 0x8880 -- 0x88AF Bit 15:0 Name RXT_LSECREIP_CPM [1--48][15:0] Function Time Slot 1--Time Slot 48 REI Count PM. Reset Default 0 458 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Descriptions (continued) RDI, C2, and PDI Status Table 449. RXT_TSRDIPR[1--48], Time Slots 1--48 Path RDI Status (RO) Address 0x8900 -- 0x892F Bit 15:3 2:0 Name -- RXT_TS_RRDI [1--48][2:0] Reserved. Time Slot 1--Time Slot 48 Received RDI Code. Function Reset Default 0 0 Table 450. RXT_TSC2R[1--24], Time Slots 1--48 Path C2 Status (RO) Address 0x8930 -- 0x8947 Bit 15:8 7:0 Name RXT_TSRC2 [1, 3, . . . , 47][7:0] RXT_TSRC2 [2, 4, . . . , 48][7:0] Function Time Slots 1, 3, 5, 7, . . . , 47 Received C2 Byte. Time Slots 2, 4, 6, 8, . . . , 48 Received C2 Byte. Reset Default 0x13 0x13 Table 451. RXT_TSPDIR[1--24], Time Slots 1--48 Path PDI Status (RO) Address 0x8960 -- 0x8977 Bit 15:8 7:0 Name RXT_TSRPDI [1, 3, . . . , 47][7:0] RXT_TSRPDI [2, 4, . . . , 48][7:0] Function Time Slots 1, 3, 5, 7, . . . , 47 Received PDI Byte. Time Slots 2, 4, 6, 8, . . . , 48 Received PDI Byte. Reset Default 0 0 Agere Systems Inc. 459 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map Table 452. RXT Register Map Note: Shading denotes reserved bits. Addr 0x8000 0x8001 0x8002 -- 0x800E 0x800F Symbol RXT_IDR RXT_CORWR -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Version Control (RO) RXT_ID[15:0] RXT_ CORW Interrupts RXT_POH_ALMBNR1 RXT_PDI_ RXT_PDI_ ALMDBN ALMBN RXT_RDI_ ALMDBN RXT_PLM _ALMDBN RXT_ UNEQR_ ALMDBN RXT_AIS_ ALMDBN RXT_LOP _ALMDBN RXT_ J1MM_ ALMBN RXT_ J1VLD_ ALMBN RXT_ USCNCT_ ALMBN RXT_ CNCTMM _ALMBN RXT_SF_ ALMBN RXT_RDI_ ALMBN RXT_PLM _ALMBN RXT_ UNEQR_ ALMBN RXT_AIS_ ALMBN RXT_ J1ACCMP _ALMBN RXT_LOP _ALMBN 0x8010 RXT_POH_ALMBNR2 0x8011 -- 0x8030 0x8031 0x8032 0x8033 0x8034 0x8035 0x8036 -- 0x8040 0x8041 0x8042 0x8043 0x8044 0x8045 0x8046 -- 0x8050 -- RXT_SF_ALMBNBSR RXT_TSSF_ALMBSRA RXT_TSSF_ALMBSRB RXT_TSSF_ALMBSRC RXT_TSSF_ALMBSRD -- Signal Fail Alarm per STS-1 Bytestream A RXT_TSSF_ALMBSA[1--12] Signal Fail Alarm per STS-1 Bytestream B RXT_TSSF_ALMBSB[1--12] Signal Fail Alarm per STS-1 Bytestream C RXT_TSSF_ALMBSC[1--12] Signal Fail Alarm per STS-1 Bytestream D RXT_TSSF_ALMBSD[1--12] Signal Fail Binning RXT_SF_ALMBNBS[A--D] RXT_RDI_ALMBNBSR RXT_TSRDI_ALMBSRA RXT_TSRDI_ALMBSRB RXT_TSRDI_ALMBSRC RXT_TSRDI_ALMBSRD -- Remote Defect Indicator Alarm per STS-1 Bytestream A RXT_TSRDI_ALMBSA[1--12] Remote Defect Indicator Alarm per STS-1 Bytestream B RXT_TSRDI_ALMBSB[1--12] Remote Defect Indicator Alarm per STS-1 Bytestream C RXT_TSRDI_ALMBSC[1--12] Remote Defect Indicator Alarm per STS-1 Bytestream D RXT_TSRDI_ALMBSD[1--12] Remote Defect Indicator Alarm Binning RXT_RDI_ALMBNBS[A--D] 460 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8051 0x8052 0x8053 0x8054 0x8055 0x8056 -- 0x8060 0x8061 0x8062 0x8063 0x8064 0x8065 0x8066 -- 0x8070 0x8071 0x8072 0x8073 0x8074 0x8075 0x8076 -- 0x8080 Symbol RXT_PLM_ALMBNBSR RXT_TSPLM_ALMBSRA RXT_TSPLM_ALMBSRB RXT_TSPLM_ALMBSRC RXT_TSPLM_ALMBSRD -- Payload Label Mismatch Alarm per STS-1 Bytestream A RXT_TSPLM_ALMBSA[1--12] Payload Label Mismatch Alarm per STS-1 Bytestream B RXT_TSPLM_ALMBSB[1--12] Payload Label Mismatch Alarm per STS-1 Bytestream C RXT_TSPLM_ALMBSC[1--12] Payload Label Mismatch Alarm per STS-1 Bytestream D RXT_TSPLM_ALMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Payload Label Mismatch Alarm Binning RXT_PLM_ALMBNBS[A--D] RXT_UNEQR_ALMBNBSR RXT_TSUNEQR_ALMBSRA RXT_TSUNEQR_ALMBSRB RXT_TSUNEQR_ALMBSRC RXT_TSUNEQR_ALMBSRD -- Unequipped Received Alarm per STS-1 Bytestream A RXT_TSUNEQR_ALMBSA[1--12] Unequipped Received Alarm per STS-1 Bytestream B RXT_TSUNEQR_ALMBSB[1--12] Unequipped Received Alarm per STS-1 Bytestream C RXT_TSUNEQR_ALMBSC[1--12] Unequipped Received Alarm per STS-1 Bytestream D RXT_TSUNEQR_ALMBSD[1--12] Unequipped Received Alarm Binning RXT_UNEQR_ALMBNBS[A--D] RXT_AIS_ALMBNBSR RXT_TSAIS_ALMBSRA RXT_TSAIS_ALMBSRB RXT_TSAIS_ALMBSRC RXT_TSAIS_ALMBSRD -- Alarm Indicator Signal Alarm per STS-1 Bytestream A RXT_TSAIS_ALMBSA[1--12] Alarm Indicator Signal Alarm per STS-1 Bytestream B RXT_TSAIS_ALMBSB[1--12] Alarm Indicator Signal Alarm per STS-1 Bytestream C RXT_TSAIS_ALMBSC[1--12] Alarm Indicator Signal Alarm per STS-1 Bytestream D RXT_TSAIS_ALMBSD[1--12] Alarm Indicator Signal Alarm Binning RXT_AIS_ALMBNBS[A--D] Agere Systems Inc. 461 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8081 0x8082 0x8083 0x8084 0x8085 0x8086 -- 0x8090 0x8091 0x8092 -- 0x80A0 0x80A1 0x80A2 -- 0x80C0 0x80C1 0x80C2 -- 0x80D0 0x80D1 0x80D2 -- 0x8100 Symbol RXT_LOP_ALMBNBSR RXT_TSLOP_ALMBSRA RXT_TSLOP_ALMBSRB RXT_TSLOP_ALMBSRC RXT_TSLOP_ALMBSRD -- Loss of Pointer Alarm per STS-1 Bytestream A RXT_TSLOP_ALMBSA[1--12] Loss of Pointer Alarm per STS-1 Bytestream B RXT_TSLOP_ALMBSB[1--12] Loss of Pointer Alarm per STS-1 Bytestream C RXT_TSLOP_ALMBSC[1--12] Loss of Pointer Alarm per STS-1 Bytestream D RXT_TSLOP_ALMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Loss of Pointer Alarm Binning RXT_LOP_ALMBNBS[A--D] RXT_CNCTMM_ALMBNBSR -- Concatenation Map Mismatch Alarm Binning RXT_CNCTMM_ALMBNBS[A--D] RXT_USCNCTM_ALMBNBSR -- Unsupported Concatenation Map Alarm Binning RXT_USCNCTM_ALMBNBS[A--D] RXT_J1NVLDMSG_ ALMBNBSR -- J1 New Validated Message Alarm Binning RXT_J1NVLDMSG_ALMBNBS[A--D] RXT_J1MSGMM_ALMBNBSR -- J1 Message Mismatch Alarm Binning RXT_J1MSGMM_ALMBNBS[A--D] 462 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8101 0x8102 0x8103 0x8104 0x8105 0x8106 -- 0x8110 0x8111 0x8112 0x8113 0x8114 0x8115 0x8116 -- 0x8120 0x8121 0x8122 0x8123 0x8124 0x8125 0x8126 -- 0x8130 Symbol RXT_PDI_ALMBNBSR RXT_TSPDI_ALMBSRA RXT_TSPDI_ALMBSRB RXT_TSPDI_ALMBSRC RXT_TSPDI_ALMBSRD -- Payload Defect Indicator Alarm per STS-1 Bytestream A RXT_TSPDI_ALMBSA[1--12] Payload Defect Indicator Alarm per STS-1 Bytestream B RXT_TSPDI_ALMBSB[1--12] Payload Defect Indicator Alarm per STS-1 Bytestream C RXT_TSPDI_ALMBSC[1--12] Payload Defect Indicator Alarm per STS-1 Bytestream D RXT_TSPDI_ALMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Payload Defect Indicator Alarm Binning RXT_PDI_ALMBNBS[A--D] RXT_RDI_ALMDBNBSR RXT_TSRDI_ALMDBSRA RXT_TSRDI_ALMDBSRB RXT_TSRDI_ALMDBSRC RXT_TSRDI_ALMDBSRD -- Remote Defect Indicator Alarm Delta Binning RXT_RDI_ALMDBNBS[A--D] Remote Defect Indicator Alarm Delta per STS-1 Bytestream A RXT_TSRDI_ALMDBSA[1--12] Remote Defect Indicator Alarm Delta per STS-1 Bytestream B RXT_TSRDI_ALMDBSB[1--12] Remote Defect Indicator Alarm Delta per STS-1 Bytestream C RXT_TSRDI_ALMDBSC[1--12] Remote Defect Indicator Alarm Delta per STS-1 Bytestream D RXT_TSRDI_ALMDBSD[1--12] RXT_PLM_ALMDBNBSR RXT_TSPLM_ALMDBSRA RXT_TSPLM_ALMDBSRB RXT_TSPLM_ALMDBSRC RXT_TSPLM_ALMDBSRD -- Payload Label Mismatch Alarm Delta Binning RXT_PLM_ALMDBNBS[A--D] Payload Label Mismatch Alarm Delta per STS-1 Bytestream A RXT_TSPLM_ALMDBSA[1--12] Payload Label Mismatch Alarm Delta per STS-1 Bytestream B RXT_TSPLM_ALMDBSB[1--12] Payload Label Mismatch Alarm Delta per STS-1 Bytestream C RXT_TSPLM_ALMDBSC[1--12] Payload Label Mismatch Alarm Delta per STS-1 Bytestream D RXT_TSPLM_ALMDBSD[1--12] Agere Systems Inc. 463 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8131 0x8132 0x8133 0x8134 0x8135 0x8136 -- 0x8140 0x8141 0x8142 0x8143 0x8144 0x8145 0x8146 -- 0x8150 0x8151 0x8152 0x8153 0x8154 0x8155 0x8156 -- 0x815F Symbol RXT_UNEQR_ALMDBNBSR RXT_TSUNEQR_ALMDBSRA RXT_TSUNEQR_ALMDBSRB RXT_TSUNEQR_ALMDBSRC RXT_TSUNEQR_ALMDBSRD -- Unequipped Received Alarm Delta per STS-1 Bytestream A RXT_TSUNEQR_ALMDBSA[1--12] Unequipped Received Alarm Delta per STS-1 Bytestream B RXT_TSUNEQR_ALMDBSB[1--12] Unequipped Received Alarm Delta per STS-1 Bytestream C RXT_TSUNEQR_ALMDBSC[1--12] Unequipped Received Alarm Delta per STS-1 Bytestream D RXT_TSUNEQR_ALMDBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unequipped Received Alarm Delta Binning RXT_UNEQR_ALMDBNBS[A--D] RXT_AIS_ALMDBNBSR RXT_TSAIS_ALMDBSRA RXT_TSAIS_ALMDBSRB RXT_TSAIS_ALMDBSRC RXT_TSAIS_ALMDBSRD -- Alarm Indicator Signal Alarm Delta per STS-1 Bytestream A RXT_TSAIS_ALMDBSA[1--12] Alarm Indicator Signal Alarm Delta per STS-1 Bytestream B RXT_TSAIS_ALMDBSB[1--12] Alarm Indicator Signal Alarm Delta per STS-1 Bytestream C RXT_TSAIS_ALMDBSC[1--12] Alarm Indicator Signal Alarm Delta per STS-1 Bytestream D RXT_TSAIS_ALMDBSD[1--12] Alarm Indicator Signal Alarm Delta Binning RXT_AIS_ALMDBNBS[A--D] RXT_LOP_ALMDBNBSR RXT_TSLOP_ALMDBSRA RXT_TSLOP_ALMDBSRB RXT_TSLOP_ALMDBSRC RXT_TSLOP_ALMDBSRD -- Loss of Pointer Alarm Delta per STS-1 Bytestream A RXT_TSLOP_ALMDBSA[1--12] Loss of Pointer Alarm Delta per STS-1 Bytestream B RXT_TSLOP_ALMDBSB[1--12] Loss of Pointer Alarm Delta per STS-1 Bytestream C RXT_TSLOP_ALMDBSC[1--12] Loss of Pointer Alarm Delta per STS-1 Bytestream D RXT_TSLOP_ALMDBSD[1--12] Loss of Pointer Alarm Delta Binning RXT_LOP_ALMDBNBS[A--D] 464 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8160 0x8161 -- 0x8170 0x8171 0x8172 0x8173 0x8174 0x8175 0x8176 -- 0x820E Symbol RXT_PTRACCMPIR -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_J1BF ACCMPI RXT_PDI_ALMDBNBSR RXT_TSPDI_ALMDBSRA RXT_TSPDI_ALMDBSRB RXT_TSPDI_ALMDBSRC RXT_TSPDI_ALMDBSRD -- PDI Alarm Delta per STS-1 Bytestream A RXT_TSPDI_ALMDBSA[1--12] PDI Alarm Delta per STS-1 Bytestream B RXT_TSPDI_ALMDBSB[1--12] PDI Alarm Delta per STS-1 Bytestream C RXT_TSPDI_ALMDBSC[1--12] PDI Alarm Delta per STS-1 Bytestream D RXT_TSPDI_ALMDBSD[1--12] PDI Alarm Delta Binning RXT_PDI_ALMDBNBS[A--D] Agere Systems Inc. 465 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x820F Symbol RXT_POH_ALMBNMR1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Masks RXT_PDI_ RXT_PDI_ RXT_ ALMALMBNM J1ACCMP DBNM _ALMBNM RXT_RDI_ ALMDBNM RXT_PLM RXT_UNE RXT_AIS_ _ALMDBN QR_ALMD ALMM BNM DBNM RXT_LOP RXT_J1M RXT_J1VL _ALMDBN M_ALMBN D_ALMBN M M M RXT_USC NCT_ALM BNM RXT_CNC TMM_ALM BNM RXT_SF_ ALMBNM RXT_RDI_ RXT_PLM RXT_UNE ALMBNM _ALMBNM QR_ALMB NM RXT_AIS_ RXT_LOP ALMBNM _ALMBNM Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x8210 RXT_POH_ALMBNMR2 0x8211 -- 0x8220 0x8221 0x8222 0x8223 0x8224 0x8225 0x8226 -- 0x8230 0x8231 0x8232 0x8233 0x8234 0x8235 0x8236 -- 0x8240 -- RXT_SF_ALMBNMBSR RXT_TSSF_ALMMBSRA RXT_TSSF_ALMMBSRB RXT_TSSF_ALMMBSRC RXT_TSSF_ALMMBSRD -- Signal Fail Alarm Mask per STS-1 Bytestream A RXT_TSSF_ALMMBSA[1--12] Signal Fail Alarm Mask per STS-1 Bytestream B RXT_TSSF_ALMMBSB[1--12] Signal Fail Alarm Mask per STS-1 Bytestream C RXT_TSSF_ALMMBSC[1--12] Signal FAil Alarm Mask per STS-1 Bytestream D RXT_TSSF_ALMMBSD[1--12] Signal Fail Alarm Binning Mask RXT_SF_ALMBNMBS[A--D] RXT_RDI_ALMBNMBSR RXT_TSRDI_ALMMBSRA RXT_TSRDI_ALMMBSRB RXT_TSRDI_ALMMBSRC RXT_TSRDI_ALMMBSRD -- Remote Defect Indicator Alarm Binning Mask RXT_RDI_ALMBNMBS[A--D] Remote Defect Indicator Alarm Mask per STS-1 Bytestream A RXT_TSRDI_ALMMBSA[1--12] Remote Defect Indicator Alarm Mask per STS-1 Bytestream B RXT_TSRDI_ALMMBSB[1--12] Remote Defect Indicator Alarm Mask per STS-1 Bytestream C RXT_TSRDI_ALMMBSC[1--12] Remote Defect Indicator Alarm Mask per STS-1 Bytestream D RXT_TSRDI_ALMMBSD[1--12] 466 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8241 0x8242 0x8243 0x8244 0x8245 0x8246 -- 0x8250 0x8251 0x8252 0x8253 0x8254 0x8255 0x8256 -- 0x8260 0x8261 0x8262 0x8263 0x8264 0x8265 0x8266 -- 0x8270 Symbol RXT_PLM_ALMBNMBSR RXT_TSPLM_ALMMBSRA RXT_TSPLM_ALMMBSRB RXT_TSPLM_ALMMBSRC RXT_TSPLM_ALMMBSRD -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Payload Label Mismatch Alarm Binning Mask RXT_PLM_ALMBNMBS[A--D] Payload Label Mismatch Alarm Mask per STS-1 Bytestream A RXT_TSPLM_ALMMBSA[1--12] Payload Label Mismatch Alarm Mask per STS-1 Bytestream B RXT_TSPLM_ALMMBSB[1--12] Payload Label Mismatch Alarm Mask per STS-1 Bytestream C RXT_TSPLM_ALMMBSC[1--12] Payload Label Mismatch Alarm Mask per STS-1 Bytestream D RXT_TSPLM_ALMMBSD[1--12] RXT_UNEQR_ALMBNMBSR RXT_TSUNEQR_ALMMBSRA RXT_TSUNEQR_ALMMBSB RXT_TSUNEQR_ALMMBSC RXT_TSUNEQR_ALMMBSD -- Unequipped Received Alarm Mask per STS-1 Bytestream A RXT_TSUNEQR_ALMMBSA[1--12] Unequipped Received Alarm Mask per STS-1 Bytestream B RXT_TSUNEQR_ALMMBSB[1--12] Unequipped Received Alarm Mask per STS-1 Bytestream C RXT_TSUNEQR_ALMMBSC[1--12] Unequipped Received Alarm Mask per STS-1 Bytestream D RXT_TSUNEQR_ALMMBSD[1--12] Unequipped Received Alarm Binning Mask RXT_UNEQR_ALMBNMBS[A--D] RXT_AIS_ALMBNMBSR RXT_TSAIS_ALMMBSRA RXT_TSAIS_ALMMBSRB RXT_TSAIS_ALMMBSRC RXT_TSAIS_ALMMBSRD -- Alarm Indicator Signal Alarm Mask per STS-1 Bytestream A RXT_TSAIS_ALMMBSA[1--12] Alarm Indicator Signal Alarm Mask per STS-1 Bytestream B RXT_TSAIS_ALMMBSB[1--12] Alarm Indicator Signal Alarm Mask per STS-1 Bytestream C RXT_TSAIS_ALMMBSC[1--12] Alarm Indicator Signal Alarm Mask per STS-1 Bytestream D RXT_TSAIS_ALMMBSD[1--12] Alarm Indicator Signal Alarm Binning Mask RXT_AIS_ALMBNMBS[A--D] Agere Systems Inc. 467 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8271 0x8272 0x8273 0x8274 0x8275 0x8276 0x8277 0x8278 0x8279 0x827A 0x827B 0x827C 0x827D 0x827E -- 0x8280 0x8281 0x8282 0x8283 0x8284 0x8285 0x8286 -- 0x8290 Symbol RXT_LOP_ALMBNMBSR RXT_TSLOP_ALMMBSRA RXT_TSLOP_ALMMBSRB RXT_TSLOP_ALMMBSRC RXT_TSLOP_ALMMBSRD -- RXT_CNCTMM_ALMMBSR -- RXT_USCNCTM_ALMMBSR -- RXT_J1NVLDMSG_ALMMBSR -- RXT_J1MSGMM_ALMMBSR -- J1 Message Mismatch Alarm Mask RXT_J1MSGMM_ALMMBS[A--D] J1 New Validated Message Alarm Mask RXT_J1NVLDMSG_ALMMBS[A--D] Unsupported Concatenation Map Alarm Mask RXT_USCNCTM_ALMMBS[A--D] Concatenation Map Mismatch Alarm Mask RXT_CNCTMM_ALMMBS[A--D] Loss of Pointer Alarm Mask per STS-1 Bytestream A RXT_TSLOP_ALMMBSA[1--12] Loss of Pointer Alarm Mask per STS-1 Bytestream B RXT_TSLOP_ALMMBSB[1--12] Loss of Pointer Alarm Mask per STS-1 Bytestream C RXT_TSLOP_ALMMBSC[1--12] Loss of Pointer Alarm Mask per STS-1 Bytestream D RXT_TSLOP_ALMMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Loss of Pointer Alarm Binning Mask RXT_LOP_ALMBNMBS[A--D] RXT_PDI_ALMBNMBSR RXT_TSPDI_ALMMBSRA RXT_TSPDI_ALMMBSRB RXT_TSPDI_ALMMBSRC RXT_TSPDI_ALMMBSRD -- Payload Defect Indicator Alarm Binning Mask RXT_PDI_ALMBNMBS[A--D] Payload Defect Indicator Alarm Mask per STS-1 Bytestream A RXT_TSPDI_ALMMBSA[1--12] Payload Defect Indicator Alarm Mask per STS-1 Bytestream B RXT_TSPDI_ALMMBSB[1--12] Payload Defect Indicator Alarm Mask per STS-1 Bytestream C RXT_TSPDI_ALMMBSC[1--12] Payload Defect Indicator Alarm Mask per STS-1 Bytestream D RXT_TSPDI_ALMMBSD[1--12] 468 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8291 0x8292 0x8293 0x8294 0x8295 0x8296 -- 0x82A0 0x82A1 0x82A2 0x82A3 0x82A4 0x82A5 0x82A6 --0x82B 0x82B1 0x82B2 0x82B3 0x82B4 0x82B5 0x82B6 -- 0x82C0 Symbol RXT_RDI_ALMDBNMBSR RXT_TSRDI_ALMDMBSRA RXT_TSRDI_ALMDMBSRB RXT_TSRDI_ALMDMBSRC RXT_TSRDI_ALMDMBSRD -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remote Defect Indicator Alarm Delta Binning Mask RXT_RDI_ALMBNDMBS[A--D] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream A RXT_TSRDI_ALMDMBSA[1--12] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream B RXT_TSRDI_ALMDMBSB[1--12] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream C RXT_TSRDI_ALMDMBSC[1--12] Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream D RXT_TSRDI_ALMDMBSD[1--12] RXT_PLM_ALMDBNMBSR RXT_TSPLM_ALMDMBSRA RXT_TSPLM_ALMDMBSRB RXT_TSPLM_ALMDMBSRC RXT_TSPLM_ALMDMBSRD -- RXT_UNEQR_ALMDBNMBSR RXT_TSUNEQR_ALMDMBSRA RXT_TSUNEQR_ALMDMBSRB RXT_TSUNEQR_ALMDMBSRC RXT_TSUNEQR_ALMDMBSRD -- Payload Label Mismatch Alarm Delta Binning Mask RXT_PLM_ALMDBNMBS[A--D] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream A RXT_TSPLM_ALMDMBSA[1--12] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream B RXT_TSPLM_ALMDMBSB[1--12] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream C RXT_TSPLM_ALMDMBSC[1--12] Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream D RXT_TSPLM_ALMDMBSD[1--12] Unequipped Received Alarm Delta Binning Mask RXT_UNEQR_ALMDBNMBS[A--D] Unequipped Received Alarm Delta Mask per STS-1 Bytestream A RXT_TSUNEQR_ALMDMBSA[1--12] Unequipped Received Alarm Delta Mask per STS-1 Bytestream B RXT_TSUNEQR_ALMDMBSB[1--12] Unequipped Received Alarm Delta Mask per STS-1 Bytestream C RXT_TSUNEQR_ALMDMBSC[1--12] Unequipped Received Alarm Delta Mask per STS-1 Bytestream D RXT_TSUNEQR_ALMDMBSD[1--12] Agere Systems Inc. 469 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x82C1 0x82C2 0x82C3 0x82C4 0x82C5 0x82C6 -- 0x82D0 0x82D1 0x82D2 0x82D3 0x82D4 0x82D5 0x82D6 -- 0x82DF 0x82E0 0x82E1 -- 0x82E8 Symbol RXT_AIS_ALMDBNMBSR RXT_TSAIS_ALMDMBSRA RXT_TSAIS_ALMDMBSRB RXT_TSAIS_ALMDMBSRC RXT_TSAIS_ALMDMBSRD -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Alarm Indicator Signal Alarm Delta Binning Mask RXT_AIS_ALMDBNMBS[A--D] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream A RXT_TSAIS_ALMDMBSA[1--12] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream B RXT_TSAIS_ALMDMBSB[1--12] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream C RXT_TSAIS_ALMDMBSC[1--12] Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream D RXT_TSAIS_ALMDMBSD[1--12] RXT_LOP_ALMDBNMBSR RXT_TSLOP_ALMDMBSRA RXT_TSLOP_ALMDMBSRB RXT_TSLOP_ALMDMBSRC RXT_TSLOP_ALMDMBSRD -- Loss of Pointer Alarm Delta Mask per STS-1 Bytestream A RXT_TSLOP_ALMDMBSA[1--12] Loss of Pointer Alarm Delta Mask per STS-1 Bytestream B RXT_TSLOP_ALMDMBSB[1--12] Loss of Pointer Alarm Delta Mask per STS-1 Bytestream C RXT_TSLOP_ALMDMBSC[1--12] Loss of Pointer Alarm Delta Mask per STS-1 Bytestream D RXT_TSLOP_ALMDMBSD[1--12] Loss of Pointer Alarm Delta Binning Mask RXT_LOP_ALMDBNMBS[A--D] RXT_PTRACCMPIR -- RXT_J1BFACCMPIM 470 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x82E9 0x82EA 0x82EB 0x82EC 0x82ED 0x82EE -- 0x82FF Symbol RXT_PDI_ALMDBNMBSR RXT_TSPDI_ALMDMBSRA RXT_TSPDI_ALMDMBSRB RXT_TSPDI_ALMDMBSRC RXT_TSPDI_ALMDMBSRD -- PDI Alarm Delta Mask per STS-1 Bytestream A RXT_TSPDI_ALMDMBSA[1--12] PDI Alarm Delta Mask per STS-1 Bytestream B RXT_TSPDI_ALMDMBSB[1--12] PDI Alarm Delta Mask per STS-1 Bytestream C RXT_TSPDI_ALMDMBSC[1--12] PDI Alarm Delta Mask per STS-1 Bytestream D RXT_TSPDI_ALMDMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDI Alarm Delta Binning Mask RXT_PDI_ALMDBNMBS[A--D] Agere Systems Inc. 471 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr -- 0x8300 -- 0x831F 0x8330 0x8331 0x8332 0x8333 0x8334 -- 0x8337 0x8338 0x8339 0x833A -- 0x833B 0x833C 0x833D 0x833E 0x833F 0x8340 -- 0x837F Symbol -- RXT_PTRBFR[1--32] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Path Trace J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer RXT_J1BYTE[1, 3, 5, . . . , 63][7:0] J1 Byte 0, 2, 4, . . . , 62 Path Trace Buffer RXT_J1BYTE[0, 2, 4, . . . , 62][7:0] Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_PTRACCTLR1 RXT_PTRACCTLR2 RXT_PTRACCTLR3 RXT_PTRACBGR -- RXT_J1TS1_CHSEL[1:0] RXT_J1BF _MSGSEL RXT_J1BF _ACTYP RXT_J1_A CBG RXT_STS12PTRCTLR1 RXT_STS12PTRCTLR2 -- J1 Message Mode Select RXT_J1MSG_MSEL[A--D] J1 Message Type Select RXT_J1MSG_TYPSEL[A--D] RXT_STS12PTRCTLR3 RXT_STS12PTRCTLR4 RXT_STS12PTRCTLR5 RXT_STS12PTRCTLR6 -- Time Slots 1--12 Select for J1 Accumulation RXT_TSSEL_J1A[3:0] RXT_TSSEL_J1B[3:0] RXT_TSSEL_J1C[3:0] RXT_TSSEL_J1D[3:0] 472 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8380 -- 0x8381 0x8382 0x8383 0x8384 0x8385 0x8386 -- 0x8389 0x838A 0x838B 0x838C 0x838D 0x838E -- 0x8391 0x8392 0x8393 0x8394 0x8395 0x8396 -- 0x8399 Symbol -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Persistency Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_TSRDI_ALMPSBSRA RXT_TSRDI_ALMPSBSRB RXT_TSRDI_ALMPSBSRC RXT_TSRDI_ALMPSBSRD -- RDI Alarm Persistency per STS-1 Bytestream A RXT_TSRDI_ALMPSBSA[1--12] RDI Alarm Persistency per STS-1 Bytestream B RXT_TSRDI_ALMPSBSB[1--12] RDI Alarm Persistency per STS-1 Bytestream C RXT_TSRDI_ALMPSBSC[1--12] RDI Alarm Persistency per STS-1 Bytestream D RXT_TSRDI_ALMPSBSD[1--12] RXT_TSPLM_ALMPSBSRA RXT_TSPLM_ALMPSBSRB RXT_TSPLM_ALMPSBSRC RXT_TSPLM_ALMPSBSRD -- Payload Label Mismatch Alarm Persistency per STS-1 Bytestream A RXT_TSPLM_ALMPSBSA[1--12] Payload Label Mismatch Alarm Persistency per STS-1 Bytestream B RXT_TSPLM_ALMPSBSB[1--12] Payload Label Mismatch Alarm Persistency per STS-1 Bytestream C RXT_TSPLM_ALMPSBSC[1--12] Payload Label Mismatch Alarm Persistency per STS-1 Bytestream D RXT_TSPLM_ALMPSBSD[1--12] RXT_TSPUNEQ_ALMPSBSRA RXT_TSPUNEQ_ALMPSBSRB RXT_TSPUNEQ_ALMPSBSR C RXT_TSPUNEQ_ALMPSBSR D -- Path Unequipped Alarm Persistency per STS-1 Bytestream A RXT_TSPUNEQ_ALMPSBSA[1--12] Path Unequipped Alarm Persistency per STS-1 Bytestream B RXT_TSPUNEQ_ALMPSBSB[1--12] Path Unequipped Alarm Persistency per STS-1 Bytestream C RXT_TSPUNEQ_ALMPSBSC[1--12] Path Unequipped Alarm Persistency per STS-1 Bytestream D RXT_TSPUNEQ_ALMPSBSD[1--12] Agere Systems Inc. 473 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x839A 0x839B 0x839C 0x839D 0x839E -- 0x83A1 0x83A2 0x83A3 0x83A4 0x83A5 0x83A6 -- 0x83A9 0x83AA 0x83AB 0x83AC 0x83AD 0x83AE -- 0x83BF Symbol RXT_TSAIS_ALMPSBSRA RXT_TSAIS_ALMPSBSRB RXT_TSAIS_ALMPSBSRC RXT_TSAIS_ALMPSBSRD -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AIS Alarm Persistency per STS-1 Bytestream A RXT_TSAIS_ALMPSBSA[1--12] AIS Alarm Persistency per STS-1 Bytestream B RXT_TSAIS_ALMPSBSB[1--12] AIS Alarm Persistency per STS-1 Bytestream C RXT_TSAIS_ALMPSBSC[1--12] AIS Alarm Persistency per STS-1 Bytestream D RXT_TSAIS_ALMPSBSD[1--12] RXT_TSLOP_ALMPSBSRA RXT_TSLOP_ALMPSBSRB RXT_TSLOP_ALMPSBSRC RXT_TSLOP_ALMPSBSRD -- LOP Alarm Persistency per STS-1 Bytestream A RXT_TSLOP_ALMPSBSA[1--12] LOP Alarm Persistency per STS-1 Bytestream B RXT_TSLOP_ALMPSBSB[1--12] LOP Alarm Persistency per STS-1 Bytestream C RXT_TSLOP_ALMPSBSC[1--12] LOP Alarm Persistency per STS-1 Bytestream D RXT_TSLOP_ALMPSBSD[1--12] RXT_TSPDI_ALMPSBSRA RXT_TSPDI_ALMPSBSRB RXT_TSPDI_ALMPSBSRC RXT_TSPDI_ALMPSBSRD -- PDI Alarm Persistency per STS-1 Bytestream A RXT_TSPDI_ALMPSBSA[1--12] PDI Alarm Persistency per STS-1 Bytestream B RXT_TSPDI_ALMPSBSB[1--12] PDI Alarm Persistency per STS-1 Bytestream C RXT_TSPDI_ALMPSBSC[1--12] PDI Alarm Persistency per STS-1 Bytestream D RXT_TSPDI_ALMPSBSD[1--12] 474 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x83C0 -- 0x83C1 0x83C2 0x83C3 0x83C4 0x83C5 0x83C6 -- 0x83C9 0x83CA 0x83CB 0x83CC 0x83CD 0x83CE -- 0x83D1 0x83D2 0x83D3 0x83D4 0x83D5 0x83D6 -- 0x83D9 Symbol -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 State Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_TSRDI_STBSRA RXT_TSRDI_STBSRB RXT_TSRDI_STBSRC RXT_TSRDI_STBSRD -- RDI State per STS-1 Bytestream A RXT_TSRDI_STBSA[1--12] RDI State per STS-1 Bytestream B RXT_TSRDI_STBSB[1--12] RDI State per STS-1 Bytestream C RXT_TSRDI_STBSC[1--12] RDI State per STS-1 Bytestream D RXT_TSRDI_STBSD[1--12] RXT_TSPLM_STBSRA RXT_TSPLM_STBSRB RXT_TSPLM_STBSRC RXT_TSPLM_STBSRD -- Payload Label Mismatch State per STS-1 Bytestream A RXT_TSPLM_STBSA[1--12] Payload Label Mismatch State per STS-1 Bytestream B RXT_TSPLM_STBSB[1--12] Payload Label Mismatch State per STS-1 Bytestream C RXT_TSPLM_STBSC[1--12] Payload Label Mismatch State per STS-1 Bytestream D RXT_TSPLM_STBSD[1--12] RXT_TSPUNEQ_STBSRA RXT_TSPUNEQ_STBSRB RXT_TSPUNEQ_STBSRC RXT_TSPUNEQ_STBSRD -- Path Unequipped State per STS-1 Bytestream A RXT_TSPUNEQ_STBSA[1--12] Path Unequipped State per STS-1 Bytestream B RXT_TSPUNEQ_STBSB[1--12] Path Unequipped State per STS-1 Bytestream C RXT_TSPUNEQ_STBSC[1--12] Path Unequipped State per STS-1 Bytestream D RXT_TSPUNEQ_STBSD[1--12] Agere Systems Inc. 475 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x83DA 0x83DB 0x83DC 0x83DD 0x83DE -- 0x83E1 0x83E2 0x83E3 0x83E4 0x83E5 0x83E6 -- 0x83E9 0x83EA 0x83EB 0x83EC 0x83ED 0x83EE -- 0x83FF Symbol RXT_TSAIS_STBSRA RXT_TSAIS_STBSRB RXT_TSAIS_STBSRC RXT_TSAIS_STBSRD -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AIS State per STS-1 Bytestream A RXT_TSAIS_STBSA[1--12] AIS State per STS-1 Bytestream B RXT_TSAIS_STBSB[1--12] AIS State per STS-1 Bytestream C RXT_TSAIS_STBSC[1--12] AIS State per STS-1 Bytestream D RXT_TSAIS_STBSD[1--12] RXT_TSLOP_STBSRA RXT_TSLOP_STBSRB RXT_TSLOP_STBSRC RXT_TSLOP_STBSRD -- LOP State per STS-1 Bytestream A RXT_TSLOP_STBSA[1--12] LOP State per STS-1 Bytestream B RXT_TSLOP_STBSB[1--12] LOP State per STS-1 Bytestream C RXT_TSLOP_STBSC[1--12] LOP State per STS-1 Bytestream D RXT_TSLOP_STBSD[1--12] RXT_TSPDI_STBSRA RXT_TSPDI_STBSRB RXT_TSPDI_STBSRC RXT_TSPDI_STBSRD -- PDI State per STS-1 Bytestream A RXT_TSPDI_STBSA[1--12] PDI State per STS-1 Bytestream B RXT_TSPDI_STBSB[1--12] PDI State per STS-1 Bytestream C RXT_TSPDI_STBSC[1--12] LOP State per STS-1 Bytestream D RXT_TSPDI_STBSD[1--12] 476 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8400 0x8401 0x8402 -- 0x840F 0x8410 0x8411 0x8412 0x8413 0x8414 0x8415 0x8416 0x8417 0x8418 0x8419 0x841A 0x841B 0x841C 0x841D 0x841E 0x841F 0x8420 0x8421 -- 0x842F 0x8430 0x8431 -- 0x843F 0x8440 0x8441 -- 0x844F 0x8450 0x8451 -- 0x8501 Symbol RXT_SFWSZ_SELR1 RXT_SFWSZ_SELR2 -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Signal Fail RXT_SFWSZ_SELSET[0--7][1:0] RXT_SFWSZ_SELCLR[0--7][1:0] Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_SFDR0 RXT_SFDR1 RXT_SFDR2 RXT_SFDR3 RXT_SFDR4 RXT_SFDR5 RXT_SFDR6 RXT_SFDR7 RXT_SFCLRR0 RXT_SFCLRR1 RXT_SFCLRR2 RXT_SFCLRR3 RXT_SFCLRR4 RXT_SFCLRR5 RXT_SFCLRR6 RXT_SFCLRR7 RXT_SFWSZR0 -- RXT_SFCLR2[13:0] RXT_SFCLR3[13:0] RXT_SFCLR4[13:0] RXT_SFCLR5[13:0] RXT_SFCLR6[13:0] RXT_SFCLR7[13:0] RXT_SFWSZ0[15:0] RXT_SFD2[13:0] RXT_SFD3[13:0] RXT_SFD4[13:0] RXT_SFD5[13:0] RXT_SFD6[13:0] RXT_SFD7[13:0] RXT_SFD0[8:0] RXT_SFD1[8:0] RXT_SFCLR0[8:0] RXT_SFCLR1[8:0] RXT_SFWSZR1 -- RXT_SFWSZ1[15:0] RXT_SFWSZR2 -- RXT_SFWSZ2[15:0] RXT_SFWSZR3 -- RXT_SFWSZ3[15:0] Agere Systems Inc. 477 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8502 0x8503 0x8504 0x8505 0x8506 0x8507 0x8508 0x8509 0x850A 0x850B -- 0x8511 0x8512 0x8513 0x8514 0x8515 0x8516 -- 0x8541 Symbol RXT_ECNCTM_TSBSRA RXT_ECNCTM_TSBSRB RXT_ECNCTM_TSBSRC RXT_ECNCTM_TSBSRD -- RXT_CNCTCPREN_TSBSRA RXT_CNCTCPREN_TSBSRB RXT_CNCTCPREN_TSBSRC RXT_CNCTCPREN_TSBSRD -- Software Concatenation Compare Enable Bytestream A RXT_CNCTCPREN_TSBSA[1--12] Software Concatenation Compare Enable Bytestream B RXT_CNCTCPREN_TSBSB[1--12] Software Concatenation Compare Enable Bytestream C RXT_CNCTCPREN_TSBSC[1--12] Software Concatenation Compare Enable Bytestream D RXT_CNCTCPREN_TSBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Concatenation Expected Concatenation Map Bytestream A RXT_ECNCT_STTSBSA[1--12] Expected Concatenation Map Bytestream B RXT_ECNCT_STTSBSB[1--12] Expected Concatenation Map Bytestream C RXT_ECNCT_STTSBSC[1--12] Expected Concatenation Map Bytestream D RXT_ECNCT_STTSBSD[1--12] RXT_RCNCTM_TSBSRA RXT_RCNCTM_TSBSRB RXT_RCNCTM_TSBSRC RXT_RCNCTM_TSBSRD -- Received Concatenation Map Bytestream A RXT_RCNCT_STTSBSA[1--12] Received Concatenation Map Bytestream B RXT_RCNCT_STTSBSB[1--12] Received Concatenation Map Bytestream C RXT_RCNCT_STTSBSC[1--12] Received Concatenation Map Bytestream D RXT_RCNCT_STTSBSD[1--12] 478 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8542 0x8543 0x8544 0x8545 0x8546 0x8547 0x8548 0x8549 0x854A 0x854B 0x854C 0x854D 0x854E 0x854F 0x8550 0x8551 0x8552 0x8553 0x8554 0x8555 -- 0x857F Symbol RXT_SWAIS_ISRTRA RXT_SWAIS_ISRTRB RXT_SWAIS_ISRTRC RXT_SWAIS_ISRTRD -- RXT_AISONUNEQ_PRA RXT_AISONUNEQ_PRB RXT_AISONUNEQ_PRC RXT_AISONUNEQ_PRD -- RXT_AISONPLM_PRA RXT_AISONPLM_PRB RXT_AISONPLM_PRC RXT_AISONPLM_PRD -- RXT_AISONTIM_PRA RXT_AISONTIM_PRB RXT_AISONTIM_PRC RXT_AISONTIM_PRD -- AIS Insert on TIM Control Bytestream A RXT_AISONTIM_PA[1--12] AIS Insert on TIM Control Bytestream B RXT_AISONTIM_PB[1--12] AIS Insert on TIM Control Bytestream C RXT_AISONTIM_PC[1--12] AIS Insert on TIM Control Bytestream D RXT_AISONTIM_PD[1--12] AIS Insert on PLM Control Bytestream A RXT_AISONPLM_PA[1--12] AIS Insert on PLM Control Bytestream B RXT_AISONPLM_PB{1--12] AIS Insert on PLM Control Bytestream C RXT_AISONPLM_PC[1--12] AIS Insert on PLM Control Bytestream D RXT_AISONPLM_PD[1--12] AIS Insert on UNEQ Control Bytestream A RXT_AISONUNEQ_PA[1--12] AIS Insert on UNEQ Control Bytestream B RXT_AISONUNEQ_PB[1--12] AIS Insert on UNEQ Control Bytestream C RXT_AISONUNEQ_PC[1--12] AIS Insert on UNEQ Control Bytestream D RXT_AISONUNEQ_PD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AIS Insert Control AIS Insert Bytestream A RXT_SWAIS_ISRTA[1--12] AIS Insert Bytestream B RXT_SWAIS_ISRTB[1--12] AIS Insert Bytestream C RXT_SWAIS_ISRTC[1--12] AIS Insert Bytestream D RXT_SWAIS_ISRTD[1--12] Agere Systems Inc. 479 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8580 0x8581 -- 0x858F 0x8590 0x8591 0x8592 0x8593 0x8594 -- 0x85A1 0x85A2 0x85A3 0x85A4 0x85A5 0x85A6 -- 0x85FF Symbol RXT_STS12_PINCDECR -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pointer Processor Control SONET/SDH Pointer Inc/Dec Rules RXT_PINCDEC[A--D] RXT_TS_INCDECBNRA RXT_TS_INCDEBNCRB RXT_TS_INCDECBNRC RXT_TS_INCDECBNRD -- STS-1 Inc/Dec Binning Select Bytestream A RXT_TS_INCDECBNA[3:0] STS-1 Inc/Dec Binning Select Bytestream B RXT_TS_INCDECBNB[3:0] STS-1 Inc/Dec Binning Select Bytestream C RXT_TS_INCDECBNC[3:0] STS-1 Inc/Dec Binning Select Bytestream D RXT_TS_INCDECBND[3:0] RXT_TSPDIVLD_CTLBSRA RXT_TSPDIVLD_CTLBSRB RXT_TSPDIVLD_CTLBSRC RXT_TSPDIVLD_CTLBSRD -- PDI Validate Control Bytestream A RXT_TSPDIVLD_CTLBSA[1--12] PDI Validate Control Bytestream B RXT_TSPDIVLD_CTLBSB[1--12] PDI Validate Control Bytestream C RXT_TSPDIVLD_CTLBSC[1--12] PDI Validate Control Bytestream D RXT_TSPDIVLD_CTLBSD[1--12] 480 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr -- 0x8600 -- 0x8617 0x8618 0x8619 0x861A 0x861B 0x861C -- 0x8681 Symbol -- RXT_EXPC2_PVSNR[1--24] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Provisioning Time Slots 1, 3, 5, . . . , 47 Expected C2 Bytes RXT_EXPC2[1, 3, 5, . . . , 47][7:0] Time Slots 2, 4, 6, . . . , 48 Expected C2 Bytes RXT_EXPCP[2, 4, 6, . . . , 48][7:0] Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_TSCBB_ERRBSRA RXT_TSCBB_ERRBSRB RXT_TSCBB_ERRBSRC RXT_TSCBB_ERRBSRD -- Count Bit/Block Errors Bytestream A RXT_TSCBB_ERRBSA[1--12] Count Bit/Block Errors Bytestream B RXT_TSCBB_ERRBSB[1--12] Count Bit/Block Errors Bytestream C RXT_TSCBB_ERRBSC[1--12] Count Bit/Block Errors Bytestream D RXT_TSCBB_ERRBSD[1--12] Agere Systems Inc. 481 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8682 -- 0x868F 0x8690 -- 0x86BF 0x86C0 -- 0x8701 0x8702 0x8703 0x8704 0x8705 0x8706 -- 0x8711 0x8712 0x8713 0x8714 0x8715 0x8716 -- 0x877F Symbol -- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Maintenance Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXT_TSMNTR[1--48] RXT_TSSF_TH[1--48][2:0] -- Interpreter Inc/Dec (PM) RXT_PI_LSECINCRA RXT_PI_LSECINCRB RXT_PI_LSECINCRC RXT_PI_LSECINCRD -- RXT_PI_LSECINCA[10:0] RXT_PI_LSECINCB[10:0] RXT_PI_LSECINCC[10:0] RXT_PI_LSECINCD[10:0] RXT_PI_LSECDECRA RXT_PI_LSECDECRB RXT_PI_LSECDECRC RXT_PI_LSECDECRD -- RXT_PI_LSECDECA[10:0] RXT_PI_LSECDECB[10:0] RXT_PI_LSECDECC[10:0] RXT_PI_LSECDECD[10:0] 482 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x8780 Symbol RXT_POH_ALMPMR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 RXT_1BR DI_DPM Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RXT_AIS_ ALMPM Bit 0 RXT_LOP _ALMPM Performance Monitoring RXT_ERDI RXT_ERDI RXT_ERDI RXT_UNE _PDPM _CDPM _SDPM QR_ALMP M 0x8781 0x8782 0x8783 0x8784 0x8785 0x8786 -- 0x8790 0x8791 0x8792 0x8793 0x8794 0x8795 0x8796 -- 0x87A0 0x87A1 0x87A2 0x87A3 0x87A4 0x87A5 0x87A6 -- 0x87B0 RXT_1BRDI_DPMBSR RXT_TS1BRDI_DPMBSRA RXT_TS1BRDI_DPMBSRB RXT_TS1BRDI_DPMBSRC RXT_TS1BRDI_DPMBSRD -- One-Bit RDI Alarm PM per STS-1 Bytestream A RXT_TS1BRDI_DPMBSA[1--12] One-Bit RDI Alarm PM per STS-1 Bytestream B RXT_TS1BRDI_DPMBSB[1--12] One-Bit RDI Alarm PM per STS-1 Bytestream C RXT_TS1BRDI_DPMBSC[1--12] One-Bit RDI Alarm PM per STS-1 Bytestream D RXT_TS1BRDI_DPMBSD[1--12] One-Bit RDI Alarm PM RXT_1BRDI_DPMBS[A--D] RXT_ERDI_PDPMBSR RXT_ERDI_PDPMBSRA RXT_ERDI_PDPMBSRB RXT_ERDI_PDPMBSRC RXT_ERDI_PDPMBSRD -- ERDI Payload Alarm PM per STS-1 Bytestream A RXT_TSERDI_PDPMBSA[1--12] ERDI Payload Alarm PM per STS-1 Bytestream B RXT_TSERDI_PDPMBSB[1--12] ERDI Payload Alarm PM per STS-1 Bytestream C RXT_TSERDI_PDPMBSC[1--12] ERDI Payload Alarm PM per STS-1 Bytestream D RXT_TSERDI_PDPMBSD[1--12] ERDI Payload Alarm PM RXT_ERDI_PDPMBS[A--D] RXT_ERDI_CDPMBSR RXT_TSERDI_CDPMBSRA RXT_TSERDI_CDPMBSRB RXT_TSERDI_CDPMBSRC RXT_TSERDI_CDPMBSRD -- ERDI Connectivity Alarm PM per STS-1 Bytestream A RXT_TSERDI_CDPMBSA[1--12] ERDI Connectivity Alarm PM per STS-1 Bytestream B RXT_TSERDI_CDPMBSB[1--12] ERDI Connectivity Alarm PM per STS-1 Bytestream C RXT_TSERDI_CDPMBSC[1--12] ERDI Connectivity Alarm PM per STS-1 Bytestream D RXT_TSERDI_CDPMBSD[1--12] ERDI Connectivity Alarm PM RXT_ERDI_CDPMBS[A--D] Agere Systems Inc. 483 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x87B1 0x87B2 0x87B3 0x87B4 0x87B5 0x87B6 -- 0x87C0 0x87C1 0x87C2 0x87C3 0x87C4 0x87C5 0x87C6 -- 0x87D0 0x87D1 0x87D2 0x87D3 0x87D4 0x87D5 0x87D6 -- 0x87E0 Symbol RXT_ERDI_SDPMBSR RXT_TSERDI_SDPMBSRA RXT_TSERDI_SDPMBSRB RXT_TSERDI_SDPMBSRC RXT_TSERDI_SDPMBSRD -- ERDI Server Alarm PM per STS-1 Bytestream A RXT_TSERDI_SDPMBSA[1--12] ERDI Server Alarm PM per STS-1 Bytestream B RXT_TSERDI_SDPMBSB[1--12] ERDI Server Alarm PM per STS-1 Bytestream C RXT_TSERDI_SDPMBSC[1--12] ERDI Server Alarm PM per STS-1 Bytestream D RXT_TSERDI_SDPMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERDI Server Alarm PM RXT_ERDI_SDPMBS[A--D] RXT_UNEQR_PMBSR RXT_TSUNEQR_PMBSRA RXT_TSUNEQR_PMBSRB RXT_TSUNEQR_PMBSRC RXT_TSUNEQR_PMBSRD -- Unequipped Received Alarm PM per STS-1 Bytestream A RXT_TSUNEQR_PMBSA[1--12] Unequipped Received Alarm PM per STS-1 Bytestream B RXT_TSUNEQR_PMBSB[1--12] Unequipped Received Alarm PM per STS-1 Bytestream C RXT_TSUNEQR_PMBSC[1--12] Unequipped Received Alarm PM per STS-1 Bytestream D RXT_TSUNEQR_PMBSD[1--12] Unequipped Received Alarm PM RXT_UNEQR_PMBS[A--D] RXT_AIS_PMBSR RXT_TSAIS_PMBSRA RXT_TSAIS_PMBSRB RXT_TSAIS_PMBSRC RXT_TSAIS_PMBSRD -- Alarm Indicator Signal Alarm PM per STS-1 Bytestream A RXT_TSAIS_PMBSA[1--12] Alarm Indicator Signal Alarm PM per STS-1 Bytestream B RXT_TSAIS_PMBSB[1--12] Alarm Indicator Signal Alarm PM per STS-1 Bytestream C RXT_TSAIS_PMBSC[1--12] Alarm Indicator Signal Alarm PM per STS-1 Bytestream D RXT_TSAIS_PMBSD[1--12] Alarm Indicator Signal Alarm PM RXT_AIS_PMBS[A--D] 484 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface STS Receive Terminator (RXT) Block (continued) RXT Register Map (continued) Table 452. RXT Register Map (continued) Note: Shading denotes reserved bits. Addr 0x87E1 0x87E2 0x87E3 0x87E4 0x87E5 0x87E6 -- 0x87FF 0x8800 -- 0x882F 0x8830 -- 0x887F 0x8880 -- 0x88AF 0x88B0 -- 0x88FF 0x8900 -- 0x892F 0x8930 -- 0x8947 0x8948 -- 0x895F 0x8960 -- 0x8977 0x8968 -- 0x8FFF Symbol RXT_LOP_PMBSR RXT_TSLOP_PMBSRA RXT_TSLOP_PMBSRB RXT_TSLOP_PMBSRC RXT_TSLOP_PMBSRD -- Loss of Pointer Alarm PM per STS-1 Bytestream A RXT_TSLOP_PMBSA[1--12] Loss of Pointer Alarm PM per STS-1 Bytestream B RXT_TSLOP_PMBSB[1--12] Loss of Pointer Alarm PM per STS-1 Bytestream C RXT_TSLOP_PMBSC[1--12] Loss of Pointer Alarm PM per STS-1 Bytestream D RXT_TSLOP_PMBSD[1--12] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Loss of Pointer Alarm PM RXT_LOP_PMBS[A--D] RXT_LSECCVP_CPMR[1--48] Time Slots 1, 2, 3, 4, . . . , 48 CV Count PM RXT_LSECCVP_CPM[1--48][15:0] -- RXT_LSECREIP_ CPMR[1--48] -- Time Slots 1, 2, 3, 4, . . . , 48 REI Count PM RXT_LSECREIP_CPM[1--48][15:0] RDI, C2 Status RXT_TSRDIPR[1--48] Time Slot 1--Time Slot 48 Received RDI Code RXT_TS_RRDI[1--48][2:0] Time Slots 1, 3, 5, 7, . . . , 47 Received C2 Byte RXT_TSRC2[1, 3, 5, . . . , 47][7:0] Time Slots 2, 4, 6, 8, . . . , 48 Received C2 byte RXT_TSRC2[2, 4, 6, . . . , 48][7:0] RXT_TSC2R[1--24] -- PDI Status RXT_TSPDIR[1--24] Time Slots 1, 3, 5, 7, . . . , 47 Received PDI Byte RXT_TSRPDI[1, 3, 5, . . . , 47][7:0] Time Slots 2, 4, 6, 8, . . . , 48 Received PDI Byte RXT_TSRPDI[2, 4, 6, . . . , 48][7:0] -- Agere Systems Inc. 485 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block DS3 Functional Description DS3 Block Interface Diagram The DS3 block consists of three major subblocks: DS3 Rx, DS3 Tx, and microprocessor interface. The DS3 block interfaces with the pointer interpreter and SPE blocks on one side and the receive sequencer/data engine blocks on the other side as shown in Figure 55. DS3 BLOCK POINTER INTERPRETER (PTR) FEEDBACK DS3 RX FEEDBACK DS3 TX RECEIVE SEQUENCER (RXS) SPE MAPPER (SPE) MICRO I/F DATA ENGINE (DE) 5-8326(F)r.5 Figure 55. DS3 Block Interface Diagram DS3 Receive Subblock The DS3 Rx block is responsible for extracting the i bits from an STS-1 frame, performing DS3 framing, and extracting the d bits from the DS3 frame, and finally, extracting data (packets or ATM cells) from the d bits. The ATM cells could be either direct mapped, or PLCP mapped, and packets are direct mapped. Data arrives at the DS3 in the Rx direction grouped as four slices of 8 bits. The four slices are labeled A, B, C, and D as shown in Figure 56. DS3 is only supported in slices A and B. The DS3 block is designed to accommodate up to 24 channels, among the two slices. Thus, each slice could have up to 12 channels, and data for any given channel will always arrive at the same slice (that is, data for any one channel arriving on slice A, will never arrive on B, C, or D). Not all 16 channels need to be DS3 mapped. Any channels not DS3 mapped will be passed through the block untouched. Additionally, the delay through each slice will be the same, if the data is not DS3 mapped, so that data that is not DS3 mapped, belonging to a single channel, can be presented across the four slices at the same time, to the next block, and the data will be transmitted out of the DS3 block aligned in time. 486 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Functional Description (continued) 24 DS3/PLCP--12 PER SLICE A AND B A B FROM PT C D DS3 I BITS EXTR. DS3 I BITS EXTR. DS3 FRM DS3 FRM PLCP FRM PRBS MON PLCP FRM PRBS MON A B TO RXS C D SLICE C--DS3 NOT SUPPORTED SLICE D--DS3 NOT SUPPORTED SPE MAPPER (SPE DS3) DS3 INs PLCP INs FIFO FROM DE PRBS INSERT PT BLOCK 16 LOGICAL CHANNELS DS3 BLOCK 5-8715(F)r.1 Figure 56. DS3 Receive Subblock The data entering the DS3 block passes through a mode look-up block, which is responsible for determining, from the time slot, if the data for that channel is DS3 encoded. If data is DS3 encoded, then the mode look-up block is responsible for indicating if DS3 data is PLCP encoded or clear channel as indicated by the following register bits DS3_RDS3PLCP_[A--B][12--1][1:0] (Table 560, Table 561, Table 563, and Table 564): 00 = no mapping, 01 = illegal (no mapping), 10 = DS3 clear channel, 11 = DS3/PLCP mapped signal. The data is then passed through the DS3 I bits extract block, which is responsible for extracting the i bits from an STS-1 frame. The format of DS3 i-bit mapping into an STS-1 frame is shown in Table 678. Data for any channels not carrying DS3 traffic is sent through this block unmodified. In this block, path-level overhead bytes are ignored. The r(reserved) and o(overhead communications channel) bits are ignored. The s bit is treated as a stuff bit according to the majority vote of the c bits, as per GR253 R3-70 and GR253 R3-71 requirements. The DS3 I bits extract block receives a J1 marker along with the data. All internal counters are resynchronized to the J1 marker, on a per time-slot basis. After the i bits are extracted, they are passed to the DS3 framer 8 bits at a time. This implies that data must be packed in this and all blocks before being sent out for further processing. All reserved and fixed stuff bytes are marked as invalid data, register bits DS3_RDS3PLCP_[A--B][12--1][1:0]. Setting a time slot into the no mapping mode (00 or 01) resets all internal states for that time slot. Once the i bits are extracted from an STS-1 frame, they are passed to the DS3 framer block, which is responsible for performing framing onto the DS3 subframe alignment and multiframe alignment signals if the signal contains a DS3 frame. The format of a DS3 multiframe is shown in Figure 61. Agere Systems Inc. 487 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Functional Description (continued) DS3 Framing Algorithm Framing is done in two stages by first finding a bit position that matches the frame alignment pattern (F bits 1001), and then locating the multiframe alignment signal (M bits 010). In F frame is declared once no errors are detected in the F-bit sequence for 16 consecutive bits. After a matching F-bit sequence is found, in frame is declared (DS3_OOF_[A--B][12--1] = 0 (Table 532 and Table 546)) when correct M bits are received for three M frames (T1.231). The maximum average reframe time is 0.5 ms in the presence of a bit error rate of 10-3. Once in frame, the received frame bits are monitored for out-of-frame. Out-of-frame is declared (DS3_OOF_[A-- B][12--1] = 1) if too many errors are received in either the F bits (three errors in 16 bits if DS3_OOF_FMODE_[A-- B] = 0 (Table 560 and Table 563), or at least one F-bit error in each of four consecutive M subframes if DS3_OOF_FMODE_[A--B] = 1) or the M bits (at least one error in each of three consecutive M frames). For testing purposes, the user may also force the framer out-of-frame by setting the mapping bits. The traditional algorithm for declaring out-of-frame (three errors in 16 F bits) results in false out-of-frame approximately every 30 seconds when the received bit error rate is 10-3. By waiting for four consecutive M subframes with F-bit errors before declaring out-of-frame, the framer normally stays in frame for over an hour when the bit error rate is 10-3. After subframe and multiframe have been acquired, the DS3 channel is declared framed, and an alarm is raised. DS3 Loss-of-Frame The DS3_LOF_[A--B][12--1] bit (Table 533 and Table 547) is set if the associated DS3_OOF_[A--B][12--1] outof-frame bit is high continuously for 28 1 frame periods (approximately 3 ms). Once set, the LOF state bit is not cleared until the OOF state bit is continuously low for 28 1 frame periods. Register bits: DS3_LOF_[A--B][12--1], DS3_LOFD_[A--B][12--1] (Table 481 and Table 493), and DS3_LOFM_[A--B][12--1] (Table 507 and Table 519). Severely Errored Frame (SEF) The received DS3 frames are checked for severely errored frames (SEF). A SEF defect is the occurrence of three or more F-bit errors in 16 consecutive F bits and reported through register bits DS3_SEF_[A--B][12--1] (Table 534 and Table 548). A SEF defect is terminated when the signal is in-frame and there are less than three F-bit errors in 16 consecutive F bits. This error may cause the DS3 framer to transition to the out-of-frame state. Register bits: DS3_SEF_[A--B][12--1], DS3_SEFD_[A--B][1--12] (Table 482 and Table 494), and DS3_SEFM_[A--B][12--1] (Table 508 and Table 520). AIS Detection/Removal In each M-frame, the 4704 information bits are checked for the presence of the AIS (1010) pattern starting after each overhead bit. In order to detect this pattern in the presence of a high error rate, AIS (DS3_AISPAT_DET_[A-- B][12--1] (Table 535 and Table 549)) pattern detection is declared if fewer than five pattern errors are received in each of two consecutive frames. Once AIS is declared, it is not cleared until at least 16 pattern errors are received in each of two consecutive M-frames (T1.231). In addition to detection of the pattern, the DS3 signal must be inframe and P-bit errors are binned during AIS detection. Register bits: DS3_AISPAT_DET_[A--B][12--1], DS3_AISPAT_DETD_[A--B][12--1] (Table 483 and Table 495), and DS3_AISPAT_DETM[A--B][12--1] (Table 509 and Table 521). 488 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Functional Description (continued) Idle Detection/Removal In each M-frame, the 4704 information bits are checked for the presence of the idle (1100) pattern starting after each overhead bit. In order to detect this pattern in the presence of a high error rate, idle (DS3_IDLEPAT_DET_[A--B][12--1] (Table 536 and Table 550)) pattern detection is declared if fewer than five pattern errors are received in each of two consecutive frames. Once Idle is declared, it is not cleared until at least 16 pattern errors are received in each of two consecutive M-frames (T1.231). In addition to detection of the pattern, the DS3 signal must be in-frame and P-bit errors are binned during Idle detection. Register bits: DS3_IDLEPAT_DET_[A--B][12--1], DS3_IDLEPAT_DETD[A--B][12--1] (Table 484 and Table 496), DS3_IDLEPAT_DETM_[A--B][12--1] (Table 510 and Table 522). C-Bit Detection and X-Bit Detection In addition to the fixed information bit patterns, AIS and Idle signals are transmitted with all C bits set to 0 and both X-bits set to 1. These conditions are monitored and reported in DS3_CBZ_DET_[A--B][12--1] (Table 537 and Table 551) and DS3_RAI_DET_[A--B][12--1] (Table 538 and Table 552) bits. If every C bit in three consecutive DS3 frame is 0, set DS3_CBZ_DET_[A--B][12--1] = 1. If the three C bits in a single M subframe are 1, clear the associated DS3_CBZ_DET_[A--B][12--1] bit. If both X bits (RAI or yellow signal) in two consecutive M frames are received as 0 (error-free), the device sets DS3_RAI_DET_[A--B][12--1] = 1. Once this bit is set, it is not cleared until both X bits in two consecutive Mframes are received as 1. The user may wish to declare AIS or idle based on a combination of some of the DS3_CBZ_DET, DS3_RAI_DET, and DS3_AISPAT_DET or DS3_IDLEPAT_DET bits. Register bits: DS3_CBZ_DET_[A--B][12--1], DS3_CBZ_DETD_[A--B][12--1] (Table 485 and Table 497), DS3_CBZ_DETM_[A--B][12--1] (Table 511 and Table 523), DS3_RAI_DET_[A--B][12--1], DS3_RAI_DETD_[A--B][12--1] (Table 486 and Table 498), DS3_RAI_DETM_[A--B][12--1] (Table 512 and Table 524). Near-End Path Failure Event and Count Near-end path failure event and count are detected via a host microprocessor. Agere Systems Inc. 489 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Functional Description (continued) DS3 OH Bits Processor All overhead bits defined in a 44.736 kbit/s multiframe structure are defined in the table below. Bold bits are processed by the OH processor block, while all other bits are ignored. Table 453. Overhead Bits Defined in a 44.736 Mbits/s Multiframe Structure Note: F1, F2, F3, F4 = 1001, M1, M2, M3 = 010, X1 = X2, P1 = P2, C31 = C32 = C33. The 56 overhead bits sequential positions as follows: X1 X2 P1 P2 M1 M2 M3 F1 F1 F1 F1 F1 F1 F1 C11 C21 C31 C41 C51 C61 C71 F2 F2 F2 F2 F2 F2 F2 C12 C22 C32 C42 C52 C62 C72 F3 F3 F3 F3 F3 F3 F3 C13 C23 C33 C43 C53 C63 C73 F4 F4 F4 F4 F4 F4 F4 X-Bit Detection The X bits are used to indicate received errored multiframes to the remote-end (remote-alarm indication RAI or yellow signal); these bits are set to binary 1 (i.e., X1 = X2 =1) during error-free conditions, and to binary 0 (i.e., X1 = X2 = 0) if OOF or AIS are detected in the incoming signal. See C-Bit Detection and X-Bit Detection section on page 489 for monitoring information. 490 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Functional Description (continued) P Bits (P1, P2) For each channel that is DS3 mapped, parity is calculated over the 4704 data bits (84 info bits * 8 blocks/subframe * 7 subframes/multiframe) following the X1 bit. Parity errors are accumulated in a read-only saturating counter. The coding violation parameter count (CVP-P) counter increments if at least one of the P bits disagree with the parity of the previous frame. This counter is cleared on a 0-to-1 transition of the PMRST (pin D7, Table 10, Pin Descriptions--Microprocessor Interface Signals on page 117) input signal. Register bits: DS3_PERR_CNT_[A--B][1--12][13:0] (Table 567 and Table 573). C31, C32, and C33 CP Bits CP bits are used to carry path (end-to-end facility) parity information. The network terminating equipment (NTE) that originates the DS3 signal must set these bits (C31 = C32 = C33) to the same value as the P bits. The CP-bit coding violation parameter count (CVCP-P) counts frames with at least two of the three C-bit parity bits indicating an error. Register bit: DS3_CPERR_CNT_[A--B][1--12][13:0] (Table 568 and Table 574). C41, C42, and C4 FEBE Bits FEBE bits are used to carry far-end block error information. All three FEBE bits are set to 1 (C41 = C42 = C43 = 1) if no errors are detected in the M bits, or F bits, or indicated by the CP bits. If any error condition is detected within the M frame, the FEBE bits must be set to any combination of 1s or 0s (except 111). The CVCP-PFE counter accumulates FEBE error indications (one error indication for each M-frame with at least one FEBE bit equal to zero). Register bit: DS3_FEBE_CNT_[A--B][1--12][13:0] (Table 569 and Table 575). C13 FEAC (Far-End Alarm and Control) FEAC is used to receive alarm and status information from the far-end terminal and to initiate or terminate line loopbacks (not supported) at the request of the far-end terminal. The FEAC signal consists of a 16-bit code word of format 0iiiiii011111111 with the right-most bit transmitted first (1); i = information bit. When no code words are transmitted, the FEAC channel is set to all 1s. After validation (four consecutive times), the code word is stored in register (DS3_RFEAC_CODE_[A--B][12--1][5:0] (Table 544 and Table 558)). If the validated codeword equals one of the codewords listed in Table 454, the RAI state bit is set. Otherwise, the RAI state bit is zero (DS3_RFEAC_RAI_[A--B][12--1] (Table 539 and Table 553), DS3_RFEAC_RAID_[A--B][12--1] (Table 487 and Table 499), DS3_RFEAC_RAIM_[A--B][12--1] (Table 513 and Table 525)). If the validated code word is not listed in Table 454, the DS3_RFEAC_CTL_[A--B][12--1] (Table 540 and Table 554) state bit is set; otherwise, this state bit is 0 (DS3_RFEAC_CTLD_[A--B][12--1] (Table 488 and Table 500), DS3_RFEAC_CTLM_[A--B][12--1] (Table 514 and Table 526)). Agere Systems Inc. 491 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Functional Description (continued) Table 454. RAI Code Words Value (LSB) 011001 (MSB) 001110 000000 010110 C5X Processing The C51, C52, and C53 bits are used for a 28.2 kbits/s terminal-to-terminal path maintenance data link. The implementation of this data link is optional and therefore is not monitored in this block. All Other C-Bit Processing C11, C12, C2X, C6X, and C7X should be set to all 1s. These bits are ignored. PRBS Detector The test-pattern detector contains a self-synchronizing detector using the identical QRSS sequence as found in the test-pattern generator (220 - 1 and 215 - 1). When the detector is out of sync, the device continually monitors the input data signal for matches to the expected data signal. When the device detects 32 matches in a row, it declares itself in sync and the error detector is enabled. If the device detects eight consecutive mismatches, the test-pattern detector declares itself out of sync and starts searching again. When in sync, the device counts the number of times the input data differs from the expected data in an 8-bit counter that holds its count when it reaches the maximum value of 255. This counter is reset when read by the microprocessor and is not affected by the PMRST (pin D7) input signal. This function is enabled on two time slots at a time, and the data must be DS3 or PLCP frame encoded. Two PRBS detectors are implemented per slice. Setting the DS3_RPRBS_TSSEL_[A--B][2--1][3:0] (Table 562 and Table 565) value to 0xF will disable the PRBS algorithm and reset all counters and state machine values to their reset default states. Register bits: DS3_RPRBS_TSSEL_[A--B][2--1][3:0], DS3_RPRBS_INV_[A--B][1:0] (Table 561 and Table 564), DS3_RPRBS_SYNC_ERR_[A--B][1:0] (Table 543 and Table 557), DS3_RPRBS_SYNC_ERRD_[A--B][1:0] (Table 491 and Table 503), DS3_RPRBS_SYNC_ERRM_[A--B][1:0] (Table 517 and Table 529), DS3_RPRBS_DS3_PLCP_[A--B][1:0] (Table 562 and Table 565), DS3_RPRBS_15or20_[A--B][1:0] (Table 562 and Table 565), DS3_RPRBS_ERRCNT_[A--B][1--2][7:0] (Table 545 and Table 559). DS3 Loss of Signal DS3 Out of Frame DS3 AIS Received Description DS3 Equipment Failure Service Affecting 492 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Functional Description (continued) DS3 PLCP (Physical Layer Convergence Protocol) Framer Once the data is extracted by the DS3 framer, if that data is PLCP mapped, PLCP framing must be performed. Otherwise, the data is sent through this block unmodified. If the data is PLCP encoded, framing is performed by checking for the A1A2 pattern. Framing: In-frame is declared after two consecutive A1A2 and two consecutive path overhead indicator (POI) patterns are detected in a row. Out of frame is declared after five consecutive A1A2 mismatches or five consecutive POI values are received in error. An alarm is issued on a per time-slot basis each time the framer changes state. Until the in-frame state is declared, all data is marked as invalid leaving this block for the associated time slot. Register bits: DS3_PLCP_OOF_[A--B][12--1] (Table 541 and Table 555), DS3_PLCP_OOFD_[A--B][12--1] (Table 489 and Table 501), DS3_PLCP_OOFM_[A--B][1--12] (Table 515 and Table 527). B1 Monitoring The BIP-8 is computed over the 12 x 54 octet structure consisting of the POH fields and the associated ATM cells of the previous PLCP frame and compared to the received BIP-8 value, and the errors are accumulated in a 16-bit saturating counter. This counter is cleared by the PMRST signal, and the error value per frame is sent to the transmit direction for insertion into the G1[7:4] bits. Register bits: DS3_PLCP_B1ERRCNT_[A--B][1--12][15:0] (Table 570 and Table 576). G1 Monitoring The G1[7:4] FEBE error value is binned in a 16-bit saturating counter that is cleared by the PMRST signal. Valid values are 0 to 8. Any value outside this range is considered 0 errors (DS3_PLCP_G1_FEBE_ERRCNT_[A-- B][1--12][15:0] (Table 571 and Table 577)). The G1[3] RAI value is monitored for a change in state. Each time a validated change of state is detected (DS3_PLCP_CNTD_G1_RAI_[A--B][3:0] (Table 562 and Table 565)), a delta bit is set (DS3_PLCP_G1_RAI_[A-- B][12--1] (Table 542 and Table 556), DS3_PLCP_G1_RAID_[A--B][12--1] (Table 490 and Table 502), and DS3_PLCP_G1_RAIM_[A--B][12--1] (Table 516 and Table 528)). All other bits are ignored. Agere Systems Inc. 493 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Transmit Direction The DS3 transmit block consists of three functional blocks. They are the FIFO block used to buffer packets from the data engine, the PLCP frame insert block used to pack ATM cells into a PLCP frame and insert the byte overhead associated with this format, and the DS3 frame insert block that inserts the valid data from the FIFO block in to a DS3 frame. The PLCP and DS3 frame insert blocks can be bypassed for pass-through traffic (virtual concatenation, etc.). Channel ID to slice/time-slot number mapping is provided for bidirectional alarm insertion in the DS3 (X1, X2) and PLCP (G1) frames. Register bits: DS3_TDS3PLCP[1--16][1:0] (Table 578); 00 = no mapping, 01 = DS3 locked mode, 10 = DS3 clear channel, 11 = DS3/PLCP mapped signal, DS3_TXCHID_TO_TSMAPPING[1--16][1:0][3:0] (Table 578) = channel ID to slice/time-slot mapping [A--B][0--11]; A = 3, B = 2; illegal values default to all selected signals are inactive (0). The DS3 locked mode allows the insertion of DS3 overhead bytes into a received packed of length (84 * 7 bytes). The DS3 frame insert mechanism will synchronize to the EOP marker. Each time the EOP marker changes position, an event indication is set (DS3_TXEOPERRE[16--1] (Table 505), DS3_TXEOPERRM[16--1] (Table 531)). The EOP marker indicates when the next MSByte contains the start of the packet. The DS3_TXEOPERRE[16--1] indicates when the EOP marker changes position in the PLCP mapping mode or DS3 locked mode. FIFO Block The FIFO block accepts data from the data engine input 32 bits at a time. Each 32 bits is associated with a channel ID, a data valid indicator and a data marker for the entire bus, and an EOP marker per byte to indicate the end of a packet (ATM, HDLC, etc). All valid data (valid indicator and data marker = 1) is written into the associated FIFO location (16 active channels x 32 locations x 36 bits = 18,432 bits (~ 36,864 gates) for the selected channel ID. Data is not read out of the FIFO until data has accumulated above the lower threshold (DS3_TFIFO_MIN[5:0] (Table 582)), and blank requests are sent if the FIFO reaches the upper threshold (DS3_TFIFO_MAX[5:0] (Table 582)). Writes to the FIFO always occur for valid data even if the FIFO will overflow. In this case, the FIFO is considered empty and reads are disabled until the lower threshold is reached. Reads from the FIFO are designed as a pull mechanism. The receiving block allows data for a particular channel ID or sends a blank request for that channel ID to the DS3 framer block. A blank request guarantees no valid data is sent to the PT block. The DS3 block requests or inhibits data from the PLCP block by asserting its data valid signal. This same mechanism exists between the PLCP framer and FIFO. The PLCP block can inhibit reads from the FIFO if it does not need data. The FIFO will issue blank requests upstream once the high-buffer threshold is exceeded. This is the only mechanism that will cause blank requests to be issued for a selected channel ID. Register bits: DS3_TFIFO_MIN[5:0], DS3_TFIFO_MAX[5:0], DS3_TFIFO_OVR_UNFLE_[16--1] (Table 504), and DS3_TFIFO_OVR_UNFLM_[16--1] (Table 530). 494 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 PLCP Frame/Data Insert Frame Format Insert This block is responsible for creating the PLCP frame if the associated channel is PLCP encoded; otherwise, the data is sent through unchanged. The channel being processed is controlled incoming channel ID. The PLCP block will request 32 bits from the FIFO when needed. The PLCP frame floats within the DS3 frame. ATM cell header locations are determined by the location of the EOP marker. If an EOP marker abruptly changes location, the remaining PLCP ATM location will be filled with 0s. This ensures the receive framer will stay in PLCP frame. Frame Alignment (A1, A2) The A1 (0xF6) and A2 (0x28) framing bytes are the same as SONET and SDH A1 and A2 bytes, respectively. The A2 byte can be inverted through (DS3_TPLCP_A2INV[1--16] (Table 578)). Path Overhead Identifier (P00--P11) The path overhead identifier (POI) indexes the adjacent path overhead (POH) octet of the PLCP. Table 455 provides the coding for each of the P00--P11 octets. The most significant bit can be inverted through (DS3_TPLCP_POIB7INV[1--16] (Table 578)). Table 455. POI Values POI P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 P01 P00 POI Code 0010_1100 0010_1001 0010_0101 0010_0000 0001_1100 0001_1001 0001_0101 0001_0000 0000_1101 0000_1000 0000_0100 0000_0001 POH Z6 Z5 Z4 Z3 Z2 Z1 X B1 G1 X X C1 Growth Octets (Z1--Z6 and X Bytes) The growth octets are reserved for future use. These octets are set to 0. PLCP Path Error Monitoring (B1) The BIP-8 field is calculated over a 12 x 54 octet structure consisting of the POH field and the associated ATM cells (648 octets) of the previous PLCP frame. The B1 byte can be inverted on a per-channel basis by setting (DS3_TPLCP_B1INV[1--16] (Table 578)). Agere Systems Inc. 495 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 PLCP Frame/Data Insert (continued) PLCP Path Status (G1) The PLCP path status is allocated to convey the received PLCP status and performance to the transmitting farend. Table 456 illustrates the G1 octet subfields: a 4-bit far-end block error (FEBE), a 1-bit remote alarm indication (RAI), and 3 X bits (X bits are set to all 1s). The FEBE is the number of B1 errors detected in the previous received PLCP frame. Valid values are 0--8. The outgoing FEBE value can be forced to a programmable value through (DS3_TPLCP_FEBE_SWENB[1--16] (Table 578), DS3_TPLCP_FEBE_DINS[3:0] (Table 581)). The same data value is used for all channels while the enable signals are per channel. The RAI bit is set to a logic 1 when the associated PLCP framer is in the out-of-frame state. This value can be overwritten through DS3_TPLCP_RAI_SWENB[1--16] (Table 578) and DS3_TPLCP_RAI_DINS[1--16] (Table 578). Table 456. G1 Byte Definition Far-End Block Error (FEBE) 4 bits (MSB) Cycle/Stuff Counter (C1) The cycle/stuff counter provides a nibble stuffing opportunity cycle and length indicator for the PLCP frame. A stuffing opportunity occurs every third frame of a three-frame (375 s) stuffing cycle. The value of the C1 code is used as an indication of the phase of the 375 s stuffing opportunity cycle. Table 457 shows that a trailer containing 13 nibbles is used in the first frame of the 375 s stuffing opportunity cycle. A trailer of 14 nibbles is used in the second frame. The third frame provides a nibble stuffing opportunity. The contents of each of the 13/14 trailer nibbles will be 1100. Table 457. Trailer Length C1 Code 1111_1111 (0xFF) 0000_0000 (0x00) 0110_0110 (0x66) 1001_1001 (0x99) Frame Phase of Cycle 1 2 3 (no stuff) 3 (stuff) Trailer Length 13 14 13 14 RAI 1 bit X-X-X 3 bits (LSB), Set to 111 The algorithm for generating the stuff bytes is summarized in Table 458. Sequence number 1 is repeated 28 times, and then sequence 2 is created. This sequence repeats after 255 PLCP frames. Table 458. PLCP Nibble Stuff Sequence Sequence Number 1 Sequence 13 - 14 - 14 13 - 14 - 13 13 - 14 - 14 2 13 - 14 - 13 1 Repeat Sequence N Times 28 496 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Frame Generate/OH Bit Inserter F Bits and M Bits Insert The DS3 frame generator is responsible for generating the M-frame as shown in Figure 61. It generates and inserts the subframe framing bits F1, F2, F3, F4 = 1001, respectively, and the framing bits M1, M2, M3 = 010, respectively. These bits can be corrupted by setting DS3_TDS3_FINV[1--16] (Table 579) to 1. This causes the F bits to be set to 1000. To corrupt the M bits, set the DS3_TDS3_MINV[1--16] (Table 579) to 1. This causes the M bits to be set to 011. X Bits Insert This block is responsible for setting the X bits. These bits are set to a binary 1 during an error-free condition or to a binary 0 if DS3_LOF, DS3_OOF, DS3_AISPAT_DET are detected in the associated received signal. The X bits must persist for 1 second after change of state. This means 0 to 1 or 1 to 0. The X-bit value is provisioned through (DS3_TDS3_XDINS[1--16] (Table 579)). P Bits (P1, P2) This block is responsible for computing parity over the previous M-frame data bits (4704). If the digital sum is 1, P1 = P2 = 1; otherwise, P1 = P2 = 0. If the DS3_TDS3_PINV[1--16] (Table 579) is set to a logic 1, the P bits are inverted. C Bits Insert Allocation of C bits for C-bit parity applications is summarized in Table 459. Table 459. C-Bit Insert C Bit C11, C12 C13 Set to binary 1. FEAC is a 16-bit code word of the form 0x5x4x3_x2x1x00_1111_1111 with the right-most bit sent first. Description Settings -- When DS3_TDS3_TFEAC_INS[1-- 16] (Table 579) bit is a 0 the C13-bit is set to a logic 1. When the control bit is set to a 1, the C13 bit is sent as a 16-bit repeating code word. DS3_TDS3_TFEAC_CODE[1-- 16][5:0] (Table 579) is sent as shown (bit 5 = x5). The 16-bit codeword must be repeated at least 10 times, or while the condition exists, whichever is longer. -- Setting the DS3_TDS3_CPINV[1--16] (Table 579) = 1 inverts all CP bits. An override bit (DS3_TDS3_FEBEINS[1--16] (Table 579) = 1, set the FEBE bits to 000. -- -- -- C21, C22, C23 C31, C32, C33 C41. C42, C43 Not used; set to binary 1. C31 = C32 = C33 = computed P-bit value. C41 = C42 = C43 = 1 if no errors are detected in the received M or F bits or indicated by the received CP bits. If any errors are detected in the previous received DS3 frame, the FEBE bits are set to 000. Nominal carries the LAPD message. This feature is optional and is not supported (C51 = C52 = C53 = 1). Not used; must be set to binary 1. Not used, must be set to binary 1. C51, C52, C53 C61, C62, C63 C71, C72, C73 Agere Systems Inc. 497 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Frame Generate/OH Bit Inserter (continued) Data Bits There are four types of data that can be inserted in to the d bits. They are idle. AIS, pseudorandom data, or data engine data. This is programmable through DS3_TDS3_AIS[1--16] (Table 579), DS3_TDS3_IDLE[1--16] (Table 579); 00 or 11 = data engine data, 01 = idle, 10 = AIS. AIS Insert When AIS is forced, the pattern 1010 . . . is sent in the data bits with a 1 starting after each overhead bit. Additionally, the X1 = X2 = 1 and all C bits are set to 0. Idle Insert When idle is forced, the pattern 1100 . . . is sent in the data bits with a 1 starting after each overhead bit. Additionally, the X1 = X2 = 1 and C bits are generated normally. PRBS Sequence When a pseudorandom sequence is inserted, a (215 - 1) or ((220 - 1) (x20 + x17 + 1 = 0 with a 14 zero limit) sequence is inserted into the data bits with the pattern starting after each overhead bit. Additionally, all overhead bits function normally. This pattern can be inserted in to the PLCP ATM cell payload bytes or the DS3 i bits. Register bits: DS3_TPRBS_CHID_INS[1--2][5:0], DS3_TPRBS15or20[1--2], DS3_TPRBS_DS3orPLCP[1--2], DS3_TPRBS_INV[1--2], DS3_TPRBS_1BERRINS[1--2] all (Table 580). Transparent Payload Mode (Used in Conjunction with DS3 Mapping) Transparent payload mode is used in conjunction with DS3 mapping. In this mode, full frames of DS3 payload bytes are treated as fixed-length packets. The packets are 588 bytes long; each M subframe contains 84 data bytes (eight blocks of 84D bits), and there are seven M subframes in a DS3 multiframe, giving 7 x 84 = 588 data payload bytes per DS3 multiframe. The DS3 frame structure is shown for reference in Figure 61. The fixed-length packet format allows a user to map data into consistent locations in a DS3 frame so that they can implement any desired sub-DS3-rate mapping (standard or nonstandard). To use this mode, configure the DS3 block to be active, and configure the DE in transparent payload mode. Configure the corresponding UT channel/interface for packets and ensure that there is enough bandwidth to avoid starvation. Other blocks are configured as usual. It is then possible to post/preprocess data from this fixed 588-byte format to any other format that may be needed. Payload data is mapped between the 588-byte packet format and the DS3 payload format in time order of transmission. The MSB of the first byte of the 588-byte packet is mapped to the first DS3 payload data bit. The first ten and a half bytes of the 588-byte packet format go into the first 84D block of the DS3 multiframe. This mapping continues from left to right, top to bottom through the entire DS3 frame. It is also possible to use this mode for monitoring the contents of an SPE (i.e., to observe the number of 7E bytes between packets or to verify the operation of the HDLC byte escaper), but in this case, there is no indication of the beginning of the SPE (i.e., first byte following J1). 498 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description The DS3/E3 block is an enhancement of the DS3 block of the (TADM042G5 (TADMV1B)) device. The E3 subblock was implemented in MARS2G5 P-Pro for E3 mapping into the VC-3, AU-3, and AUG path as shown in Figure 57. The E3 (34.368 Mbits/s) signal is mapped into a VC-3 and then to an AU-3 as shown in Figure 58. The final step is multiplexing the AU-3 map into an AUG. SONET DS3 MAPPING STS-1 SPE DS3 SDH DS3/E3 MAPPING xN AUG x1 AU-4 VC-4 x3 x1 TUG-3 TU-3 VC-3 x3 AU-3 VC-3 C-3 DS3(44.736) OR E3 (34.368) THIS PATH IS EQUIVALENT TO SONET STS-1 DS3 SPE MAPPING 2318(F) Note: Shaded mappings are supported. AU-3 and STS-1 are equivalent. Figure 57. DS3/E3 Mappings Agere Systems Inc. 499 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) 1 J1 B3 C2 G1 F2 H4 F3 K3 N1 VC-3 POH 29 30 31 58 59 60 87 C-3 C-3 C-3 VC-3 PLUS 2 COLUMNS OF FIXED STUFF (84 DATA COLUMNS) FLOATING PHASE H1 H2 H3 AU-3 2319(F) Figure 58. VC-3 Into an AU-3 A 34.368 Mbits/s signal can be mapped into a VC-3 as shown in Figure 59. In addition to the VC-3 POH, the VC-3 consists of a payload of 9 x 84 bytes every 125 s. This payload is divided in three subframes, each subframe consisting of: 1431 data bits (D); two sets of five justification control bits (C1, C2); two justification opportunity bits (S1, S2); 573 fixed stuff bits (R); Two sets of five justification control bits C1 and C2 are used to control the two justification opportunity bits S1 and S2, respectively. C1C2C3C4C5 = 00000 indicates that the S1 is a data bit while C1C2C3C4C5 = 11111 indicates that S1 is a justification bit. C2 bits control S2 in the same way. Majority vote should be used to make the justification decision in the desynchronizer for protection against single and double bit errors in the C bits. The value contained in S1 and S2, when they are justification bits, is not defined. To maintain the E3 rate in the transmit direction, the S1 bit should be a fixed stuff bit while the S2 bit is a data bit. 500 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) J1 B3 C2 G1 F2 H4 F3 K3 N1 1 VC-3 POH T1 T2 T3 84 bytes 3 3 3 3 3 3 3 3 3 C3 3 3 3 3 3 3 3 3 3 C3 3 3 3 3 3 3 3 3 3 C3 3 3 3 3 3 3 3 3 3 C3 3 3 3 3 3 3 3 3 3 C3 3 3 3 3 3 3 3 3 3 AB 1 = RRRRRRRR (FIXED STUFF) C = RRRRRRC1C2 A = RRRRRRRS1 B = S2DDDDDDD 3 = THREE DATA bytes (DDDDDDDD) 1 = ONE DATA byte (DDDDDDDD) 2320(F) Figure 59. Asynchronous Mapping of 34,368 kbits/s Tributary Into VC-3 E3 Frame Format Requirements from ITU-T G.832 (10/98) The basic G.832 E3 frame structure at 34,368 kbits/s comprises 7 octets of overhead and 530 octets of payload capacity per 125 s as shown in Table 463. Agere Systems Inc. 501 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) 59 COLUMNS FA1 FA2 EM TR MA NR GC 530 OCTET PAYLOAD 9 ROWS 2321(F) Figure 60. G.832 E3 Frame Structure at 34,368 kbits/s E3 Overhead Octets The values and allocation of the overhead octets are shown in Table 460 and described below. Table 460. Overhead Allocation at 34,368 kbits/s FA1 EM TR MA NR GC RDI REI 1 1 1 1 0 1 1 0 0 0 1 0 1 0 0 0 FA2 BIP-8 Trail Trace--16-Byte Sequence Payload Type MFI SSM Network Operator Byte GP Communication Channel 502 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) Frame Synchronization Bytes (Frame Alignment: FA1/FA2) Frame alignment signal values 0xF6/0x28 (11110110 00101000). This pattern is inserted at the transmitter at the beginning of each 125 s frame interval. The receiver identifies the pattern to establish frame alignment so that all other bytes can be properly located and interpreted. Performance Byte (Error Monitoring: EM) One byte is allocated for error monitoring. This function will be a BIP-8 code using even parity. The BIP-8 is calculated over all bits, including the overhead bits, of the previous 125 s frame. The receiver compares this received parity value with the parity computed by receiver. The result of this comparison indicates the error performance of the connection between the transmitter and the receiver. Trail Trace Byte (TR) This byte is used to repetitively transmit a trail access point identifier so that a trail receiving terminal can verify its continued connection to the intended transmitter. A 16-byte frame is defined for the transmission of the access point identifier. The most significant bit (MSB) of the message is a logic 1 value while all other MSBs are 0. Agere Systems Inc. 503 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) MA--Maintenance and Adaptation Byte Each bit in the MA byte is defined in the table below. Table 461. MA Byte Description Bit 7 Bit 6 Bits[5:3] RDI REI Payload Type Set when the associated receive E3 signal is in an alarm state. This bit is controlled under software control only. This bit is set to 1 if one or more errors were detected by the BIP-8, otherwise set to 0. Code 000 001 010 011 Others Bits[2:0] Multiframe Indicator/ SSM* Bit 2 0 0 1 1 Signal Unequipped Equipped, Nonspecific ATM SDH TU-12s Undefined Bit 1 0 1 0 1 Bit 0 SSM Bit 3 (MSB) SSM Bit 2 SSM Bit 1 SSM Bit 0 (LSB) * Bit 0 is used in a four-frame multiframe. The phase of the multiframe is determined by the value of MA bits 2 and 1. The 4 bits of the multiframe are allocated to the synchronization status message (SSM). When interworking with old equipment that used bit 0 as a timing marker (nonmultiframe), the new equipment implementing the above requirement should be capable of being configured to transmit the old requirement as given below. Bit 0, timing marker. This bit is set to 0 to indicate that the timing source is traceable to a primary reference clock, and is otherwise set to 1. NR--Network Operator Byte This byte is allocated for maintenance purposes specific to individual network operators. Its transparency from trail termination to trail termination is not guaranteed. For tandem connection maintenance, the byte is used in accordance with Annex D/G.707. Tandem connection maintenance is not supported by this block. This byte is not supported. GC General purpose communication channel (e.g., to provide data/voice channel connection for maintenance purposes). This byte is not supported. 504 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) Mapping of ATM Cells into 34,368 kbits/s--ITU-T G.804 (02/98) The ATM cells are mapped into the 530 payload octets of the 34,368 kbit/s frame with the octet structure of the cell aligned with the octet structure of the frame. The ATM cell payload (48 bytes) shall be scrambled before mapping into the 34,368 kbit/s signal. E3-PLCP Frame Format The E3-PLCP format consists of 57 bytes x 9 rows with a programmable trailer of 17 to 21 octets in length. The G.751 E3 framing bytes are defined to be (1111010000 A N 1100) as shown in the G.751 E3 frame in Table 462. The overhead bits are defined as an alarm indication bit (A or RAI) and a national use bit (N). The least significant nibble is set to a fixed pattern of 1100. Table 462. G.751 E3 Frame Format 1 1 1 1 0 1 0 0 0 0 RAI NA 1 1 0 0 368 Payload Bits C11 C21 C31 C41 C12 C22 C32 C42 C13 C23 C33 C43 J1 J2 J3 J4 380 Payload Bits 380 Payload Bits 376 Payload Bits Note: Framing occurs on 10-bit pattern 1111010000. When ATM cells are either directly mapped or with a PLCP frame, all C and J bits are used as data bits. Table 463. E3-PLCP Mapping of ATM Cells Framing (3 octets) A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 P8 P7 P6 P5 P4 P3 P2 P1 P0 POH Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 53 octets ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell Trailer (17--21) Agere Systems Inc. 505 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) E3-PLCP Field Definitions The PLCP frame has framing, path overhead (POH), data, and trailer bytes. Framing Octets (A1, A2). The first two columns (A1, A2) are used for frame delineation (A1 = 0xF6, A2 = 0x28). Path Overhead Identifier (P0--P8). The third column identifies the PLCP overhead octets contained in the fourth column of Table 463. The left most 6 bits of these octets provide numbering of the 9 rows. The 7th bit is reserved, and the right-most bit (LSB) is parity bit. The reserved bit is set to 0. The parity bit provides odd parity over this field. A code is considered invalid if it does not match a value in Table 464 or its parity bit is invalid and will not be used to transition the in-PLCP-frame state. Table 464. Path Overhead Identifier Codes (POI) POI P8 P7 P6 P5 P4 P3 P2 P1 P0 Row Count Value 001 000 000 000 000 000 000 000 000 000 111 110 101 100 011 010 001 000 Reserved Odd Parity 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 PLCP Path User Channel (F1). The F1 octet is the user channel, which is allocated for user communication purposes between adjacent PLCPs. The default code for this octet is 00000000. Bit Interleaved Parity-8 (B1). One octet is allocated for PLCP path error monitoring. This function is a bit interleaved parity-8 (BIP-8) code using even parity. The PLCP path BIP-8 is calculated over the 9 x 54 octet structure (columns 4 to 57, numbering from 1) of the previous PLCP frame and inserted into the B1 of the current frame. 506 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) PLCP Path Status (G1). The G1 octet is allocated to convey the received PLCP status and performance back to the transmitting PLCP. The G1 octet consists of: 4 bits for far-end block error (FEBE--G1[7:4]) code. -- FEBE code may be used to convey the count of the interleaved-bit blocks that have been detected to be in error by the BIP-8 code in the preceding frame. If implemented, this count has nine legal values, namely zero (0000) to eight (1000) errors. If not implemented, the code is 1111. All other codes are interpreted as zero errors. 1 bit for the alarm signal (AS). -- The AS bit is set to a logic 1 when a received failure is detected. This bit is set under software control only. 3 bits for a link status signal (LSS). -- The remaining 3 bits are used for the LSS as described in IEEE Standard 802.6 Section 11.3.2. The LSS is used to communicate information about the status of the transmission link between two adjacent PLCP entities. The function is not supported and the bits are set to 111. The G1 fields are illustrated in Table 465. Table 465. PLCP G1 byte 7 6 5 4 3 AS 2 1 LSS 0 FEBE DQDB Layer Management Information Octets (M1, M2). The octets M1 and M2 carry the DQDB layer management information octets that are described in IEEE Standard 802.6, Section 10.1. These bytes are not supported and set to 0. Agere Systems Inc. 507 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) Stuffing (C1). The C1 octet indicates the PLCP frame in which an octet stuffing will occur and contains the number of trailer octets transmitted (17 to 21). The allowed C1 codes are as per Table 466. Table 466. C1 Values and Transmit Insert Sequence Trailer Byte Value 17 18 19 20 21 Sequence Type A B 18 18 19 19 Numbering 7 6 001 010 011 100 101 Sequence 18 19 18 5 4 Protection Code 3 1101 0111 1010 1110 0011 Transmit C1 Insert Sequence Repeat N times 6 1 2 1 Not Used 0 1 1 1 1 1 0x3B 0x4F 0x75 0x9D 0xA7 Hex The C1 codes above provide error correction capability for one bit error and two adjacent bit errors, and error detection capability for three random bit errors using the Abramson code (x3 + x + 1)(x + 1). Growth Octets (Z1--Z3). These octets are reserved for future use. These octets are encoded to the default code of 00000000. 508 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) Register Description Control Bits for G.751 E3 Frame, E3 PLCP Frame, and G.832 Frame This section describes the monitoring and insert capabilities for G.751 E3 frame, E3 PLCP frame, and G.832 E3 frame. Rx/Tx Mode Control Definition. Three bits are used in the receive/transmit directions to determine the mapping/ demapping mode. See Table 467 and Table 468. Table 467. Receive Mode Control Signals Control Bit RDS3orE3 0 0 0 0 1 1 1 1 RDS3PLCP[1:0] 00 01 10 11 00 01 10 11 DS3/Clear Channel Mapping DS3/PLCP Mapping X/No Mapping E3/G.832 Frame E3/G.751 Frame E3/G.751 PLCP Mapping X/ No Mapping 000, No Mapping Mode Reset Default Mode Table 468. Transmit Mode Control Signals Control Bit TDS3orE3 0 0 0 0 1 1 1 1 TDS3PLCP[1:0] 00 01 10 11 00 01 10 11 No Mapping DS3 Locked Mode DS3 Clear Channel DS3/PLCP Mapping X/No Mapping E3/G.832 Frame E3/G751 Frame E3/G751 PLCP Mapping 000, No Mapping Mode Reset Default Mode Agere Systems Inc. 509 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 19, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) G.751 E3 Frame. This block implements only direct or PLCP mapping into the G.751 E3 frame. ATM cells are octet aligned with the 16 overhead bits at the start of each frame. See Table 462 for the G.751 E3 frame format. Table 469. G.751 E3 Frame Transmit Overhead Operation Control Bit Frame Alignment Signal RAI: Remote Alarm Indication (A) NA: National Use Bit Cjk: Justification Service Bits Jk: Tributary Justification Bits Transmit Direction Insert value 10b`1111010000. TE3_FA_INV[16--1] Insert the RAI value under software control only. Set the NA bit to 0. Included as part of payload. Included as part of payload. TE3_RAI_DINS[16--1] No Control Bit No Control Bit No Control Bit Register Bits Table 470. G.751 E3 Frame Receive Overhead Operation Control Bit Frame Alignment Signal Receive Direction Out of frame = 0, when the pattern (10 or 14 bits) has been detected for three consecutive frames. Out of frame = 1, when four consecutive frames are detected with errors. Loss of frame = 1, when the associated OOF bit is high continuously for a programmable number of frame periods (range 0 to 4 ms in 125 s steps). Loss of frame = 0, when the associated OOF bit is low continuously for a programmable number of frame periods. RAI: Remote Alarm Indication NA: National Use Bit Cjk: Justification Service Bits Monitor with a programmable continuous N times detect (CNTD), 0 to 15. Not monitored. Process as part of payload. Register Bits E3_OOF[A--B][12--1], E3_OOF[A--B][12--1]D/M, E3_G751_10or14bit_FRMPAT E3_LOF[A--B][12--10], E3_LOF[A--B][12--1]D/M E3_LOF_SETCNT[4:0], E3_LOF_CLRCNT[4:0] E3_G751_RAI_DET_CNTD[3:0], E3_G751_RAI_DET[A--B][12--1], E3_G751_RAI_DET[A--B][12--1]D/M No Control Bit No Control Bit No Control Bit Jk: Tributary Justification Process as part of payload. Bits 510 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) AIS Insertion and Detection. Insertion. Under software control, an all 1s pattern can be generated to replace the G.751 E3 frame and payload bytes (TE3_AISINS[16--1]). Detection. E3_AISPAT_DET = 1, when less than a programmable number of 0s are detected during one complete frame period while the framer is in the out-of-frame mode (E3_OOF = 1). E3_AISPAT_DET = 0, when greater than or equal to a programmable number of 0s are detected during one complete frame period, or the framer is in frame (E3_OOF = 0). Register bits: E3_G751_AIS_0CNT[3:0] (Default Value = 5), E3_AISPAT_DET[A--B][12--1], E3_AISPAT_DET[A--B][12--1]D/M. Agere Systems Inc. 511 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) G.751 E3 PLCP Frame. The PLCP frame is octet aligned to the 16 overhead bits. There is no relationship between the start of the PLCP frame and the start of the E3 frame. Table 471. G.751 E3-PLCP Transmit Overhead Operation Control Bit A1, A2: Frame P0--P8: Path Overhead Identifier Z1--Z3: Growth F1: User Channel Transmit Direction Insert A1, A2 values (0xF6, 0x28), respectively. Insert per Table 464. Insert a programmable value into the selected time slot from the associated software register; otherwise, insert a fixed value of all zeros. A calculated BIP-8 value over the previous frame (Col. 4 to 57) is inserted into this byte. G1[7:4] = FEBE indicates the number of B1 errors detected in the receive direction. The FEBE field has nine legal values (4b`0000 to 4b`1000). Its value can be inserted under software control (used for testing). G1[3] = AS, This bit is programmable through the microprocessor interface. G[2:0] = LSS, This function is not supported and fixed to (3b`111). M1 and M2: Control Information This function is not supported. Set both octets to (00000000). C1: Stuff Counter Table 466 defines the sequence used for the C1 byte to yield a nominal PLCP frame rate of 125 s. The C1 value can only change by 1 at any value change. No control bits No control bits Register Bits TE3_PLCP_A2_INV[16--1] TE3_PLCP_POIB7_INV[16--1] TE3_PLCP_ZF_CHID[5:0], TE3_PLCP_Z1_DINS[7:0],TE3_ PLCP_Z2_DINS[7:0], TE3_PLCP_Z3_DINS[7:0], TE3_PLCP_F1_DINS[7:0], TE3_PLCP_B1_INV [16--1] TE3_PLCP_FEBE_SWEN [16--1], TE3_PLCP_FEBE_DINS [3:0], TE3_PLCP_G1_AS_DINS [16--1] B1: Bit Interleaved Parity G1: Path Status 512 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) Table 472. G.751 E3-PLCP Receive Overhead Operation Control Bit A1, A2: Frame Receive Direction Register Bits E3_PLCP_OOF[A--B][12--1], Out-of-frame = 0, when the pattern has been detected for two consecutive rows, along with two E3_PLCP_OOF[A--B][12--1]D/M valid POI octets. Out-of-frame = 1, when errors are detected in both octets in a single row, or when errors are detected in two consecutive POI octets. Loss-of-frame = 1, when the associated OOF bit is high continuously for a programmable number of frame periods (range 0 to 4 ms in 125 s steps). Loss-of-frame = 0, when the associated OOF bit is low continuously for a programmable number of frame periods. Used in PLCP framing. These bytes are independently monitored for a CNTD value change. E3_PLCP_LOF[A--B][12--1], E3_PLCP_LOF[A--B][12--1]D/M E3_PLCP_LOF_SETCNT[4:0], E3_PLCP_LOF_CLRCNT[4:0] No status bits E3_PLCP_ZF_CNTD[3:0], E3_PLCP_ZF_TSSEL[A-D][3:0], E3_PLCP_ZF_DMON [A--B]D/M E3_PLCP_Z1_DMON[A--B][7:0], E3_PLCP_Z2_DMON[A--B][7:0], E3_PLCP_Z3_DMON[A--B][7:0], E3_PLCP_F1_DMON[A--B][7:0] E3_PLCP_B1ERRCNT [A--B][12--1][15:0], E3_PLCP_B1_BITBLK E3_PLCP_G1_FEBE_BITBLK, E3_PLCP_G1_FEBE_ERRCNT [A--B][12--1][15:0], E3_PLCP_G1_AS[A--B][12--1], E3_PLCP_G1_AS[A--B][12-- 1]D/M, E3_PLCP_G1_AS_CNTD[3:0] No status bits No status bits P0--P8: Path Overhead Identifier Z1--Z3: Growth F1: User Channel B1: Bit Interleaved Parity The received BIP-8 value is checked against the calculated value. Any differences are accumulated in a saturating counter. This counter can count bit or block errors; this is a per block control bit. G1: Path Status G1[7:4] = FEBE, All legal values are accumulated in a saturating counter. This counter can accumulate bit or block errors; this is a per block control bit. G1[3] = AS, This bit is monitored for a CNTD value change. This is a per block control bit. G[2:0] = LSS, This function is not supported and ignored. These octets are ignored. The stuff counter is decoded and error correction is performed to determine the number of trailer bytes (see Stuffing (C1). The C1 octet indicates the PLCP frame in which an octet stuffing will occur and contains the number of trailer octets transmitted (17 to 21). The allowed C1 codes are as per Table 466. on page 508). M1 and M2: Control Information C1: Stuff Counter Agere Systems Inc. 513 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) G.832 E3 Frame Overhead Operation. The G.832 E3 frame format allows direct byte mapping of ATM cells. ATM cells are octet aligned with the G.832 E3 frame. This block does not support E3 PLCP mapped ATM cells in the G.832 E3 frame. Table 473. G.832 E3 Transmit Frame Overhead Operation Control Bit A1, A2: Frame Transmit Direction Insert FA1, FA2 as 0xF6, 0x28, respectively. The framing pattern can be inverted under software control. Inserts even parity (BIP-8) calculated over the entire frame including the overhead bits. Register Bits TE3_FA_INV[16--1] EM: Error Monitor BIP-8 TR: Trail Trace TE3_B1_INV[16--1] Inserts the 16-byte identifier from provisionable TE3_TR_INS[16--1], registers when enabled; otherwise, set TR byte to TE3_TR_DINS[16--1][15--0][7:0] 00000000. MA[7] = RDI, This bit is software provisionable only. MA[6] = REI, Set to 1 if one or more BIP-8 errors were detected in the associated E3 signal. If the error insert bit is zero, follow the hardware value; otherwise, force the bit to 1 continuously. MA[5:3] = Payload type. Insert value under software control. MA[2:0] = Multiframe indicator and SSM pattern. Bits[2:1] are a multiframe pattern counting from 0 to 3. A multiframe count of 0 = MSB of SSM four bit pattern. To support old equipment, set all SSM values to 0 or 1. TE3_MA_RDI_DINS[16--1], TE3_MA_REI_ERRINS[16--1], MA: Maintenance and Adaptation Byte TE3_MA_PTYPE_DINS[16-- 1][2:0], TE3_MA_SSM[16--1][3:0]. NR: Network Operator Byte Inserts a fixed value (00000000) for this byte. Software insert is not supported. No control bits No control bits GC: General-Purpose Inserts a fixed value (00000000) for this byte. Communication Channel Software insert is not supported. 514 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) Table 474. G.832 E3 Receive Frame Overhead Operation Control Bit A1, A2: Frame Receive Direction Out of frame = 0, when the pattern has been detected for two consecutive frames. Out of frame = 1, when four consecutive frame are detected with errors. Loss of frame = 1, when the associated OOF bit is high continuously for a programmable number of frame periods (range 0 to 4 ms in 125 s steps). Loss of frame = 0, when the associated OOF bit is low continuously for a programmable number of frame periods. EM: Error Monitor BIP-8 Computes the incoming BIP-8 and compares that value to the incoming value. Errors are accumulated in a 14-bit saturating counter. Bit or block errors can be accumulated (block control bit). Compares the TR 16-byte pattern with an expected value. (See description in G.832 E3 Frame TR-Byte Processing on page 516.) Register Bits E3_OOF[A--B][12--1], E3_OOF[A--B][12--1]D/M E3_LOF[A--B][12--1], E3_LOF[A--B][12--1]D/M E3_LOF_SETCNT[4:0], E3_LOF_CLRCNT[4:0] E3_B1_ERRCNT [A--B][12--1][13:0], E3_B1_BITBLK E3_TR_MODE[A--B][12--1][1:0], E3_TR_MISMATCH [A--B][12--1]D/M, E3_TR_MISMATCH[A--B][12--1], E3_TR_EXP[A--B][12--1][15--0][7:0], E3_TR_CAP[A--B][12--1][15--0][7:0] E3_G832_MA_RDI_CNTD[3:0], E3_G832_MA_RDI_DET [A--B][12--1]D/M, E3_G832_MA_RDI_DET [A--B][12--1], E3_MA_REI_ERRCNT [A--B][12--1][13:0], E3_MA_PT_CNTD[3:0], E3_MA_PT[A--B][12--1]D/M, E3_MA_PT_CODE [A--B][12--1][2:0], E3_MA_MF_ENABLE[A--B][12--1], E3_MA_SSM_CNTD[3:0], E3_MA_SSM[A--B][12--1]D/M, E3_MA_SSM_CODE [A--B][12--1][3:0] TR: Trail Trace MA: Maintenance and Adaptation Byte MA[7] = RDI, this bit is monitored using a CNTD monitor. MA[6] = REI, A saturating counter accumulates the REI values. MA[5:3] = Payload type (PT). A CNTD monitor is used on this field. A stable value is accessible through the P interface. MA[2:0] = In nonmultiframe alignment mode, bit 0 is monitored for a CNTD value. In multiframe alignment mode, a CNTD detection is performed on the 4-bit SSM message. NR: Network Operator Byte Byte not monitored. No status bits No status bits GC: General Purpose Byte not monitored. Communication Channel Agere Systems Inc. 515 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Functional Description (continued) AIS Insertion and Detection. Insertion. Under software control an all 1s pattern can be generated to replace the G.751 E3 frame and payload bytes (TE3_AISINS[16--1]). Detection (Default = 8 Matches/Mismatches). E3_AISPAT_DET = 1, when less than a programmable number of 0s are detected during one complete frame period (E3 G.751 frame (192 bytes)), while the framer is in the out-offrame mode (E3_OOF = 1). E3_AISPAT_DET = 0, when greater than or equal to a programmable number of 0s are detected during one complete frame period, or the framer is in frame (E3_OOF = 0). Register bits: E3_G832_AIS_0CNT[3:0], E3_AISPAT_DET[A--B][11--0], E3_AISPAT_DET[A--B][11--0]D/M. G.832 E3 Frame TR-Byte Processing The TR byte carries a repeating 16-byte message. The block extracts the message from all E3 channels and stores the message in an internal register bank. Three types of monitoring are allowed: 1. Mode = 00, disable function. 2. Mode = 01, monitor for a mismatch between the incoming value and an expected value. -- A mismatch is declared if the received message differs from the expected message for ten consecutive messages. A mismatch clears when 4-out-of-5 received messages match the expected message. -- In this mode, the device frames on the most significant bit (MSB) of the first byte in the message being set to 1. 3. Mode = 10, monitor for a sustained change in the message. -- A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message and the device starts checking for a sustained change from this new stable message. -- In this mode, no framing on the MSB occurs. 4. Mode = 11, capture incoming data. 516 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Functional Description (continued) Transmit Channel ID to Time-Slot Alarm Mapping The control bits to provide this function are TxChidtoTSMapping[16--1][1:0][3:0], where [16--1] = channel ID number, [1:0] = slice (A = 00, B, C, or D = 11, respectively), and [3:0] = time slots 0 to 11. The following signals are transferred from the receive in each mode. 1. G.832 E3 framing mode. -- MA byte, REI--One bit signal that toggles for each error detected in the received EM byte. 2. G.751 E3 framing mode. -- No status bits transferred. 3. G.751 E3 PLCP framing mode. -- G1 byte, FEBE, 4-bit field, and single toggles for each error. PRBS Insert and Monitor A 223 - 1 PRBS pattern can be generated and placed in either E3 frame or the E3 PLCP frame under software control. See Table 475 and Table 476 for the control bit summary for the receive and transmit directions, respectively. These bits, along with the other PRBS insert/monitor bits already defined (see DS3 requirements), control the PRBS functions. Table 475. PRBS Receive (Monitor) Pattern Control Signals Control Bit RPRBS23 0 0 1 1 RPRBS_15or20 0 1 X 215 - 1 220 - 1 223 - 1 Mode Table 476. PRBS Transmit Pattern Control Signals Control Bit TPRBS23 0 0 1 1 TPRBS15or20 0 1 X 215 - 1 220 - 1 223 - 1 Mode Agere Systems Inc. 517 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions DS3 Global Registers Table 477. DS3E3_VERR, Version Control (RO) Address 0x5000 Bit 15:8 7:0 Name -- DS3E3_VER[7:0] Reserved. Block Version. Indicates version number of this block. Function Reset Default 0x00 0x00 Table 478. DS3_SCRATCHR, Scratch Register (R/W) Address 0x5001 Bit 15:0 Name DS3_SCRATCH [15:0] Function Reset Default Read/write register with no other internal DS3 connections. 0x0000 Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event Registers (R/W) Address 0x5002 Bit 15 Name DS3_COR_COWN Function Control bit, when set (0) all delta and event registers function in the clear-on-write (COW) mode; otherwise, they function in the clear-on-read (COR) mode. Reserved. Monitor receive output signals (active-high) DS3_TM_DATA <= ("00000000000000", DS3_RXSYNC, DS3_RXPM_A, DS3_RXEOP_A, DS3_RXPM_B, DS3_RXEOP_B, DS3_RXPM_C, DS3_RXEOP_C, DS3_RXPM_D, DS3_RXEOP_D, DS3_RXDATA_A, DS3_RXDATA_B, DS3_RXDATA_C, DS3_RXDATA_D); Reset Default 0 14:12 11 -- SEQ_RX -- 0x0 518 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event Registers (R/W) (continued) Address 0x5002 Bit 10 Name TM_RX Function Control inputs into the receive direction (active-high) if (TM_RX = '1') the PT_RXSYNC_i <= TM_DATA(40); PT_RXJ1_A_i <= TM_DATA(39); PT_RXPM_A_i <= TM_DATA(38); PT_RXJ1_B_i <= TM_DATA(37); PT_RXPM_B_i <= TM_DATA(36); PT_RXJ1_C_i <= TM_DATA(35); PT_RXPM_C_i <= TM_DATA(34); PT_RXJ1_D_i <= TM_DATA(33); PT_RXPM_D_i <= TM_DATA(32); PT_RXDATA_A_i <= TM_DATA(31:24); PT_RXDATA_B_i <= TM_DATA(23:16); PT_RXDATA_C_i <= TM_DATA(15:8); PT_RXDATA_D_i <= TM_DATA(7:0); else PT_RXSYNC_i <= PT_RXSYNC; PT_RXJ1_A_i <= PT_RXJ1_A; PT_RXPM_A_i <= PT_RXPM_A; PT_RXDATA_A_i <= PT_RXDATA_A; PT_RXJ1_B_i <= PT_RXJ1_B; PT_RXPM_B_i <= PT_RXPM_B; PT_RXDATA_B_i <= PT_RXDATA_B; PT_RXJ1_C_i <= PT_RXJ1_C; PT_RXPM_C_i <= PT_RXPM_C; PT_RXDATA_C_i <= PT_RXDATA_C; PT_RXJ1_D_i <= PT_RXJ1_D; PT_RXPM_D_i <= PT_RXPM_D; PT_RXDATA_D_i <= PT_RXDATA_D; end if; Monitor transmit output signals (active-high) DS3_TM_DATA <= ("00", PT_TXBR, PT_TXBR_CID, DS3_TXBR, DS3_TXBR_CID, DS3_TXPM, DS3_TXCID, DS3_TXDATA); Reset Default 0x0 9 PT_TX 0x0 Agere Systems Inc. 519 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event Registers (R/W) (continued) Address 0x5002 Bit 8 Name TM_TX Function Control inputs into the transmit direction (active-high) DS3_TM_DATA <= ("00000000000000000", "00000000000000000", "00000000000000", DS3_TXBR_CID, DS3_TXBR); if (TM_TX = '1') then DE_TXDATA_i <= TM_DATA(31 0); DE_TXPM_i <= TM_DATA(32); DE_TXDVLD_i <= TM_DATA(33); DE_TXEOP_i <= TM_DATA(37:34); DE_TXCID_i <= TM_DATA(43: 38); else DE_TXDATA_i <= DE_TXDATA; DE_TXPM_i <= DE_TXPM; DE_TXDVLD_i <= DE_TXDVLD; DE_TXEOP_i <= DE_TXEOP; DE_TXCID_i <= DE_TXCID; end if; Reserved. GPO_ADDRESS can be 0x00 to 0x2b. Configure the GPO_ADDRESS to this register, and this address is passed to DS3_GPO_MUX block to select one of GPO outputs when it is selected to read. Reset Default 0x0 7:6 5:0 -- GPOSEL[5:0] -- 000000 520 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Interface A Delta/Event Registers Table 480. DS3FRMD_A, DS3 Out-of-Frame Delta (COR/COW) Address 0x5003 Bit 15:12 11:0 Name -- DS3_OOFD_ A[12--1] Reserved. Each time the DS3_OOF_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 481. DS3LOFD_A, DS3 Loss-of-Frame Delta (COR/COW) Address 0x5004 Bit 15:12 11:0 Name -- DS3_LOFD_ A[12--1] Reserved. Each time the DS3_LOF_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Agere Systems Inc. 521 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 482. DS3SEFD_A, DS3 Severely Errored Frame (SEF) Delta (COR/COW) Address 0x5005 Bit 15:12 11:0 Name -- DS3_SEFD_ A[12--1] Reserved. Each time the DS3_SEF_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 483. DS3AISD_A, DS3 AIS Detection Delta (COR/COW) Address 0x5006 Bit 15:12 11:0 Name -- DS3_AISPAT_ DETD_A[12--1] Reserved. Each time the DS3_AISPAT_DET_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 484. DS3IDLED_A, DS3 Idle Detection Delta (COR/COW) Address 0x5007 Bit 15:12 11:0 Name -- DS3_IDLEPAT_ DETD_A[12--1] Reserved. Each time the DS3_IDLEPAT_DET_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 485. DS3CBD_A, DS3 C-Bit Detect Delta (COR/COW) Address 0x5008 Bit 15:12 11:0 Name -- DS3_CBZ_DETD_ A[12--1] Reserved. Each time the DS3_CBZ_DET_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 486. DS3RAID_A, DS3 X-Bit Detect Delta (COR/COW) Address 0x5009 Bit 15:12 11:0 Name -- DS3_RAI_DETD_ A[12--1] Reserved. Each time the DS3_RAI_DET_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 522 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 487. DS3FEACALMD_A, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW) Address 0x500A Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 DS3_RFEAC_RAID_ Each time the DS3_RFEAC_RAI_A[12--1] state bit A[12--1] changes state (0 to 1 or 1 to 0), the delta bit is set. Table 488. DS3FEACCTLD_A, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW) Address 0x500B Bit 15:12 11:0 Name -- DS3_RFEAC_ CTLD_A[12--1] Reserved. Each time the DS3_RFEAC_CTL_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 489. DS3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW) Address 0x500C Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x0FFF DS3_PLCP_OOFD_ Each time the DS3_PLCP_OOF_A[12--1] state bit A[12--1] changes state (0 to 1 or 1 to 0), the delta bit is set. Table 490. DS3_PLCPRAID_A, PLCP RAI (G1[3]) Monitoring Delta (COR/COW) Address 0x500D Bit 15:12 11:0 Name -- DS3_PLCP_G1_ RAID_A[12--1] Reserved. Each time the DS3_PLCP_G1_RAI_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 491. DS3_RXPRBS_SYNCD_A, PRBS Detector Sync Delta (COR/COW) Address 0x500E Bit 15:2 1:0 Name -- Reserved. Function Reset Default 0x000 11 DS3_RPRBS_ Each time the DS3_RPRBS_SYNC_ERR_A[12--1] state SYNC_ERRD_A[1:0] bit changes state (0 to 1 or 1 to 0), the delta bit is set. Agere Systems Inc. 523 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Interface B Delta/Event Registers Table 492. DS3FRMD_B, DS3 Out-of-Frame Delta (COR/COW) Address 0x500F Bit 15:12 11:0 Name -- DS3_OOFD_ B[12--1] Reserved. Each time the DS3_OOF_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 493. DS3LOFD_B, DS3 Loss-of-Frame Delta (COR/COW) Address 0x5010 Bit 15:12 11:0 Name -- DS3_LOFD_ B[12--1] Reserved. Each time the DS3_LOF_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 494. DS3SEFD_B, DS3 Severely Errored Frame (SEF) Delta (COR/COW) Address 0x5011 Bit 15:12 11:0 Name -- DS3_SEFD_ B[12--1] Reserved. Each time the DS3_SEF_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 495. DS3AISD_B, DS3 AIS Detection Delta (COR/COW) Address 0x5012 Bit 15:12 11:0 Name -- DS3_AISPAT_ DETD_B[12--1] Reserved. Each time the DS3_AISPAT_DET_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 496. DS3IDLED_B, DS3 Idle Detection Delta (COR/COW) Address 0x5013 Bit 15:12 11:0 Name -- DS3_IDLEPAT_ DETD_B[12--1] Reserved. Each time the DS3_IDLEPAT_DET_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 524 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 497. DS3CBD_B, DS3 C-Bit Detect Delta (COR/COW) Address 0x5014 Bit 15:12 11:0 Name -- DS3_CBZ_DETD_ B[12--1] Reserved. Each time the DS3_CBZ_DET_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 498. DS3RAID_B, DS3 X-Bit Detect Delta (COR/COW) Address 0x5015 Bit 15:12 11:0 Name -- DS3_RAI_DETD_ B[12--1] Reserved. Each time the DS3_RAI_DET_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 499. DS3FEACALMD_B, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW) Address 0x5016 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 DS3_RFEAC_RAID_ Each time the DS3_RFEAC_RAI_B[12--1] state bit B[12--1] changes state (0 to 1 or 1 to 0), the delta bit is set. Table 500. DS3FEACCTLD_B, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW) Address 0x5017 Bit 15:12 11:0 Name -- DS3_RFEAC_ CTLD_B[12--1] Reserved. Each time the DS3_RFEAC_CTL_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x0FFF Table 501. DS3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW) Address 0x5018 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x0FFF DS3_PLCP_OOFD_ Each time the DS3_PLCP_OOF_B[12--1] state bit B[12--1] changes state (0 to 1 or 1 to 0), the delta bit is set. Agere Systems Inc. 525 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 502. DS3_PLCPRAID_B, PLCP RAI (G1[3]) Monitoring Delta (COR/COW) Address 0x5019 Bit 15:12 11:0 Name -- DS3_PLCP_G1_ RAID_B[12--1] Reserved. Each time the DS3_PLCP_G1_RAI_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 503. DS3_RXPRBS_SYNCD_B, PRBS Detector Sync Delta (COR/COW) Address 0x501A Bit 15:2 1:0 Name -- Reserved. Function Reset Default 0x000 11 DS3_RPRBS_ Each time the DS3_RPRBS_SYNC_ERR_B[2:1] state bit SYNC_ERRD_B[1:0] changes state (0 to 1 or 1 to 0), the delta bit is set. Transmit Direction FIFO Overflow/Underflow Event Table 504. DS3_TXFIFOERRE, FIFO Overflow Indicator Event (COR/COW) Address 0x5033 Bit 15:0 Name DS3_TFIFO_OVR_ UNFLE[16--1] Function Transmit FIFO overflow or underflow event indication (active-high). Reset Default 0x0000 Transmit Direction EOP Marker Error Event Table 505. DS3_TXEOPERRER, EOP Marker Error Event (COR/COW) Address 0x5036 Bit 15:0 Name DS3_TXEOPERRE [16--1] Function EOP marker in PLCP or DS3 locked mode changed position. Reset Default 0 526 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Interface A Mask Registers Table 506. DS3FRMM_A, DS3 Out-of-Frame Mask (R/W) Address 0x5039 Bit 15:12 11:0 Name -- DS3_OOFM_ A[12--1] Reserved. DS3 Out-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 507. DS3LOFM_A, DS3 Loss-of-Frame Mask (R/W) Address 0x503A Bit 15:12 11:0 Name -- DS3_LOFM_ A[12--1] Reserved. DS3 Loss-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 508. DS3SEFM_A, DS3 Severely Errored Frame (SEF) Mask (R/W) Address 0x503B Bit 15:12 11:0 Name -- DS3_SEFM_ A[12--1] Reserved. DS3 Severely Errored Frame (SEF) Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 509. DS3AISM_A, DS3 AIS Detection Mask (R/W) Address 0x503C Bit 15:12 11:0 Name -- DS3_AISPAT_ DETM_A[12--1] Reserved. DS3 AIS Detection Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 510. DS3IDLEM_A, DS3 Idle Detection Mask (R/W) Address 0x503D Bit 15:12 11:0 Name -- DS3_IDLEPAT_ DETM_A[12--1] Reserved. DS3 Idle Detection Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Agere Systems Inc. 527 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 511. DS3CBM_A, DS3 C-Bit Detect Mask (R/W) Address 0x503E Bit 15:12 11:0 Name -- DS3_CBZ_DETM_ A[12--1] Reserved. DS3 C-Bit Detect Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 512. DS3RAIM_A, DS3 X-Bit Detect Mask (R/W) Address 0x503F Bit 15:12 11:0 Name -- DS3_RAI_DETM_ A[12--1] Reserved. DS3 X-Bit Detect Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 513. DS3FEACALMM_A, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W) Address 0x5040 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_RFEAC_RAIM_ DS3 Far-End Alarm and Control (FEAC) Alarm Mask. A[12--1] When set high, the delta will not contribute to the interrupt signal. Table 514. DS3FEACCTLM_A, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W) Address 0x5041 Bit 15:12 11:0 Name -- DS3_RFEAC_ CTLM_A[12--1] Reserved. DS3 Far-End Alarm and Control (FEAC) Control Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 515. DS3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W) Address 0x5042 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_PLCP_OOFM_ PLCP Out-of-Frame Monitor Mask. When set high, the A[12--1] delta will not contribute to the interrupt signal. 528 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 516. DS3_PLCPRAIM_A, PLCP RAI (G1[3]) Monitoring Mask (R/W) Address 0x5043 Bit 15:12 11:0 Name -- DS3_PLCP_G1_ RAIM_A[12--1] Reserved. PLCP RAI (G1[3]) Monitoring Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 517. DS3_RXPRBS_SYNCM_A, PRBS Detector Sync Mask (R/W) Address 0x5044 Bit 15:2 1:0 Name -- Reserved. Function Reset Default 0x000 11 DS3_RPRBS_ PRBS Detector Sync Mask. When set high, the delta will SYNC_ERRM_A[1:0] not contribute to the interrupt signal. Interface B Mask Registers Table 518. DS3_DS3FRMM_B, DS3 Out-of-Frame Mask (R/W) Address 0x5045 Bit 15:12 11:0 Name -- DS3_DS3_OOFM_ B[12--1] Reserved. DS3 Out-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 519. DS3LOFM_B, DS3 Loss-of-Frame Mask (R/W) Address 0x5046 Bit 15:12 11:0 Name -- DS3_LOFM_ B[12--1] Reserved. DS3 Loss-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 520. DS3SEFM_B, DS3 Severely Errored Frame (SEF) Mask (R/W) Address 0x5047 Bit 15:12 11:0 Name -- DS3_SEFM_ B[12--1] Reserved. DS3 Severely Errored Frame (SEF) Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Agere Systems Inc. 529 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 521. DS3AISM_B, DS3 AIS Detection Mask (R/W) Address 0x5048 Bit 15:12 11:0 Name -- DS3_AISPAT_ DETM_B[12--1] Reserved. DS3 AIS Detection Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 522. DS3IDLEM_B, DS3 Idle Detection Mask (R/W) Address 0x5049 Bit 15:12 11:0 Name -- DS3_IDLEPAT_ DETM_B[12--1] Reserved. DS3 Idle Detection Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 523. DS3CBM_B, DS3 C-Bit Detect Mask (R/W) Address 0x504A Bit 15:12 11:0 Name -- DS3_CBZ_DETM_ B[12--1] Reserved. DS3 C-Bit Detect Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 524. DS3RAIM_B, DS3 X-Bit Detect Mask (R/W) Address 0x504B Bit 15:12 11:0 Name -- DS3_RAI_DETM_ B[12--1] Reserved. DS3 X-Bit Detect Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 525. DS3FEACALMM_B, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W) Address 0x504C Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_RFEAC_RAIM_ DS3 Far-End Alarm and Control (FEAC) Alarm Mask. B[12--1] When set high, the delta will not contribute to the interrupt signal. 530 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 526. DS3FEACCTLM_B, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W) Address 0x504D Bit 15:12 11:0 Name -- DS3_RFEAC_ CTLM_B[12--1] Reserved. DS3 Far-End Alarm and Control (FEAC) Control Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 527. DS3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W) Address 0x504E Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_PLCP_OOFM_ PLCP Out-of-Frame Monitor Mask. When set high, the B[12--1] delta will not contribute to the interrupt signal. Table 528. DS3_PLCPRAIM_B, PLCP RAI (G1[3]) Monitoring Mask (R/W) Address 0x504F Bit 15:12 11:0 Name -- DS3_PLCP_G1_ RAIM_B[12--1] Reserved. PLCP RAI (G1[3]) Monitoring Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 529. DS3_RXPRBS_SYNCM_B, PRBS Detector Sync Mask (R/W) Address 0x5050 Bit 15:2 1:0 Name -- Reserved. Function Reset Default 0x000 11 DS3_RPRBS_ PRBS Detector Sync Mask. When set high, the delta will SYNC_ERRM_B[1:0] not contribute to the interrupt signal. Agere Systems Inc. 531 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Transmit Direction FIFO Overflow/Underflow Mask Table 530. DS3_TXFIFOERRM, FIFO Overflow Indicator Mask (R/W) Address 0x5069 Bit 15:0 Name DS3_TFIFO_OVR_ UNFLM[16--1] Function Reset Default FIFO Overflow Indicator Mask. Transmit FIFO overflow or 0xFFFF underflow event indication (active-high). Transmit Direction EOP Marker Error Mask Table 531. DS3_TXEOPERRM, EOP Marker Error Mask (R/W) Address 0x506C Bit 15:0 Name DS3_TXEOPERRM [16--1] Function EOP Marker Error Mask. EOP marker in PLCP or DS3 locked mode changed position. Reset Default 0xFFFF 532 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Interface A State Registers Table 532. DS3FRM_A, DS3 Out-of-Frame State (RO) Address 0x506F Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_OOF_A[12--1] DS3 Out-of-Frame State. State bit indicating on a per slice and time-slot basis if the DS3 framer is in frame. 0 = in frame, 1 = out of frame. Table 533. DS3LOF_A, DS3 Loss-of-Frame State (RO) Address 0x5070 Bit 15:12 11:0 Name -- DS3_LOF_A[12--1] Reserved. DS3 Loss-of-Frame State. State bit is set (1) when the DS3 framer is in the out-of-frame state for 28 continuous frame periods (approximately 3 ms). Function Reset Default 0x0 0xFFF Table 534. DS3SEF_A, DS3 Severely Errored Frame (SEF) (RO) Address 0x5071 Bit 15:12 11:0 Name -- DS3_SEF_A[12--1] Reserved. A SEF defect is the occurrence of three or more F-bit errors in 16 consecutive F bits. A SEF is cleared when the signal is in-frame and there are less than 3 F-bit errors in 16 consecutive F bits. Function Reset Default 0x0 0xFFF Table 535. DS3AIS_A, DS3 AIS Detection (RO) Address 0x5072 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 DS3_AISPAT_DET_ AIS is declared if fewer than five pattern errors (1010) are A[12--1] received in each of two consecutive M-frames. AIS is cleared when at least 16 pattern errors are received in each of two consecutive M-frames. Agere Systems Inc. 533 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 536. DS3IDLE_A, DS3 Idle Detection (RO) Address 0x5073 Bit 15:12 11:0 Name -- DS3_IDLEPAT_ DET_A[12--1] Reserved. Idle is declared if fewer than five pattern errors (1100) are received in each of two consecutive M-frames. Idle is cleared when at least 16 pattern errors are received in each of two consecutive M-frames. Function Reset Default 0x0 0x000 Table 537. DS3CB_A, DS3 C-Bit Detect (RO) Address 0x5074 Bit 15:12 11:0 Name -- DS3_CBZ_DET_ A[12--1] Reserved. Set if every C bit in three consecutive M frames are set to 0; clear if the three C bits in a M subframe are 1. Function Reset Default 0x0 0x000 Table 538. DS3RAI_A, DS3 X-Bit Detect (RO) Address 0x5075 Bit 15:12 11:0 Name -- DS3_RAI_DET_ A[12--1] Reserved. Set if both X bits in two consecutive M frames are received as 0; clear when both X bits in two consecutive M frames are received as 1. Function Reset Default 0x0 0x000 Table 539. DS3FEACALM_A, DS3 Far-End Alarm and Control (FEAC) (RO) Address 0x5076 Bit 15:12 11:0 Name -- DS3_RFEAC_RAI_ A[12--1] Reserved. If the validated code equals (011001, 001110, 000000, or 010110), then the RAI state bit is set. When the validated code word does not equal one of the patterns above, the RAI state bit is 0. Function Reset Default 0x0 0x000 534 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 540. DS3FEACCTL_A, DS3 Far-End Alarm and Control (FEAC) (RO) Address 0x5077 Bit 15:12 11:0 Name -- DS3_RFEAC_CTL_ A[12--1] Reserved. If the validated code does not equal (011001, 001110, 000000, or 010110), then the CTL state bit is set. When the validated code word equals one of the patterns above, the CTL state bit is 0. Function Reset Default 0x0 0xFFF Table 541. DS3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO) Address 0x5078 Bit 15:12 11:0 Name -- DS3_PLCP_OOF_ A[12--1] Reserved. When the A1A2 pattern is detected in two consecutive rows, the PLCP framer is considered in-frame. The PLCP framer will transition to the OOF state when five consecutive A1A2 mismatches are detected or five consecutive POI mismatches occur. Function Reset Default 0x0 0xFFF Table 542. DS3_PLCPRAI_A, PLCP RAI (G1[3]) Monitoring (RO) Address 0x5079 Bit 15:12 11:0 Name -- DS3_PLCP_G1_ RAI_A[12--1] Reserved. While the PLCP framer is in the in-frame state, the RAI bit is validated for changes and the validated value is placed in this state register. Function Reset Default 0x0 0x000 Table 543. DS3_RXPRBS_SYNC_A, PRBS Detector Sync State (RO) Address 0x507A Bit 15:2 1:0 Name -- DS3_RPRBS_ SYNC_ERR_A[1:0] Reserved. When the device detects 32 matches in a row, it declares itself in-sync (DS3_RPRBS_SYNC_ERR[A--B][1:0] is cleared to 0) and the error detector is enabled. If the device detects eight consecutive mismatches, the test-pattern detector declares itself out-of-sync and starts searching again. Function Reset Default 0x000 11 Agere Systems Inc. 535 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 544. DS3FEACCODE_A[1--6], DS3 Far-End Alarm and Control (FEAC) (RO) Address 0x507B -- 0x5080 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_RFEAC_ This register is updated each time a validated code word is CODE_A[12--1][5:0] accepted (same code word four consecutive times) serially through the C13 bit. (Bit 5 = MSB of code word, LSB = Bit 0.) Table 545. DS3_RXPRBSERRCNT_A, PRBS Error Counter (RO) Address 0x5081 Bit 15:0 Name DS3_RPRBS_ ERRCNT_ A[2--1][7:0] Function The device counts the number of times the input data differs from the expected value in an 8-bit counter that holds its count when it reaches the maximum value of 255. This counter is reset when read by the microprocessor and is not affected by the PMRST signal. Reset Default 0x0000 Interface B State Registers Table 546. DS3FRM_B, DS3 Out-of-Frame State (RO) Address 0x5082 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_OOF_B[12--1] DS3 Out-of-Frame State. State bit indicating on a per slice and time-slot basis if the DS3 framer is in frame. 0 = in frame, 1 = out of frame. Table 547. DS3LOF_B, DS3 Loss-of-Frame State (RO) Address 0x5083 Bit 15:12 11:0 Name -- DS3_LOF_B[12--1] Reserved. DS3 Loss-of-Frame State. State bit is set (1) when the DS3 framer is in the out-of-frame state for 28 continuous frame periods (approximately 3 ms). Function Reset Default 0x0 0xFFF 536 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 548. DS3SEF_B, DS3 Severely Errored Frame (SEF) (RO) Address 0x5084 Bit 15:12 11:0 Name -- DS3_SEF_B[12--1] Reserved. A SEF defect is the occurrence of three or more F-bit errors in 16 consecutive F bits. A SEF is cleared when the signal is in-frame and there are less than 3 F-bit errors in 16 consecutive F bits. Function Reset Default 0x0 0xFFF Table 549. DS3AIS_B, DS3 AIS Detection (RO) Address 0x5085 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 DS3_AISPAT_DET_ AIS is declared if fewer than five pattern errors (1010) are B[12--1] received in each of two consecutive M frames. AIS is cleared when at least 16 pattern errors are received in each of two consecutive M frames. Table 550. DS3IDLE_B, DS3 Idle Detection (RO) Address 0x5086 Bit 15:12 11:0 Name -- DS3_IDLEPAT_ DET_B[12--1] Reserved. Idle is declared if fewer than five pattern errors (1100) are received in each of two consecutive M frames. Idle is cleared when at least 16 pattern errors are received in each of two consecutive M frames. Function Reset Default 0x0 0x000 Table 551. DS3CB_B, DS3 C-Bit Detect (RO) Address 0x5087 Bit 15:12 11:0 Name -- DS3_CBZ_DET_ B[12--1] Reserved. Set if every C bit in three consecutive M frames are set to 0; clear if the three C bits in a M subframe are 1. Function Reset Default 0x0 0x000 Agere Systems Inc. 537 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 552. DS3RAI_B, DS3 X-Bit Detect (RO) Address 0x5088 Bit 15:12 11:0 Name -- DS3_RAI_DET_ B[12--1] Reserved. Set if both X bits in two consecutive M frames are received as 0; clear when both X bits in two consecutive M frames are received as 1. Function Reset Default 0x0 0x000 Table 553. DS3FEACALM_B, DS3 Far-End Alarm and Control (FEAC) (RO) Address 0x5089 Bit 15:12 11:0 Name -- DS3_RFEAC_RAI_ B[12--1] Reserved. If the validated code equals (011001, 001110, 000000, or 010110), then the RAI state bit is set. When the validated code word does not equal one of the patterns above, the RAI state bit is 0. Function Reset Default 0x0 0x000 Table 554. DS3FEACCTL_B, DS3 Far-End Alarm and Control (FEAC) (RO) Address 0x508A Bit 15:12 11:0 Name -- DS3_RFEAC_CTL_ B[12--1] Reserved. If the validated code does not equal (011001, 001110, 000000, or 010110), then the CTL state bit is set. When the validated code word equals one of the patterns above, the CTL state bit is 0. Function Reset Default 0x0 0xFFF Table 555. DS3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO) Address 0x508B Bit 15:12 11:0 Name -- DS3_PLCP_OOF_ B[12--1] Reserved. When the A1A2 pattern is detected in two consecutive rows, the PLCP framer is considered in frame. The PLCP framer will transition to the OOF state when five consecutive A1A2 mismatches are detected or five consecutive POI mismatches occur. Function Reset Default 0x0 0xFFF 538 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 556. DS3_PLCPRAI_B, PLCP RAI (G1[3]) Monitoring (RO) Address 0x508C Bit 15:12 11:0 Name -- DS3_PLCP_G1_ RAI_B[12--1] Reserved. While the PLCP framer is in the in-frame state, the RAI bit is validated for changes and the validated value is placed in this state register. Function Reset Default 0x0 0x000 Table 557. DS3_RXPRBS_SYNC_B, PRBS Detector Sync State (RO) Address 0x508D Bit 15:2 1:0 Name -- DS3_RPRBS_ SYNC_ERR_B[1:0] Reserved. When the device detects 32 matches in a row, it declares itself in-sync (DS3_RPRBS_SYNC_ERR[A--B][1:0] is cleared to 0) and the error detector is enabled. If the device detects eight consecutive mismatches, the test-pattern detector declares itself out-of-sync and starts searching again. Function Reset Default 0x000 11 Table 558. DS3FEACCODE_B[1--6], DS3 Far-End Alarm and Control (FEAC) (RO) Address 0x508E -- 0x5093 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF DS3_RFEAC_ This register is updated each time a validated code word is CODE_B[12--1][5:0 accepted (same code word four consecutive times) serially through the C13 bit. (Bit 5 = MSB of code word, LSB = Bit 0.) Table 559. DS3_RXPRBSERRCNT_B, PRBS Error Counter (RO) Address 0x5094 Bit 15:0 Name DS3_RPRBS_ ERRCNT_ B[2--1][7:0] Function The device counts the number of times the input data differs from the expected value in an 8-bit counter that holds its count when it reaches the maximum value of 255. This counter is reset when read by the microprocessor, and is not affected by the PMRST signal. Reset Default 0x0000 Agere Systems Inc. 539 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Receive Interface A Control Registers Table 560. DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) Address 0x50BB Bit 15 Name Function Reset Default 0 DS3_OOF_FMODE_ DS3 Framer F-Bit Error Control. (0 = 3 or more errors in A 16 F bits) or (1 = 1 or more F-bit error in each of four consecutive M-subframes) declare the DS3 out of frame. -- DS3_RDS3PLCP_ A[6--1][1:0] Reserved. Receive Mode Control. 00 or 01 = no mapping, 10 = DS3 clear channel mapping, 11 = DS3/PLCP mapped signal. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. 14:12 11:0 0x0 0x000 Table 561. DS3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W) Address 0x50BC Bit 15:14 13:12 11:0 Name DS3_RPRBS_INV_ A[1:0] DS3_RPRBS23_ A[1:0] DS3_RDS3PLCP_ A[12--7][1:0] Function Control bit, when set, inverts the incoming pattern before synchronization occurs. Control bit, when set, generates a (223 - 1) PRBS pattern; otherwise, follow the RPRBS_15or20 control bit. Receive Mode Control. 00 or 01 = no mapping, 10 = DS3 clear channel mapping, 11 = DS3/PLCP mapped signal. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. Reset Default 00 00 0x000 540 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 562. DS3_RXPRBS_A, Receive PRBS (R/W) Address 0x50BD Bit 15:8 Name Function Reset Default 0xFF DS3_RPRBS_ PRBS Detector Time-Slot Detect. This register selects TSSEL_A[2--1][3:0] which time slot the PRBS detector will monitor. Valid values are 0 to 11, all illegal values disable the monitor. See DS3_RPRBS_DS3_PLCP_A[1:0] bits 7:6 of this table and DS3_PLCP_CNTD_G1_RAI_A[3:0] bits 3:0 of this table. DS3_RPRBS_DS3_ PRBS Detector Control. Control bit, when cleared, inserts PLCP_A[1:0] the PRBS sequence into a DS3 frame structure; otherwise, it causes the PRBS sequence insertion to occur in the PLCP ATM cell locations. DS3_RPRBS_ 15or20_A[1:0] Control bit, when set, generates a (220 - 1) QRSS pattern; otherwise, it generates a (215 - 1) PRBS pattern. 7:6 00 5:4 3:0 00 0xB DS3_PLCP_CNTD_ (PLCPRAI[x][y]) PLCP RAI (G1[3]) Monitoring. The RAI G1_RAI_A[3:0] is validated using a continuous N times detect (CNTD) mechanism, where the value must be the same for N times in a row. This value can be programmed from 0 to 7. A value of 0 or 1 causes the RAI value to be accepted each time it changes state. Receive Interface B Control Registers Table 563. DS3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W) Address 0x50BF Bit 15 Name Function Reset Default 0 DS3_OOF_FMODE_ DS3 Framer F-Bit Error Control. (0 = 3 or more errors in B 16 F bits) or (1 = 1 or more F-bit error in each of four consecutive M-subframes) declare the DS3 out of frame. -- DS3_RDS3PLCP_ B[6--1][1:0] Reserved. Receive Mode Control. 00 or 01 = no mapping, 10 = DS3 clear channel mapping, 11 = DS3/PLCP mapped signal. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. 14:12 11:0 0x0 0x000 Agere Systems Inc. 541 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 564. DS3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W) Address 0x50C0 Bit 15:14 13:12 11:0 Name DS3_RPRBS_INV_ B[1:0] DS3_RPRBS23_ B[1:0] DS3_RDS3PLCP_ B[12--7][1:0] Function Control bit, when set, inverts the incoming pattern before synchronization occurs. Control bit, when set, generates a (223 - 1) PRBS pattern; otherwise, follow the RPRBS_15or20 control bit. Receive Mode Control. 00 or 01 = no mapping, 10 = DS3 clear channel mapping, 11 = DS3/PLCP mapped signal. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. Reset Default 00 00 0x000 Table 565. DS3_RXPRBS_B, Receive PRBS (R/W) Address 0x50C1 Bit 15:8 Name Function Reset Default 0xFF DS3_RPRBS_ PRBS Detector Time-Slot Detect. This register selects TSSEL_B[2--1][3:0] which time slot the PRBS detector will monitor. Valid values are 0 to 11; all illegal values disable the monitor. See DS3_RPRBS_DS3_PLCP_B[1:0] bits 7:6 of this table and DS3_PLCP_CNTD_G1_RAI_B[3:0] bit 3:0 of this table. DS3_RPRBS_DS3_ PRBS Detector Control. Control bit, when cleared, inserts PLCP_B[1:0] the PRBS sequence into a DS3 frame structure; otherwise, it causes the PRBS sequence insertion to occur in the PLCP ATM cell locations. DS3_RPRBS_ 15or20_B[1:0] Control bit, when set, generates a (220 - 1) QRSS pattern; otherwise, it generates a (215 - 1) PRBS pattern. 7:6 00 5:4 3:0 00 0xB DS3_PLCP_CNTD_ (PLCPRAI[x][y]) PLCP RAI (G1[3]) Monitoring. The RAI G1_RAI_B[3:0] is validated using a continuous N times detect (CNTD) mechanism, where the value must be the same for N times in a row. This value can be programmed from 0 to 7. A value of 0 or 1 causes the RAI value to be accepted each time it changes state. 542 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Receive Interface A Counters Table 566. DS3_RXDS3FBIT_A[1--12], DS3 F-Bit and M-Bit Error Count (RO) Address 0x5100-- 0x510B Bit 15:14 13:0 Name -- DS3_FERR_CNT_ A[1--12][13:0] Reserved. This counter increments each time an error is detected in either an F bit or M bit while the DS3 framer is in frame. This counter is disabled while DS3_OOF = 1. Function Reset Default 00 0x0000 Table 567. DS3_RXDS3_CVP_P_A[1--12], DS3 P-Bit CVP-P Error Counter (CVP-P) (RO) Address 0x510C-- 0x5117 Bit 15:14 13:0 Name -- DS3_PERR_CNT_ A[1--12][13:0] Reserved. This counter increments if at least one of the P bits disagree with the parity of the previous frame. This counter saturates at its maximum value and is cleared by PMRST. Function Reset Default 00 0x0000 Table 568. DS3_RXDS3_CVCP_P_A[1--12], DS3 CP-Bit Error Counter (CVCP-P) (RO) Address 0x5118-- 0x5123 Bit 15:14 13:0 Name -- Reserved. Function Reset Default 00 0x0000 DS3_CPERR_CNT_ This counter increments if at least two of the three CP bits A[1--12][13:0] disagree with the parity of the previous frame. This counter saturates at its maximum value and is cleared by PMRST. Agere Systems Inc. 543 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 569. DS3_RXDS3FEBE_A[1--12], DS3 FEBE Error Counter (CVCP-PFE) (RO) Address 0x5124-- 0x512F Bit 15:14 13:0 Name -- DS3_FEBE_CNT_ A[1--12][13:0] Reserved. The counter increments whenever 1 of the FEBE bits (C41, C42, and C43) is set to zero in one M frame. This counter saturates at its maximum value and is cleared by PMRST. Function Reset Default 00 0x0000 Table 570. DS3_RXPLCPB1ECNT_A[1--12], PLCP B1 Error Count (RO) Address 0x5160-- 0x516B Bit 15:0 Name DS3_PLCP_ B1ERRCNT_ A[1--12][15:0] Function While the PLCP framer is in the in-frame state, the number of bit errors between the incoming BIP-8 and the calculated BIP-8 value is accumulated in a 16-bit saturating counter. This counter is cleared by the PMRST signal. Reset Default 0x0000 Table 571. DS3_PLCPFEBECNT_A[1--12], PLCP FEBE (G1[7:4]) Error Count (RO) Address 0x516C-- 0x5177 Bit 15:0 Name DS3_PLCP_G1_ FEBE_ERRCNT_ A[1--12][15:0] Function While the PLCP framer is in the in-frame state, the number of FEBE errors received (0--8) is accumulated in a 16-bit saturating counter. Values greater than eight are ignored. This counter is cleared by the PMRST signal. Reset Default 0x0000 544 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Receive Interface B Counters Table 572. DS3_RXDS3FBIT_B[1--12], DS3 F-Bit and M-Bit Error Count (RO) Address 0x5180-- 0x518B Bit 15:14 13:0 Name -- DS3_FERR_CNT_ B[1--12][13:0] Reserved. This counter increments each time an error is detected in either an F bit or M bit while the DS3 framer is in-frame. This counter is disabled while DS3_OOF = 1. Function Reset Default 00 0x0000 Table 573. DS3_RDS3_CVP_P_B[1--12], DS3 P-Bit CVP-P Error Counter (CVP-P) Address 0x518C-- 0x5197 Bit 15:14 13:0 Name -- DS3_PERR_CNT_ B[1--12][13:0] Reserved. This counter increments if at least one of the P bits disagree with the parity of the previous frame. This counter saturates at its maximum value and is cleared by PMRST. Function Reset Default 00 0x0000 Table 574. DS3_RXDS3_CVCP_P_B[1--12], DS3 CP-Bit Error Counter (CVCP-P) (RO) Address 0x5198-- 0x51A3 Bit 15:14 13:0 Name -- Reserved. Function Reset Default 00 0x0000 DS3_CPERR_CNT_ This counter increments if at least two of the three CP bits B[1--12][13:0] disagree with the parity of the previous frame. This counter saturates at its maximum value and is cleared by PMRST. Agere Systems Inc. 545 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 575. DS3_RXDS3FEBE_B[1--12], DS3 FEBE Error Counter (CVCP-PFE) (RO) Address 0x51A4-- 0x51AF Bit 15:14 13:0 Name -- DS3_FEBE_CNT_ B[1--12][13:0] Reserved. The counter increments whenever 1 of the FEBE bits (C41, C42, and C43) is set to 0 in one M frame. This counter saturates at its maximum value and is cleared by PMRST. Function Reset Default 00 0x0000 Table 576. DS3_RXPLCPB1ECNT_B[1--12], PLCP B1 Error Count (RO) Address 0x51C0-- 0x51CB Bit 15:0 Name DS3_PLCP_ B1ERRCNT_ B[1--12][15:0] Function While the PLCP framer is in the in-frame state, the number of bit errors between the incoming BIP-8 and the calculated BIP-8 value is accumulated in a 16-bit saturating counter. This counter is cleared by the PMRST signal. Reset Default 0x0000 Table 577. DS3_PLCPFEBECNT_B[1--12], PLCP FEBE (G1[7:4]) Error Count (RO) Address 0x51CC-- 0x51D7 Bit 15:0 Name DS3_PLCP_G1_ FEBE_ERRCNT_ B[1--12][15:0] Function While the PLCP framer is in the in-frame state, the number of FEBE errors received (0--8) is accumulated in a 16-bit saturating counter. Values greater than eight are ignored. This counter is cleared by the PMRST (pin D7) signal. Reset Default 0x0000 546 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Transmit Control Signals (Channel Based 1--16) Table 578. DS3_TDS3PLCPCTL1_CHD[1--16], Transmit PLCP (R/W) Address 0x5300-- 0x530F Bit 15:14 Name DS3_TDS3PLCP [1--16][1:0] Function Transmit Mode Control Per Channel. 00 = No mapping. 01 = DS3 locked mode. 10 = DS3 clear channel. 11 = DS3/PLCP mapped signal. 0 Reset Default 00 13 DS3_TPLCP_A2INV Transmit PLCP A2 Byte Invert Control. [1--16] 1 = Invert all A2 bytes (0xD7) of a PLCP frame. 0 = Send valid A2 byte values (0x28). DS3_TPLCP_ POIB7INV[1--16] DS3_TPLCP_ B1INV[1--16] DS3_TPLCP_RAI_ SWENB[1--16] DS3_TPLCP_RAI_ DINS[1--16] Transmit PLCP POI Bit 7 Invert Control. 1 = Invert bit 7 of all POI bytes of a PLCP frame. 0 = Send valid POI B7 bits. Transmit PLCP B1 Byte Invert Control. 1 = Invert B1 byte of a PLCP frame. 0 = Send valid B1 values. Transmit PLCP RAI Insert. Control bit, when set, forces the DS3_PLCP_RAI_DINS value to be inserted into the outgoing G1[3] bit; otherwise, sends the hardware value. Transmit PLCP RAI Insert Data Value for All Channels. This bit when enabled will be inserted into the G1[3] bit. 12 0 11 0 10 0 9 8 0 0 DS3_TPLCP_FEBE_ Transmit PLCP FEBE Insert. Control bit, when set, forces SWENB[1--16] the DS3_TLCP_FEBE_DINS[3:0] (Table 581) value to be inserted into the outgoing G1[7:4] nibble; otherwise, sends the hardware value. -- DS3_TXCHID_TO_ TSMAPPING [1--16][1:0][3:0] Reserved. This parameter maps time-slot-based received alarms to channel-based transmit far-end alarms. Valid DS3 block slice values are [A--B] selected through bits [5:4], where 11 = A and 10 = B; valid time-slot values are 0 to 11 and are selected through bits [3:0]. Invalid values disable the mapping and force all error conditions to their inactive state. 7:6 5:0 00 0x00 Agere Systems Inc. 547 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Descriptions (continued) Table 579. DS3_TDS3CTL_CHD[1--16], Transmit DS3 (R/W) Address 0x53C0-- 0x53CF Bit 15:14 Name DS3_TDS3_ AIS[1--16], DS3_TDS3_ IDLE[1--16] DS3_TDS3_ FINV[1--16] DS3_TDS3_ MINV[1--16] DS3_TDS3_ PINV[1--16] DS3_TDS3_ CPINV[1--16] DS3_TDS3_ FEBEINS[1--16] Function Transmit DS3 Data Type. 00 or 11 = Data engine data. 01 = Idle. 10 = AIS. Transmit DS3 F-Bit Invert. Control bit, when set, forces an error in the F-bit sequence (1000); otherwise, insert a valid sequence (1001) into the F1--F4 framing bits, respectively. Transmit DS3 M-Bit Invert. Control bit, when set, forces an error in the M-bit sequence (011); otherwise, insert a valid sequence (010) into the M1--M3 bits, respectively. Transmit DS3 P1-Bit, P2-Bit Control. This bit, when set, inverts the P1 and P2 bits in the associated DS3 frame. Transmit DS3 CP-Bit Control. Control bit, when set, the computed CP-bit value is inverted (C31 = C32 = C33); otherwise, insert a valid CP-bit value. Transmit DS3 FEBE Error Insert. Control bit, when set, forces the FEBE bits (C41 = C42 = C43) to 000 respectively (error condition); otherwise, insert FEBE bits under hardware control. C41 = C42 = C43 = 1, if no errors are detected in the received M or F bits or indicated by the received CP bits; otherwise, set the FEBE bits to 000. Reserved. Transmit DS3 X-Bit Control. X-bit value (1 = error-free, 0 = error condition). 0 0 Reset Default 0 13 12 0 11 10 9 0 8 7 6 -- DS3_TDS3_ XDINS[1--16] 0 0 0 DS3_TDS3_TFEAC_ Transmit DS3 C-Bit Control. Control bit, when set to 0, INS[1--16] the C13-bit is set to 1; otherwise, set the C13 bits as a 16-bit repeating sequence in the form of 0x5x4x3_x2x1x00_1111_1111 with the right-most bit sent first. Bits x5 to x0 are programmable from register DS3_TFEAC_CODE. DS3_TDS3_TFEAC_ Value for FEAC Programmable Bits. Bit 5 is transmitted CODE[1--16][5:0] first. 5:0 0 548 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Descriptions (continued) Transmit PRBS Control Signals Table 580. DS3_TXPRBSCTL_[1--2], Transmit PRBS Control (R/W) Address 0x53F0-- 0x53F1 Bit 15:10 9 8 7 6 Name -- DS3_TPRBS_ 1BERRINS[1--2] Reserved. Error Insert Bit. When a 0-to-1 transition is detected, one error is injected into the PRBS sequence. Function Reset Default 0x00 0 0 0 0 DS3_TPRBS_15or20 Control bit, when set, inserts 220 - 1 QRSS pattern; [1--2] otherwise, insert 215 - 1 PRBS pattern. DS3_TPRBS_INV [1--2] Control bit, when set, inverts the PRBS pattern before insertion into the DS3 or PLCP frames. DS3_TPRBS_DS3or Control bit, when set, inserts into the PLCP ATM cell PLCP[1--2] payload bytes; otherwise, it causes the PRBS pattern to be inserted into the DS3 frame. DS3_TPRBS_CHID_ PRBS Channel ID Insert Control Function. Valid values INS[1--2][5:0] are 0 to 15; invalid values disable the PRBS insert function. 5:0 0x3F Transmit FEBE Insert Value Table 581. DS3_TXFEBEDINS, Transmit Blank Request Counter Reset (R/W) Address 0x53F2 Bit 15 14:4 3:0 Name Function Reset Default 0 0x000 0x0 DS3_TBRCNT_RST Control bit, when set, resets internal blank request counter. -- Reserved. DS3_TPLCP_FEBE_ Transmit PLCP FEBE Insert Data Value for All DINS[3:0] Channels. Transmit FIFO Control Table 582. DS3_TXFIFO, Transmit FIFO Min/Max Thresholds (R/W) Address 0x53F3 Bit 15 14 13:8 7:6 5:0 Name -- -- DS3_TFIFO_MIN [5:0] -- DS3_TFIFO_MAX [5:0] Function Selects TFIFO_OVF_UNFL_SEL alarm. Reserved. Data is not read out of the FIFO until data has accumulated to at least the lower threshold. Reserved. Blank requests are generated for the associated channel when the FIFO fill has reached or exceeded the max value. Reset Default 0 0 0x03 00 0x2A Agere Systems Inc. 549 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions Global Registers Table 583. DS3E3_VERR, Version Control (RO) Address 0x5000 Bit 15:8 7:0 Name -- DS3E3_VER[7:0] Reserved. Block Version. Indicates version number of this block. Function Reset Default 0x00 0x00 Table 584. E3_SCRATCHR, Scratch Register (R/W) Address 0x5001 Bit 15:0 Name E3_SCRATCH [15:0] Function Read/write register with no other internal E3 connections. Reset Default 0x0000 Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event Registers (R/W) Address 0x5002 Bit 15 Name E3_COR_COWN Function Control bit, when set (0) all delta and event registers function in the clear-on-write (COW) mode; otherwise, they function in the clear-on-read (COR) mode. Reserved. Monitor receive output signals (active-high) E3_TM_DATA <= ("00000000000000", E3_RXSYNC, E3_RXPM_A, E3_RXEOP_A, E3_RXPM_B, E3_RXEOP_B, E3_RXPM_C, E3_RXEOP_C, E3_RXPM_D, E3_RXEOP_D, E3_RXDATA_A, E3_RXDATA_B, E3_RXDATA_C, E3_RXDATA_D); 0x0 Reset Default 0 14:12 11 -- SEQ_RX 550 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/ Event Registers (R/W) (continued) Address 0x5002 Bit 10 Name TM_RX Function Control inputs into the receive direction (active-high) if (TM_RX = 1) the PT_RXSYNC_i <= TM_DATA(40); PT_RXJ1_A_i <= TM_DATA(39); PT_RXPM_A_i <= TM_DATA(38); PT_RXJ1_B_i <= TM_DATA(37); PT_RXPM_B_i <= TM_DATA(36); PT_RXJ1_C_i <= TM_DATA(35); PT_RXPM_C_i <= TM_DATA(34); PT_RXJ1_D_i <= TM_DATA(33); PT_RXPM_D_i <= TM_DATA(32); PT_RXDATA_A_i <= TM_DATA(31:24); PT_RXDATA_B_i <= TM_DATA(23:16); PT_RXDATA_C_i <= TM_DATA(15:8); PT_RXDATA_D_i <= TM_DATA(7:0); else PT_RXSYNC_i <= PT_RXSYNC; PT_RXJ1_A_i <= PT_RXJ1_A; PT_RXPM_A_i <= PT_RXPM_A; PT_RXDATA_A_i <= PT_RXDATA_A; PT_RXJ1_B_i <= PT_RXJ1_B; PT_RXPM_B_i <= PT_RXPM_B; PT_RXDATA_B_i <= PT_RXDATA_B; PT_RXJ1_C_i <= PT_RXJ1_C; PT_RXPM_C_i <= PT_RXPM_C; PT_RXDATA_C_i <= PT_RXDATA_C; PT_RXJ1_D_i <= PT_RXJ1_D; PT_RXPM_D_i <= PT_RXPM_D; PT_RXDATA_D_i <= PT_RXDATA_D; end if; Monitor transmit output signals (active-high) E3_TM_DATA <= (00, PT_TXBR, PT_TXBR_CID, E3_TXBR, E3_TXBR_CID, E3_TXPM, E3_TXCID, E3_TXDATA); Reset Default 0x0 9 PT_TX 0x0 Agere Systems Inc. 551 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/ Event Registers (R/W) (continued) Address 0x5002 Bit 8 Name TM_TX Function Control inputs into the transmit direction (active-high) E3_TM_DATA <= ("00000000000000000", "00000000000000000", "00000000000000", E3_TXBR_CID, E3_TXBR); if (TM_TX = '1') then DE_TXDATA_i <= TM_DATA(31 0); DE_TXPM_i <= TM_DATA(32); DE_TXDVLD_i <= TM_DATA(33); DE_TXEOP_i <= TM_DATA(37:34); DE_TXCID_i <= TM_DATA(43: 38); else DE_TXDATA_i <= DE_TXDATA; DE_TXPM_i <= DE_TXPM; DE_TXDVLD_i <= DE_TXDVLD; DE_TXEOP_i <= DE_TXEOP; DE_TXCID_i <= DE_TXCID; end if; Reserved. GPO_ADDRESS can be 0x00 to 0x2B. Configure the GPO_ADDRESS to this register and this address is passed to E3_GPO_MUX block to select one of GPO outputs when it is selected to read. 000000 Reset Default 0x0 7:6 5:0 -- GPOSEL[5:0] 552 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Interface A Delta/Event Registers Table 586. E3FRMD_A, E3 Out-of-Frame Delta (COR/COW) Address 0x5003 Bit 15:12 11:0 Name -- E3_OOFD_ A[12--1] Reserved. Each time the E3_OOFD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 587. E3LOFD_A, E3 Loss-of-Frame Delta (COR/COW) Address 0x5004 Bit 15:12 11:0 Name -- E3_LOFD_ A[12--1] Reserved. Each time the E3_LOFD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 588. E3_TR_MISMATCHD_A, E3 Delta (COR/COW) Address 0x5005 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF E3_TR_MISMATCHD Each time the state bit changes state (0 to 1 or 1 to 0), the _A[12--1] delta bit is set. Table 589. E3AISD_A, E3 AIS Detection Delta (COR/COW) Address 0x5006 Bit 15:12 11:0 Name -- E3_AISPAT_ DETD_A[12--1] Reserved. Each time the E3_AISPAT_DETD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Agere Systems Inc. 553 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 590. E3_D_A, E3 Delta (COR/COW) Address 0x5007 Bit 15:4 3:0 Name -- E3_PLCP_ZF_ DMON[x]D Reserved. Each time an associated state value changes, the composite delta bit is set. Function Reset Default 0x0 Table 591. E3_MA_SSMD_A, E3 Delta (COR/COW) Address 0x5008 Bit 15:12 11:0 Name -- E3_MA_SSMD_ A[12--1] Reserved. Each time the E3_MA_SSMD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 592. E3_D_A, E3 Delta (COR/COW) Address 0x5009 Bit 15:12 11:0 Name -- E3_G751_RAI_ DETD_A[12--1] E3_G832_MA_RDI_ DETD_A[12--1] Reserved. Each time the state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 593. E3_MA_PTD_A, E3 Delta (COR/COW) Address 0x500A Bit 15:12 11:0 Name -- E3_MA_PTD_ A[12--1] Reserved. Each time the E3_MA_PTD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 554 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 594. E3_PLCP_LOFD_A, E3 Delta (COR/COW) Address 0x500B Bit 15:12 11:0 Name -- E3_PLCP_LOFD_ A[12--1] Reserved. Each time the E3_PLCP_LOFD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 595. E3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW) Address 0x500C Bit 15:12 11:0 Name -- E3_PLCP_OOFD_ A[12--1] Reserved. Each time the E3_PLCP_OOFD_A[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 596. E3_PLCPASD_A, PLCP (G1[3]) Monitoring Delta (COR/COW) Address 0x500D Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 E3_PLCP_G1_ASD_ Each time the E3_PLCP_G1_ASD_A[12--1] state bit A[12--1] changes state (0 to 1 or 1 to 0), the delta bit is set. Agere Systems Inc. 555 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Interface B Delta/Event Registers Table 597. E3FRMD_B, E3 Out-of-Frame Delta (COR/COW) Address 0x500F Bit 15:12 11:0 Name -- E3_OOFD_ B[12--1] Reserved. Each time the E3_OOFD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 598. E3LOFD_B, E3 Loss-of-Frame Delta (COR/COW) Address 0x5010 Bit 15:12 11:0 Name -- E3_LOFD_ B[12--1] Reserved. Each time the E3_LOFD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 599. E3_TR_MISMATCHD_B, E3 Delta (COR/COW) Address 0x5011 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF E3_TR_MISMATCHD Each time the state bit changes state (0 to 1 or 1 to 0), the _B[12--1] delta bit is set. Table 600. E3AISD_B, E3 AIS Detection Delta (COR/COW) Address 0x5012 Bit 15:12 11:0 Name -- E3_AISPAT_ DETD_B[12--1] Reserved. Each time the E3_AISPAT_DETD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 556 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 601. E3_D_B, E3 Delta (COR/COW) Address 0x5013 Bit 15:4 3:0 Name -- E3_PLCP_ZF_ DMOND[A--B] Reserved. Each time an associated state value changes, the composite delta bit is set. Function Reset Default 0x000 Table 602. E3_MA_SSMD_B, E3 Delta (COR/COW) Address 0x5014 Bit 15:12 11:0 Name -- E3_MA_SSMD_ B[12--1] Reserved. Each time the E3_MA_SSMD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Table 603. E3_D_B, E3 Delta (COR/COW) Address 0x5015 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 E3_G751_RAI_DET Each time the state bit changes state (0 to 1 or 1 to 0), the D_B[12--1] delta bit is set. E3_G832_MA_RDI_ DETD_B[12--1] Table 604. E3_MA_PTD_B, E3 Delta (COR/COW) Address 0x5016 Bit 15:12 11:0 Name -- E3_MA_PTD_ B[12--1] Reserved. Each time the E3_MA_PTD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0x000 Agere Systems Inc. 557 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 605. E3_PLCP_LOFD_B, E3 Delta (COR/COW) Address 0x5017 Bit 15:12 11:0 Name -- E3_PLCP_LOFD_ B[12--1] Reserved. Each time the E3_PLCP_LOFD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 606. E3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW) Address 0x5018 Bit 15:12 11:0 Name -- E3_PLCP_OOFD_ B[12--1] Reserved. Each time the E3_PLCP_OOFD_B[12--1] state bit changes state (0 to 1 or 1 to 0), the delta bit is set. Function Reset Default 0x0 0xFFF Table 607. E3_PLCP_G1_ASD_B, PLCP (G1[3]) Monitoring Delta (COR/COW) Address 0x5019 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 E3_PLCP_G1_ASD_ Each time the E3_PLCP_G1_ASD_B[12--1] state bit B[12--1] changes state (0 to 1 or 1 to 0), the delta bit is set. 558 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Interface A Mask Registers Table 608. E3FRMM_A, E3 Out-of-Frame Mask (R/W) Address 0x5039 Bit 15:12 11:0 Name -- E3_OOFM_ A[12--1] Reserved. E3 Out-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 609. E3LOFM_A, E3 Loss-of-Frame Mask (R/W) Address 0x503A Bit 15:12 11:0 Name -- E3_LOFM_ A[12--1] Reserved. E3 Loss-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 610. E3SEFM_A, E3 Severely Errored Frame (SEF) Mask (R/W) Address 0x503B Bit 15:12 11:0 Name -- E3_SEFM_ A[12--1] Reserved. E3 Severely Errored Frame (SEF) Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 611. E3AISM_A, E3 AIS Detection Mask (R/W) Address 0x503C Bit 15:12 11:0 Name -- E3_AISPAT_ DETM_A[12--1] Reserved. E3 AIS Detection Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Agere Systems Inc. 559 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 612. E3_M_A, E3 Mask (R/W) Address 0x503D Bit 15:4 3:0 Name -- E3_PLCP_ZF_ DMONM[A--B] Reserved. Associated Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 Table 613. E3MAM_A, E3 MA-Bit Detect Mask (R/W) Address 0x503E Bit 15:12 11:0 Name -- E3_MA_SSMM_ A[12--1] Reserved. E3 MA-Bit Detect Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 614. E3_M_A, E3 Detect Mask (R/W) Address 0x503F Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF 0xFFF E3_G751_RAI_DET E3 G751 RAI Detect Mask. When set high, the delta will M_A[12--1] not contribute to the interrupt signal. E3_G832_MA_RDI_ E3 G832 MA RDI Detect Mask. When set high, the delta DETM_A[12--1] will not contribute to the interrupt signal. Table 615. E3_MA_PTM_A, E3 Mask (R/W) Address 0x5040 Bit 15:12 11:0 Name -- E3_MA_PTM_ A[12--1] Reserved. Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF 560 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 616. E3_PLCP_LOFM_A, E3 Mask (R/W) Address 0x5041 Bit 15:12 11:0 Name -- E3_PLCP_LOFM_ A[12--1] Reserved. Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 617. E3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W) Address 0x5042 Bit 15:12 11:0 Name -- E3_PLCP_OOFM_ A[12--1] Reserved. PLCP Out-of-Frame Monitor Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 618. DS3_PLCPASM_A, PLCP (G1[3]) Monitoring Mask (R/W) Address 0x5043 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF E3_PLCP_G1_ASM Mask. When set high, the delta will not contribute to the _A[12--1] interrupt signal. Agere Systems Inc. 561 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Interface B Mask Registers Table 619. E3FRMM_B, E3 Out-of-Frame Mask (R/W) Address 0x5045 Bit 15:12 11:0 Name -- E3_OOFM_ B[12--1] Reserved. E3 Out-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 620. E3LOFM_B, E3 Loss-of-Frame Mask (R/W) Address 0x5046 Bit 15:12 11:0 Name -- E3_LOFM_ B[12--1] Reserved. E3 Loss-of-Frame Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 621. E3SEFM_B, E3 Severely Errored Frame (SEF) Mask (R/W) Address 0x5047 Bit 15:12 11:0 Name -- E3_SEFM_ B[12--1] Reserved. E3 Severely Errored Frame (SEF) Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 622. E3AISM_B, E3 AIS Detection Mask (R/W) Address 0x5048 Bit 15:12 11:0 Name -- E3_AISPAT_ DETM_B[12--1] Reserved. E3 AIS Detection Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF 562 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 623. E3_M_B, E3 Mask (R/W) Address 0x5049 Bit 15:4 3:0 Name -- E3_PLCP_ZF_ DMONM[A--B] Reserved. Associated Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 Table 624. E3MAM_B, E3 MA-Bit Detect Mask (R/W) Address 0x504A Bit 15:12 11:0 Name -- E3_MA_SSMM_ B[12--1] Reserved. E3 MA-Bit Detect Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 625. E3_M_B, E3 Detect Mask (R/W) Address 0x504B Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF 0xFFF E3_G751_RAI_DET E3 G751 RAI Detect Mask. When set high, the delta will M_B[12--1] not contribute to the interrupt signal. E3_G832_MA_RDI_ E3 G832 MA RDI Detect Mask. When set high, the delta DETM_B[12--1] will not contribute to the interrupt signal. Table 626. E3_MA_PTM_B, E3 Mask (R/W) Address 0x504C Bit 15:12 11:0 Name -- E3_MA_PTM_ B[12--1] Reserved. Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Agere Systems Inc. 563 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 627. E3_PLCP_LOFM_B, E3 Mask (R/W) Address 0x504D Bit 15:12 11:0 Name -- E3_PLCP_LOFM_ B[12--1] Reserved. Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 628. E3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W) Address 0x504E Bit 15:12 11:0 Name -- E3_PLCP_OOFM_ B[12--1] Reserved. PLCP Out-of-Frame Monitor Mask. When set high, the delta will not contribute to the interrupt signal. Function Reset Default 0x0 0xFFF Table 629. E3_PLCPASM_B, PLCP (G1[3]) Monitoring Mask (R/W) Address 0x504F Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0xFFF E3_PLCP_G1_ASM Mask. When set high, the delta will not contribute to the _B[12--1] interrupt signal. 564 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Interface A State Registers Table 630. E3FRM_A, E3 Out-of-Frame State (RO) Address 0x506F Bit 15:12 11:0 Name -- E3_OOF_A[12--1] Reserved. E3 Out-of-Frame State. State bit indicating on a per slice and time-slot basis if the E3 framer is in frame. 0 = in frame, 1 = out of frame. Function Reset Default 0x0 0xFFF Table 631. E3LOF_A, E3 Loss-of-Frame State (RO) Address 0x5070 Bit 15:12 11:0 Name -- E3_LOF_A[12--1] Reserved. E3 Loss-of-Frame State. State bit is set (1) when the E3 framer is in the out-of-frame state for 28 continuous frame periods (approximately 3 ms). Function Reset Default 0x0 0xFFF Table 632. E3SEF_A, E3 Severely Errored Frame (SEF) (RO) Address 0x5071 Bit 15:12 11:0 Name -- E3_SEF_A[12--1] Reserved. A SEF defect is the occurrence of three or more F-bit errors in 16 consecutive F bits. A SEF is cleared when the signal is in-frame and there are less than 3 F-bit errors in 16 consecutive F bits. Function Reset Default 0x0 0xFFF Table 633. E3AIS_A, E3 AIS Detection (RO) Address 0x5072 Bit 15:12 11:0 Name -- E3_AISPAT_DET_ A[12--1] Reserved. AIS is declared if fewer than five pattern errors (1010) are received in each of two consecutive M-frames. AIS is cleared when at least 16 pattern errors are received in each of two consecutive M frames. Function Reset Default 0x0 0x000 Agere Systems Inc. 565 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 634. Address 0x5075 E3E3_A, E3 Detect (RO) Name -- Reserved. Function Reset Default 0x0 0x000 Bit 15:12 11:0 E3_G751_RAI_DET E3_G751_RAI_DET. Monitor with a programmable _A[12--1] continuous N times detect monitor (E3_G751_RAI_CNTD[3:0]). E3_G832_MA_RDI_ E3_G832_MA_RDI_DET. Monitor with a programmable DET_A[12--1] continuous N times detect monitor (E3_G832_MA_RDI_CNTD[3:0]). Table 635. E3_PLCP_LOF_A, E3 PLCP Loss-of-Frame Monitor (RO) Address 0x5077 Bit 15:12 11:0 Name -- E3_PLCP_LOF_ A[12--1] Reserved. E3_PLCP_LOF. The state bit is set when the associated E3_PLCP_OOF state bit is active (1) for a programmable number of frames (125 s, E3_PLCP_LOF_SETCNT[3:0]). The state bit is cleared when the associated E3_PLCP_OOF state bit is inactive (0) for a programmable number of frames (125 s, E3_PLCP_LOF_CLRCNT[3:0]). Function Reset Default 0x0 0xFFF Table 636. E3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO) Address 0x5078 Bit 15:12 11:0 Name -- E3_PLCP_OOF_ A[12--1] Reserved. When the A1A2 pattern is detected in two consecutive rows, the PLCP framer is considered in-frame. The PLCP framer will transition to the OOF state when five consecutive A1A2 mismatches are detected or five consecutive POI mismatches occur. E3_PLCP_OOF = 0, when the pattern has been detected for two consecutive rows, along with two valid POI octets. E3_PLCP_OOF= 1, when errors are detected in both octets in a single row, or when errors are detected in two consecutive POI octets. Function Reset Default 0x0 0xFFF 566 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 637. E3_PLCPAS_A, PLCP (G1[3]) Monitoring (RO) Address 0x5079 Bit 15:12 11:0 Name -- E3_PLCP_G1_AS _A[12--1] Reserved. E3_PLCP_G1_AS. When a programmable CNTD (E3_PLCP_G1_AS_CNTD[3:0]) change is detected in the G1 - AS bit, this value is updated. Function Reset Default 0x0 0x000 Table 638. E3SSMCODE_A[1--6], E3 (RO) Address 0x507B -- 0x5080 Bit 15:14 Name -- Reserved. Function Reset Default 00 0x0000 13:12 E3_MA_SSM_CODE State value of the received SSM code in framing and non_A[1--12][3] framing mode. This register is updated each time a CNTD value is detected (E3_MA_SSM_CNTD[3:0]). Each time 5:3, E3_MA_SSM_CODE the multiframe indicator reaches 11 the received 4-bit code 11:9 _A[1--12][2:0] is checked against the validated value for a consistent change. In nonframing mode, bit 0 contains the only valid value. 2:0, 8:6 E3_MA_PT_CODE_ State value for the payload type registers in the MA byte of A[1--12][2:0] an E3 G.832 frame. This byte is monitored with a programmable CNTD monitor (E3_MA_PT_CNTD[3:0]). Agere Systems Inc. 567 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Interface B State Registers Table 639. E3FRM_B, E3 Out-of-Frame State (RO) Address 0x5082 Bit 15:12 11:0 Name -- E3_OOF_B[12--1] Reserved. E3 Out-of-Frame State. State bit indicating on a per slice and time-slot basis if the E3 framer is in frame. 0 = in frame, 1 = out of frame. Function Reset Default 0x0 0xFFF Table 640. E3LOF_B, E3 Loss-of-Frame State (RO) Address 0x5083 Bit 15:12 11:0 Name -- E3_LOF_B[12--1] Reserved. E3 Loss-of-Frame State. State bit is set (1) when the E3 framer is in the out-of-frame state for 28 continuous frame periods (approximately 3 ms). Function Reset Default 0x0 0xFFF Table 641. E3SEF_B, E3 Severely Errored Frame (SEF) (RO) Address 0x5084 Bit 15:12 11:0 Name -- E3_SEF_B[12--1] Reserved. A SEF defect is the occurrence of three or more F-bit errors in 16 consecutive F bits. A SEF is cleared when the signal is in-frame and there are less than 3 F-bit errors in 16 consecutive F bits. Function Reset Default 0x0 0xFFF Table 642. E3AIS_B, E3 AIS Detection (RO) Address 0x5085 Bit 15:12 11:0 Name -- E3_AISPAT_DET_ B[12--1] Reserved. AIS is declared if fewer than five pattern errors (1010) are received in each of two consecutive M frames. AIS is cleared when at least 16 pattern errors are received in each of two consecutive M frames. Function Reset Default 0x0 0x000 568 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 643. E3_B, E3 Detect (RO) Address 0x5088 Bit 15:12 11:0 Name -- Reserved. Function Reset Default 0x0 0x000 E3_G751_RAI_DET E3_G751_RAI_DET. Monitor with a programmable _B[12--1] continuous N times detect monitor (E3_G751_RAI_CNTD[3:0]). E3_G832_MA_RDI_ E3_G832_MA_RDI_DET. Monitor with a programmable DET_B[12--1] continuous N times detect monitor (E3_G832_MA_RDI_CNTD[3:0]). Table 644. E3_PLCP_LOF_B, E3 PLCP Loss-of-Frame Monitor (RO) Address 0x508A Bit 15:12 11:0 Name -- E3_PLCP_LOF_ B[12--1] Reserved. E3_PLCP_LOF. The state bit is set when the associated E3_PLCP_OOF state bit is active (1) for a programmable number of frames (125 s, E3_PLCP_LOF_SETCNT[3:0]). The state bit is cleared when the associated E3_PLCP_OOF state bit is inactive (0) for a programmable number of frames (125 s, E3_PLCP_LOF_CLRCNT[3:0]). Function Reset Default 0x0 0xFFF Table 645. E3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO) Address 0x508B Bit 15:12 11:0 Name -- E3_PLCP_OOF_ B[12--1] Reserved. When the A1A2 pattern is detected in two consecutive rows, the PLCP framer is considered in-frame. The PLCP framer will transition to the OOF state when five consecutive A1A2 mismatches are detected or five consecutive POI mismatches occur. E3_PLCP_OOF = 0, when the pattern has been detected for two consecutive rows, along with two valid POI octets. E3_PLCP_OOF= 1, when errors are detected in both octets in a single row, or when errors are detected in two consecutive POI octets. Function Reset Default 0x0 0xFFF Agere Systems Inc. 569 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 646. E3_PLCPAS_B, PLCP (G1[3]) Monitoring (RO) Address 0x508C Bit 15:12 11:0 Name -- E3_PLCP_G1_AS _B[12--1] Reserved. E3_PLCP_G1_AS. When a programmable CNTD (E3_PLCP_G1_AS_CNTD[3:0]) change is detected in the G1 - AS bit, this value is updated. Function Reset Default 0x0 0x000 Table 647. E3SSMCODE_B[1--6], E3 (RO) Address 0x508E -- 0x5093 Bit 15:14 11:0 Name -- Reserved. Function Reset Default 0x0 0x0000 E3_MA_SSM_CODE State value of the received SSM code in framing and non_B[1--12][3] framing mode. This register is updated each time a CNTD 13:12 value is detected (E3_MA_SSM_CNTD[3:0]). Each time 5:3, E3_MA_SSM_CODE the multiframe indicator reaches 11, the received 4-bit code 11:9 _B[1--12][2:0] is checked against the validated value for a consistent change. In nonframing mode, bit 0 contains the only valid value. 2:0, 8:6 E3_MA_PT_CODE_ State value for the payload type registers in the MA byte of B[1--12][2:0] an E3 G.832 frame. This byte is monitored with a programmable CNTD monitor (E3_MA_PT_CNTD[3:0]). 570 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Receive Interface A Control Registers Table 648. E3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) Address 0x50BB Bit 15:12 11:0 Name -- E3_RE3PLCP_ A[6--1][1:0] Reserved. Receive Mode Control E3 Mode. 00 = no mapping, 01 = G.832 frame, 10 = G.751 frame, 11 = G.751/PLCP frame. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. Function Reset Default 0x0 0x000 Table 649. E3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W) Address 0x50BC Bit 15:14 Name -- Reserved. Function Reset Default 00 00 0x000 13:12 E3_RPRBS23_A[1:0] Control bit, when set, generates a (223 - 1) PRBS pattern; otherwise, follow the RPRBS_15or20 control bit. 11:0 E3_RE3PLCP_ A[12--7][1:0] Receive Mode Control E3 Mode. 00 = no mapping, 01 = G.832 frame, 10 = G.751 frame, 11 = G.751/PLCP frame. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. Table 650. RDS3E3_A, Receive Mode Control (R/W) Address 0x50BE Bit 15:12 11:0 Name E3_PLCP_ZF_ TSSEL_A[3:0] Function Control register, selects the time slot for Z1--Z3, F1 monitoring in the E3 PLCP frame. Reset Default 0xF 0x000 RDS3orE3_A[12--1] 0 = DS3 mode. 1 = E3 mode. Agere Systems Inc. 571 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Receive Interface B Control Registers Table 651. E3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W) Address 0x50BF Bit 15:12 11:0 Name -- E3_RE3PLCP_ B[6--1][1:0] Reserved. Receive Mode Control E3 Mode. 00 = no mapping, 01 = G.832 frame, 10 = G.751 frame, 11 = G.751/PLCP frame. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. Function Reset Default 0x0 0x000 Table 652. E3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W) Address 0x50C0 Bit 15:14 Name -- Reserved. Function Reset Default 00 00 0x000 13:12 E3_RPRBS23_B[1:0] Control bit, when set, generates a (223 - 1) PRBS pattern; otherwise, follow the RPRBS_15or20 control bit. 11:0 E3_RE3PLCP_ B[12--7][1:0] Receive Mode Control E3 Mode. 00 = no mapping, 01 = G.832 frame, 10 = G.751 frame, 11 = G.751/PLCP frame. See Table 560, DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) on page 540 and Table 565, DS3_RXPRBS_B, Receive PRBS (R/W) on page 542. Table 653. RDS3E3_B, Receive Mode Control Address 0x50C2 Bit 15:12 11:0 Name E3_PLCP_ZF_ TSSEL_B[3:0] Function Control register, selects the time slot for Z1--Z3, F1 monitoring in the E3 PLCP frame. Reset Default 0xF 0x000 RDS3orE3_B[12--1] 0 = DS3 mode. 1 = E3 mode. 572 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Receive Common Parameters (per Block) Table 654. E3PROV_1, E3 Provisioning Parameters (Per Block) (R/W) Address 0x50CB Bit 15:12 11 Name E3_G751_RAI_DET_ CNTD[3:0] E3_G751_10or14BIT_ FRMPAT Function Control register, continuous N times detect (CNTD) value for RAI bit in the G.751 E3 frame. Control bit, when set use 14 bits (11110100001100) in the determining the framing pattern for an E3 G.751 frame; otherwise, use 10 bits (1111010000) for the framing pattern. Control register, number of 125 s frames the OOF state bit must be inactive (1) before the LOF state bit is cleared. Valid for both G.751 and G.832 E3 frame formats. Reserved. Control register, number of 125 s frames the OOF state bit must be active (1) before the LOF state bit is cleared. Valid for both G.751 and G.832 E3 frame formats. Reset Default 4'h3 1'b0 10:6 E3_LOF_CLRCNT[4:0] 5'h18 5 4:0 -- E3_LOF_SETCNT[4:0] -- 5`h18 Table 655. E3PROV_2, E3 PLCP Provisioning Parameters (Per Block) (R/W) Address 0x50CC Bit Name Function Reset Default 4`h8 15:12 E3_G832_AIS_0CNT[3:0] Control register, number of zeros that must be detected in a G.832 E3 frame to declare or remove an AIS condition. 11 10:6 -- E3_PLCP_LOF_ CLRCNT[4:0] -- E3_PLCP_LOF_ SETCNT[4:0] Reserved. Control register, number of 125 s frames the OOF PLCP state bit must be inactive (1) before the LOF state bit is cleared. Valid for G.751 E3 frame formats. Reserved. Control register, number of 125 s frames the OOF PLCP state bit must be active (1) before the LOF state bit is cleared. Valid for G.751 E3 frame formats. -- 4`h18 5 4:0 -- 4`h18 Table 656. E3PROV_3, E3 AIS Provisioning Parameters (Per Block) (R/W) Address 0x50CD Bit Name Function Reset Default 4`h5 15:12 E3_G751_AIS_0CNT[3:0] Control register, number of 0s that must be detected in a G.751 E3 frame to declare or remove an AIS condition. 11:0 -- Reserved. -- Agere Systems Inc. 573 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 657. E3PROV_4, E3 Provisioning Parameters (Per Block) (R/W) Address 0x50CE Bit 15:12 Name E3_PLCP_G1_AS_ CNTD[3:0] Function Control register, number of consecutive N times detect values that must be detected to accept a new validated value. Valid values 0 to 15. Reset Default 4`h5 11:8 E3_PLCP_ZF_CNTD[3:0] Control register, number of consecutive N times detect values that must be detected to accept a new validated value. Valid values 0 to 15. -- E3_B1_BITBLK E3_PLCP_G1_ FEBE_BITBLK E3_PLCP_B1_BITBLK Reserved. Control bit, when set, forces the associated counter to count bit errors; otherwise, count block errors, one or more bit errors per frame equals one block error. 4`hA 7:3 2 1 0 -- 3`b111 Table 658. E3PROV_5, E3 Provisioning Parameters (Per Block) (R/W) Address 0x50CF Bit 15:12 11:8 7:4 3:0 Name -- Reserved. 1`h3 1`h3 1`h3 Function Reset Default E3_MA_SSM_CNTD[3:0] Control register; CNTD value for SSM, PT, and RDI bits E3_MA_PT_CNTD[3:0] in the MA byte of a G.832 E3 frame. Valid values are 0 to 15. E3_G832_MA_RDI_ CNTD[3:0] Table 659. E3_MA_MF_[A--B], E3 Provisioning Parameters Address Bit Name Function Reset Default -- E3_MA_MF_ENABLE_ [A--B][1--12] Control bit, when set, indicates MA[2:1] bits contain a multiframe that should be used in evaluating MA[0] bit; otherwise, extract MA[0] bit without using the multiframe indicator bits. 1`b0 0x50D0-- 15:12 0x50D1 0:11 574 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Receive E3 G.832 Trail Identifier Monitor Mode per Time Slot Table 660. E3_TR_NMODE_[A--B][1--2], (R/W) Address 0x50D4-- 0x50D7 Bit 15:12 0:11 Name -- E3_TR_MMODE_ [A--B][1--12][1:0] Reserved. E3 TR Monitor Mode. 00 = disabled, 01 = expected value, 10 = sustained change mode, 11 = capture mode. 0x000 Function Reset Default Receive E3 PLCP Z1--Z3, F1 Byte State Values Table 661. E3PLCP_MON[A--B][1--2], (RO) Address 0x50DC-- 0x50DF Bit 15:0 Name E3_PLCP_ [Z1, Z2, Z3, F1]_ DMON_[A--B][7:0] Function When a CNTD value change is detected, the validated value is stored. Reset Default 0x0000 Agere Systems Inc. 575 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Receive Interface A Counters Table 662. E3_MA_REI_ERRCNT_A[1--12], E3 MA REI Error Count (RO) Address 0x5100-- 0x510B Bit 15:14 13:0 Name -- E3_MA_ REI_ERRCNT_ A[1--12][13:0] Reserved. This counter increments each time an error is detected in the G.832 MA byte REI bit. This counter is disabled while E3_OOF = 1. Function Reset Default 00 0x0000 Table 663. E3_B1_ERRCNT_A[1--12], E3 B1 Error Counter (RO) Address 0x510C-- 0x5117 Bit 15:14 13:0 Name -- E3_B1_ERRCNT_ A[1--12][13:0] Reserved. This counter increments by one (block errors or 1 to 8 for bit errors) when an error is detected in the G.832 B1 byte. This counter saturates at its maximum value and is cleared by PMRST (pin D7). Function Reset Default 00 0x0000 Table 664. E3_RXPLCPB1ECNT_A[1--12], PLCP B1 Error Count (RO) Address 0x5160-- 0x516B Bit 15:0 Name E3_PLCP_ B1ERRCNT_ A[1--12][15:0] Function While the E3 PLCP framer is in the in-frame state, the number of bit errors between the incoming BIP-8 and the calculated BIP-8 value is accumulated in a 160-bit saturating counter. This counter saturates at its maximum value and is cleared by the PMRST signal. Reset Default 0x0000 Table 665. E3_PLCPFEBECNT_A[1--12], PLCP FEBE (G1[7:4]) Error Count (RO) Address 0x516C-- 0x5177 Bit 15:0 Name E3_PLCP_G1_ FEBE_ERRCNT_ A[1--12][15:0] Function While the PLCP framer is in the in-frame state the number of FEBE errors received (0--8) are accumulated in a 16-bit saturating counter. Bit or block counts can be accumulated in this counter. Values greater than eight are ignored. This counter is cleared by the PMRST signal. Reset Default 0x0000 576 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Receive Interface B Counters Table 666. E3_MA_REI_ERRCNT_B[1--12], E3 MA REI Error Count (RO) Address 0x5180-- 0x518B Bit 15:14 13:0 Name -- E3_MA_ REI_ERRCNT_ B[1--12][13:0] Reserved. This counter increments each time an error is detected in the G.832 MA byte REI bit. This counter is disabled while E3_OOF = 1. Function Reset Default 00 0x0000 Table 667. E3_B1_ERRCNT_B[1--12], E3 B1 Error Counter (RO) Address 0x518C-- 0x5197 Bit 15:14 13:0 Name -- E3_B1_ERRCNT_ B[1--12][13:0] Reserved. This counter increments by one (block errors or 1 to 8 for bit errors) when an error is detected in the G.832 B1 byte. This counter saturates at its maximum value and is cleared by PMRST. Function Reset Default 00 0x0000 Table 668. E3_RXPLCPB1ECNT_B[1--12], PLCP B1 Error Count (RO) Address 0x51C0-- 0x51CB Bit 15:0 Name E3_PLCP_ B1ERRCNT_ B[1--12][15:0] Function While the E3 PLCP framer is in the in-frame state, the number of bit errors between the incoming BIP-8 and the calculated BIP-8 value is accumulated in a 160-bit saturating counter. This counter saturates at its maximum value and is cleared by the PMRST signal. Reset Default 0x0000 Table 669. E3_PLCPFEBECNT_B[1--12], PLCP FEBE (G1[7:4]) Error Count (RO) Address 0x51CC-- 0x51D7 Bit 15:0 Name E3_PLCP_G1_ FEBE_ERRCNT_ B[1--12][15:0] Function While the PLCP framer is in the in-frame state, the number of FEBE errors received (0--8) are accumulated in a 16-bit saturating counter. Bit or block counts can be accumulated in this counter. Values greater than eight are ignored. This counter is cleared by the PMRST signal. Reset Default 0x0000 Agere Systems Inc. 577 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Transmit Control Signals (Channel Based 1--16) Table 670. E3_TE3PLCPCTL1_CHD[1--16], Transmit PLCP (R/W) Address 0x5300-- 0x530F Bit 15:14 Name E3_TE3PLCP [1--16][1:0] Function Transmit Mode Control Per Channel E3 Mode. 00 = No mapping. 01 = G.832 frame. 10 = G.751 frame. 11 = G.751/PLCP mapping. Transmit PLCP A2 Byte Invert Control. 1 = Invert all A2 bytes (0xD7) of a PLCP frame. 0 = Send valid A2 byte values (0x28). Transmit PLCP POI Bit 7 Invert Control. 1 = Invert bit 7 of all POI bytes of a PLCP frame. 0 = Send valid POI B7 bits. Transmit PLCP B1 Byte Invert Control. 1 = Invert B1 byte of a PLCP frame. 0 = Send valid B1 values. Reserved. Software data value for G1-AS bit per channel. Control bit, when 0 allows hardware control of the G1FEBE bit; otherwise, allows software value insertion. 0 = DS3 mode. 1 = E3 mode. Reserved. 0 0 0 0 00 0 0 0 Reset Default 00 13 TE3_PLCP_A2_ INV[1--16] TE3_PLCP_ POIB7INV[1--16] TE3_PLCP_ B1INV[1--16] -- TE3_PLCP_G1_ AS_DINS[1--16] TE3_PLCP_FEBE_ SWEN[1--16] TDS3orE3 -- 12 11 10 9 8 7 6:0 578 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Table 671. E3_TE3CTL_CHD[1--16], Transmit E3 (R/W) Address 0x53C0-- 0x53CF Bit 15 14 13 Name TE3_AISINS[1--16] Function Control bit, when set, forces an all 1s pattern in place of the selected E3 frame format. Reset Default 0 0 0 TE3_TR_INS[1--16] Control bit, when set, inserts the provisioned trail identifier into the G.832 E3 frame; otherwise, set this byte to zero. TE3_FA_INV[1--16] Control bit, when set, inverts the framing pattern in the G.751 or G.832 out-going frame; otherwise, inserts an error free value. TE3_RAI_ DINS[1--16] TE3_MA_RDI_ DINS[1--16] TE3_MA_REI_ ERRINS[1--16] TE3_B1INV[1--16] TE3_MA_PTY_ DINS[2:0] -- TE3_MA_ SSM[1--16][3:0] Data value for the RAI bit in the E3 G.751 frame. Data value for the MA byte RDI bit in the G.831 frame. Control bit, when set, forces an error into the MA byte REI bit in the G.832 frame. Control bit, when set, inverts the B1 value in the outgoing G.832 B1 byte (EM). Transmit E3 Payload Type Value. Reserved. In E3 mode, these bits are reserved. Software value for SSM 4-bit pattern. Bit 3 is transmitted with multiframe value 00. 12 11 10 9 8:6 5:4 3:0 0 0 0 0 000 0 0 Agere Systems Inc. 579 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Descriptions (continued) Transmit FEBE Insert Value Table 672. E3_TXFEBEDINS, Transmit PLCP FEBE Insert Data Value for All Channel (R/W) Address 0x53F2 Bit 15:8 7:4 3:0 Name -- TE3_PLCP_FEBE_ DINS[3:0] -- Reserved. Transmit PLCP FEBE Insert Data Value for All Channels. Reserved. Function Reset Default 0x000 0x0 Table 673. TXE3PLCP_P[1--3], Transmit G.751 E3 PLCP Z1--Z3, F1 Insert Control (R/W) Address 0x53F4 Bit 15:6 5:0 Name -- Reserved. 6`b3F Function Reset Default TE3_PLCP_ZF_CHID[5:0] Control value, selects the channel id to insert the Z1-- Z3, F1 values into the PLCP frame. Otherwise, inserts the default value. TE3_PLCP_Z1_DINS[7:0] E3 PLCP, Z1 Byte Software Value. TE3_PLCP_Z2_DINS[7:0] E3 PLCP, Z2 Byte Software Value. TE3_PLCP_Z3_DINS[7:0] E3 PLCP, Z3 Byte Software Value. TE3_PLCP_F1_DINS[7:0] E3 PLCP, F1 Byte Software Value. 0x53F5 0x53F6 15:8 7:0 15:8 7:0 0x0000 0x0000 Table 674. TXTRACE[1--16]_B[1--8], Transmit E3 G.832 Trail Trace (TR) Insert Registers (128 Locations) (R/W) Address 0x5400-- 0x547F Bit 15:0 Name TE3_TR_DINS [1--16][0--15][7:0] Function Trace identifier value for each channel. Reset Default 0 580 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Descriptions (continued) Address Space Accessed Through MPU_E3_SELP Signal Table 675. Receive E3 (G.832) Trail Trace Expected/Captured Value--Expected/Capture Format Same as Transmit Insert Format Address 0x5C00-- 0x5D7F (RO, R/W) 0x5D80-- 0x5EFF (RO) Bit 15:0 Name Function Reset Default 0x0000 15:0 E3_TR_EXP Mode = 00, Disable Function. [A--B][1--12][0--15][7:0] Mode = 01, Monitor for a Mismatch Between the Incoming Value and an Expected Value. A mismatch is declared if the received message differs from the E3_TR_CAP [A--B][1--12][0--15][7:0] expected message for ten consecutive messages. A mismatch clears when 4-out-of-5 received messages match the expected message. In this mode, the device frames on the most significant bit (MSB) of the first byte in the message being set to 1. Mode = 10, Monitor for a Sustained Change in the Message. A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message and the device starts checking for a sustained change from this new stable message. In this mode, no framing occurs and the E3_TR_EXP is RO. Mode = 11, Capture Incoming Data. 0x0000 Agere Systems Inc. 581 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map Table 676. DS3 Register Map Note: Shading denotes reserved bits. Addr 0x5000 0x5001 0x5002 Register Name DS3_VERR DS3_SCRATCHR DS3_CORW_ GPOSEL Type RO R/W R/W DS3_COR _COWN SEQ_RX TM_RX PT_TX DS3_SCRATCH[15:0] TM_TX GPOSEL[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3_VER[7:0] Interface A Delta/Event Registers 0x5003 0x5004 0x5005 0x5006 0x5007 0x5008 0x5009 0x500A 0x500B 0x500C 0x500D 0x500E DS3FRMD_A DS3LOFD_A DS3SEFD_A DS3AISD_A DS3IDLED_A DS3CBD_A DS3RAID_A DS3FEACALMD_A DS3FEACCTLD_A COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W DS3_OOFD_A[12--1] DS3_LOFD_A[12--1] DS3_SEFD_A[12--1] DS3_AISPAT_DETD_A[12--1] DS3_IDLEPAT_DETD_A[12--1] DS3_CBZ_DETD_A[12--1] DS3_RAI_DETD_A[12--1] DS3_RFEAC_RAID_A[12--1] DS3_RFEAC_CTLD_A[12--1] DS3_PLCP_OOFD_A[12--1] DS3_PLCP_G1_RAID_A[12--1] DS3_RPRBS_SYNC_ ERRD_A[1:0] DS3_PLCPOOFD_A COR/ W DS3_PLCPRAID_A DS3_ RXPRBSSYNCD_A COR/ W COR/ W 582 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface B Delta/Event Registers 0x500F 0x5010 0x5011 0x5012 0x5013 0x5014 0x5015 0x5016 0x5017 0x5018 0x5019 0x501A 0x501B-- 0x5032 DS3FRMD_B DS3LOFD_B DS3SEFD_B DS3AISD_B DS3IDLED_B DS3CBD_B DS3RAID_B DS3FEACALMD_B DS3FEACCTLD_B COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W DS3_OOFD_B[12--1] DS3_LOFD_B[12--1] DS3_SEFD_B[12--1] DS3_AISPAT_DETD_B[12--1] DS3_IDLEPAT_DETD_B[12--1] DS3_CBZ_DETD_B[12--1] DS3_RAI_DETD_B[12--1] DS3_RFEAC_RAID_B[12--1] DS3_RFEAC_CTLD_B[12--1] DS3_PLCP_OOFD_B[12--1] DS3_PLCP_G1_RAID_B[12--1] DS3_RPRBS_SYNC_ ERRD_B[1:0] DS3_PLCPOOFD_B COR/ W DS3_PLCPRAID_B DS3_ RXPRBSSYNCD_B -- COR/ W COR/ W COR/ W Transmit Direction FIFO Over/Underflow Registers 0x5033 0x5034-- 0x5035 DS3_TXFIFOERRE -- COR/ W -- DS3_TFIFO_OVR_UNFLE_[16--1] Transmit Direction EOP Marker Error 0x5036 0x5037-- 0x5038 DS3_ TXEOPERRER -- COR/ W -- DS3_TXEOPERRE[16--1] Agere Systems Inc. 583 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface A Mask Registers 0x5039 0x503A 0x503B 0x503C 0x503D 0x503E 0x503F 0x5040 0x5041 0x5042 0x5043 0x5044 DS3FRMM_A DS3LOFM_A DS3SEFM_A DS3AISM_A DS3IDLEM_A DS3CBM_A DS3RAIM_A DS3FEACALMM_A DS3FEACCTLM_A DS3_ PLCPOOFM_A DS3_PLCPRAIM_A DS3_ RXPRBSSYNCM_A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interface B Mask Registers 0x5045 0x5046 0x5047 0x5048 0x5049 0x504A 0x504B 0x504C 0x504D 0x504E 0x504F 0x5050 0x5051-- 0x5068 DS3FRMM_B DS3LOFM_B DS3SEFM_B DS3AISM_B DS3IDLEM_B DS3CBM_B DS3RAIM_B DS3FEACALMM_B DS3FEACCTLM_B DS3_ PLCPOOFM_B DS3_PLCPRAIM_B DS3_ RXPRBSSYNCM_B -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DS3_OOFM_B[12--1] DS3_LOFM_B[12--1] DS3_SEFM_B[12--1] DS3_AISPAT_DETM_B[12--1] DS3_IDLEPAT_DETM_B[12--1] DS3_CBZ_DETM_B[12--1] DS3_RAI_DETM_B[12--1] DS3_RFEAC_RAIM_B[12--1] DS3_RFEAC_CTLM_B[12--1] DS3_PLCP_OOFM_B[12--1] DS3_PLCP_G1_RAIM_B[12--1] DS3_RPRBS_SYNC_ ERRM_B[1:0] DS3_OOFM_A[12--1] DS3_LOFM_A[12--1] DS3_SEFM_A[12--1] DS3_AISPAT_DETM_A[12--1] DS3_IDLEPAT_DETM_A[12--1] DS3_CBZ_DETM_A[12--1] DS3_RAI_DETM_A[12--1] DS3_RFEAC_RAIM_A[12--1] DS3_RFEAC_CTLM_A[12--1] DS3_PLCP_OOFM_A[12--1] DS3_PLCP_G1_RAIM_A[12--1] DS3_RPRBS_SYNC_ ERRM_A[1:0] 584 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Transmit Direction FIFO Over/Underflow Mask 0x5069 0x506A-- 0x506B DS3_TXFIFOERRM -- R/W -- Transmit Direction EOP Marker Error 0x506C 0x506D-- 0x506E DS3_TXEOPERRM -- R/W -- Interface A State Registers 0x506F 0x5070 0x5071 0x5072 0x5073 0x5074 0x5075 0x5076 0x5077 0x5078 0x5079 0x507A 0x507B 0x507C 0x507D 0x507E 0x507F 0x5080 0x5081 DS3FRM_A DS3LOF_A DS3SEF_A DS3AIS_A DS3IDLE_A DS3CB_A DS3RAI_A DS3FEACALM_A DS3FEACCTL_A DS3_PLCPOOF_A DS3_PLCPRAI_A DS3_ RXPRBSSYNC_A DS3FEACCODE_A1 DS3FEACCODE_A2 DS3FEACCODE_A3 DS3FEACCODE_A4 DS3FEACCODE_A5 DS3FEACCODE_A6 DS3_RXPRBSERR CNT_A RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO DS3_RPRBS_ERRCNT_A[2][7:0] DS3_RFEAC_CODE_A[2][5:0] DS3_RFEAC_CODE_A[4][5:0] DS3_RFEAC_CODE_A[6][5:0] DS3_RFEAC_CODE_A[8][5:0] DS3_RFEAC_CODE_A[10][5:0] DS3_RFEAC_CODE_A[12][5:0] DS3_OOF_A[12--1] DS3_LOF_A[12--1] DS3_SEF_A[12--1] DS3_AISPAT_DET_A[12--1] DS3_IDLEPAT_DET_A[12--1] DS3_CBZ_DET_A[12--1] DS3_RAI_DET[_A[12--1] DS3_RFEAC_RAI_A[12--1] DS3_RFEAC_CTL_A[12--1] DS3_PLCP_OOF_A[12--1] DS3_PLCP_G1_RAI_A[12--1] DS3_RPRBS_SYNC_ ERR_A[1:0] DS3_RFEAC_CODE_A[1][5:0] DS3_RFEAC_CODE_A[3][5:0] DS3_RFEAC_CODE_A[5][5:0] DS3_RFEAC_CODE_A[7][5:0] DS3_RFEAC_CODE_A[9][5:0] DS3_RFEAC_CODE_A[11][5:0] DS3_RPRBS_ERRCNT_A[1][7:0] DS3_TXEOPERRM[16--1] DS3_TFIFO_OVR_UNFLM[16--1] Agere Systems Inc. 585 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface B State Registers 0x5082 0x5083 0x5084 0x5085 0x5086 0x5087 0x5088 0x5089 0x508A 0x508B 0x508C 0x508D 0x508E 0x508F 0x5090 0x5091 0x5092 0x5093 0x5094 0x5095-- 0x50BA DS3FRM_B DS3LOF_B DS3SEF_B DS3AIS_B DS3IDLE_B DS3CB_B DS3RAI_B DS3FEACALM_B DS3FEACCTL_B DS3_PLCPOOF_B DS3_PLCPRAI_B DS3_RXPRBS_ SYNC_B DS3FEACCODE_B1 DS3FEACCODE_B2 DS3FEACCODE_B3 DS3FEACCODE_B4 DS3FEACCODE_B5 DS3FEACCODE_B6 DS3_RXPRBSERR CNT_B -- RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO -- DS3_RPRBS_ERRCNT_B[2][7:0] DS3_RFEAC_CODE_B[2][5:0] DS3_RFEAC_CODE_B[4][5:0] DS3_RFEAC_CODE_B[6][5:0] DS3_RFEAC_CODE_B[8][5:0] DS3_RFEAC_CODE_B[10][5:0] DS3_RFEAC_CODE_B[12][5:0] DS3_OOF_B[12--1] DS3_LOF_B[12--1] DS3_SEF_B[12--1] DS3_AISPAT_DET_B[12--1] DS3_IDLEPAT_DET_B[12--1] DS3_CBZ_DET_B[12--1] DS3_RAI_DET_B[12--1] DS3_RFEAC_RAI_B[12--1] DS3_RFEAC_CTL_B[12--1] DS3_PLCP_OOF_B[12--1] DS3_PLCP_G1_RAI_B[12--1] DS3_RPRBS_SYNC_ ERR_B[1:0] DS3_RFEAC_CODE_B[1][5:0] DS3_RFEAC_CODE_B[3][5:0] DS3_RFEAC_CODE_B[5][5:0] DS3_RFEAC_CODE_B[7][5:0] DS3_RFEAC_CODE_B[9][5:0] DS3_RFEAC_CODE_B[11][5:0] DS3_RPRBS_ERRCNT_B[1][7:0] 586 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Interface A Control Registers 0x50BB 0x50BC DS3_RXMODE_A_1 DS3_RXMODE_A_2 R/W DS3_OOF_ FMODE_A DS3_RDS3PLCP_A[6][1:0] DS3_RDS3PLCP_A[5][1:0] DS3_RDS3PLCP_A[4][1:0] DS3_RDS3PLCP_A[3][1:0] DS3_RDS3PLCP_A[2][1:0] DS3_RDS3PLCP_A[1][1:0] DS3_RDS3PLCP_A[11][1: 0] DS3_RDS3PLCP_A[10][1: DS3_RDS3PLCP_A[9][1:0] DS3_RDS3PLCP_A[8][1:0] DS3_RDS3PLCP_A[7][1:0] 0] R/W DS3_RPRBS_INV_A[1: DS3_ DS3_RDS3PLCP_A[12][1: 0] RPRBS 0] 23_ A[1:0] R/W -- DS3_RPRBS_TSSEL_A[2][3:0] 0x50BD 0x50BE DS3_RXPRBS_A -- DS3_RPRBS_TSSEL_A[1][3:0] DS3_RPRBS_DS3_PLCP_ DS3_RPRBS__15or20_A[ A[1:0] 1:0] DS3_PLCP_CNTD_G1_RAI_A[3:0] Receive Interface B Control Registers 0x50BF 0x50C0 DS3_RXMODE_B_1 DS3_RXMODE_B_2 R/W DS3_OOF_ FMODE_B DS3_RDS3PLCP_B[6][1:0] DS3_RDS3PLCP_B[5][1:0] DS3_RDS3PLCP_B[4][1:0] DS3_RDS3PLCP_B[3][1:0] DS3_RDS3PLCP_B[2][1:0] DS3_RDS3PLCP_B[1][1:0] DS3_RDS3PLCP_B[11][1: 0] DS3_RDS3PLCP_B[10][1: DS3_RDS3PLCP_B[9][1:0] DS3_RDS3PLCP_B[8][1:0] DS3_RDS3PLCP_B[7][1:0] 0] R/W DS3_RPRBS_INV_B[1: DS3_ DS3_RDS3PLCP_B[12][1: 0] RPRBS 0] 23_ B[1:0] R/W -- DS3_RPRBS_TSSEL_B[2][3:0] 0x50C1 0x50C2-- 0x50CA DS3_RXPRBS_B -- DS3_RPRBS_TSSEL_B[1][3:0] DS3_RPRBS_DS3_PLCP_ DS3_RPRBS__15or20_B[ B[1:0] 1:0] DS3_PLCP_CNTD_G1_RAI_B[3:0] Agere Systems Inc. 587 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Interface A Counters 0x5100 0x5101 0x5102 0x5103 0x5104 0x5105 0x5106 0x5107 0x5108 0x5109 0x510A 0x510B 0x510C 0x510D 0x510E 0x510F 0x5110 0x5111 0x5112 0x5113 0x5114 0x5115 0x5116 0x5117 0x5118 0x5119 0x511A 0x511B 0x511C 0x511D 0x511E 0x511F DS3_RXDS3FBIT_A1 DS3_RXDS3FBIT_A2 DS3_RXDS3FBIT_A3 DS3_RXDS3FBIT_A4 DS3_RXDS3FBIT_A5 DS3_RXDS3FBIT_A6 DS3_RXDS3FBIT_A7 DS3_RXDS3FBIT_A8 DS3_RXDS3FBIT_A9 DS3_RXDS3FBIT_A10 DS3_RXDS3FBIT_A11 DS3_RXDS3FBIT_A12 DS3_RXDS3_CVP_P_A1 DS3_RXDS3_CVP_P_A2 DS3_RXDS3_CVP_P_A3 DS3_RXDS3_CVP_P_A4 DS3_RXDS3_CVP_P_A5 DS3_RXDS3_CVP_P_A6 DS3_RXDS3_CVP_P_A7 DS3_RXDS3_CVP_P_A8 DS3_RXDS3_CVP_P_A9 DS3_RXDS3_CVP_P_A10 DS3_RXDS3_CVP_P_A11 DS3_RXDS3_CVP_P_A12 DS3_RXDS3_CVCP_P_A1 DS3_RXDS3_CVCP_P_A2 DS3_RXDS3_CVCP_P_A3 DS3_RXDS3_CVCP_P_A4 DS3_RXDS3_CVCP_P_A5 DS3_RXDS3_CVCP_P_A6 DS3_RXDS3_CVCP_P_A7 DS3_RXDS3_CVCP_P_A8 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO DS3_FERR_CNT_A1[13:0] DS3_FERR_CNT_A2[13:0] DS3_FERR_CNT_A3[13:0] DS3_FERR_CNT_A4[13:0] DS3_FERR_CNT_A5[13:0] DS3_FERR_CNT_A6[13:0] DS3_FERR_CNT_A7[13:0] DS3_FERR_CNT_A8[13:0] DS3_FERR_CNT_A9[13:0] DS3_FERR_CNT_A10[13:0] DS3_FERR_CNT_A11[13:0] DS3_FERR_CNT_A12[13:0] DS3_PERR_CNT_A1[13:0] DS3_PERR_CNT_A2[13:0] DS3_PERR_CNT_A3[13:0] DS3_PERR_CNT_A4[13:0] DS3_PERR_CNT_A5[13:0] DS3_PERR_CNT_A6[13:0] DS3_PERR_CNT_A7[13:0] DS3_PERR_CNT_A8[13:0] DS3_PERR_CNT_A9[13:0] DS3_PERR_CNT_A10[13:0] DS3_PERR_CNT_A11[13:0] DS3_PERR_CNT_A12[13:0] DS3_CPERR_CNT_A1[13:0] DS3_CPERR_CNT_A2[13:0] DS3_CPERR_CNT_A3[13:0] DS3_CPERR_CNT_A4[13:0] DS3_CPERR_CNT_A5[13:0] DS3_CPERR_CNT_A6[13:0] DS3_CPERR_CNT_A7[13:0] DS3_CPERR_CNT_A8[13:0] 588 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x5120 0x5121 0x5122 0x5123 0x5124 0x5125 0x5126 0x5127 0x5128 0x5129 0x512A 0x512B 0x512C 0x512D 0x512E 0x512F 0x5160 0x5161 0x5162 0x5163 0x5164 0x5165 0x5166 0x5167 0x5168 0x5169 0x516A 0x516B Register Name DS3_RXDS3_CVCP_P_A9 DS3_RXDS3_CVCP_P_A10 DS3_RXDS3_CVCP_P_A11 DS3_RXDS3_CVCP_P_A12 DS3_RXDS3FEBE_A1 DS3_RXDS3FEBE_A2 DS3_RXDS3FEBE_A3 DS3_RXDS3FEBE_A4 DS3_RXDS3FEBE_A5 DS3_RXDS3FEBE_A6 DS3_RXDS3FEBE_A7 DS3_RXDS3FEBE_A8 DS3_RXDS3FEBE_A9 DS3_RXDS3FEBE_A10 DS3_RXDS3FEBE_A11 DS3_RXDS3FEBE_A12 DS3_RXPLCPB1ECNT_A1 DS3_RXPLCPB1ECNT_A2 DS3_RXPLCPB1ECNT_A3 DS3_RXPLCPB1ECNT_A4 DS3_RXPLCPB1ECNT_A5 DS3_RXPLCPB1ECNT_A6 DS3_RXPLCPB1ECNT_A7 DS3_RXPLCPB1ECNT_A8 DS3_RXPLCPB1ECNT_A9 DS3_RXPLCPB1ECNT_A10 DS3_RXPLCPB1ECNT_A11 DS3_RXPLCPB1ECNT_A12 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3_CPERR_CNT_A9[13:0] DS3_CPERR_CNT_A10[13:0] DS3_CPERR_CNT_A11[13:0] DS3_CPERR_CNT_A12[13:0] DS3_FEBE_CNT_A1[13:0] DS3_FEBE_CNT_A2[13:0] DS3_FEBE_CNT_A3[13:0] DS3_FEBE_CNT_A4[13:0] DS3_FEBE_CNT_A5[13:0] DS3_FEBE_CNT_A6[13:0] DS3_FEBE_CNT_A7[13:0] DS3_FEBE_CNT_A8[13:0] DS3_FEBE_CNT_A9[13:0] DS3_FEBE_CNT_A10[13:0] DS3_FEBE_CNT_A11[13:0] DS3_FEBE_CNT_A12[13:0] DS3_PLCP_B1ERRCNT_A1[15:0] DS3_PLCP_B1ERRCNT_A2[15:0] DS3_PLCP_B1ERRCNT_A3[15:0] DS3_PLCP_B1ERRCNT_A4[15:0] DS3_PLCP_B1ERRCNT_A5[15:0] DS3_PLCP_B1ERRCNT_A6[15:0] DS3_PLCP_B1ERRCNT_A7[15:0] DS3_PLCP_B1ERRCNT_A8[15:0] DS3_PLCP_B1ERRCNT_A9[15:0] DS3_PLCP_B1ERRCNT_A10[15:0] DS3_PLCP_B1ERRCNT_A11[15:0] DS3_PLCP_B1ERRCNT_A12[15:0] Agere Systems Inc. 589 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x516C 0x516D 0x516E 0x516F 0x5170 0x5171 0x5172 0x5173 0x5174 0x5175 0x5176 0x5177 Register Name DS3_PLCPFEBECNT_A1 DS3_PLCPFEBECNT_A2 DS3_PLCPFEBECNT_A3 DS3_PLCPFEBECNT_A4 DS3_PLCPFEBECNT_A5 DS3_PLCPFEBECNT_A6 DS3_PLCPFEBECNT_A7 DS3_PLCPFEBECNT_A8 DS3_PLCPFEBECNT_A9 DS3_PLCPFEBECNT_A10 DS3_PLCPFEBECNT_A11 DS3_PLCPFEBECNT_A12 Type RO RO RO RO RO RO RO RO RO RO RO RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3_PLCP_G1_FEBE_ERRCNT_A1[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A2[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A3[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A4[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A5[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A6[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A7[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A8[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A9[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A10[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A11[15:0] DS3_PLCP_G1_FEBE_ERRCNT_A12[15:0] 590 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Interface B Counters 0x5180 0x5181 0x5182 0x5183 0x5184 0x5185 0x5186 0x5187 0x5188 0x5189 0x518A 0x518B 0x518C 0x518D 0x518E 0x518F 0x5190 0x5191 0x5192 0x5193 0x5194 DS3_RXDS3FBIT_B1 DS3_RXDS3FBIT_B2 DS3_RXDS3FBIT_B3 DS3_RXDS3FBIT_B4 DS3_RXDS3FBIT_B5 DS3_RXDS3FBIT_B6 DS3_RXDS3FBIT_B7 DS3_RXDS3FBIT_B8 DS3_RXDS3FBIT_B9 DS3_RXDS3FBIT_B10 DS3_RXDS3FBIT_B11 DS3_RXDS3FBIT_B12 DS3_RXDS3_CVP_P_B1 DS3_RXDS3_CVP_P_B2 DS3_RXDS3_CVP_P_B3 DS3_RXDS3_CVP_P_B4 DS3_RXDS3_CVP_P_B5 DS3_RXDS3_CVP_P_B6 DS3_RXDS3_CVP_P_B7 DS3_RXDS3_CVP_P_B8 DS3_RXDS3_CVP_P_B9 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO DS3_FERR_CNT_B1[13:0] DS3_FERR_CNT_B2[13:0] DS3_FERR_CNT_B3[13:0] DS3_FERR_CNT_B4[13:0] DS3_FERR_CNT_B5[13:0] DS3_FERR_CNT_B6[13:0] DS3_FERR_CNT_B7[13:0] DS3_FERR_CNT_B8[13:0] DS3_FERR_CNT_B9[13:0] DS3_FERR_CNT_B10[13:0] DS3_FERR_CNT_B11[13:0] DS3_FERR_CNT_B12[13:0] DS3_PERR_CNT_B1[13:0] DS3_PERR_CNT_B2[13:0] DS3_PERR_CNT_B3[13:0] DS3_PERR_CNT_B4[13:0] DS3_PERR_CNT_B5[13:0] DS3_PERR_CNT_B6[13:0] DS3_PERR_CNT_B7[13:0] DS3_PERR_CNT_B8[13:0] DS3_PERR_CNT_B9[13:0] Agere Systems Inc. 591 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x5195 0x5196 0x5197 0x5198 0x5199 0x519A 0x519B 0x519C 0x519D 0x519E 0x519F 0x51A0 0x51A1 0x51A2 0x51A3 0x51A4 0x51A5 0x51A6 0x51A7 0x51A8 0x51A9 0x51AA 0x51AB 0x51AC 0x51AD 0x51AE 0x51AF Register Name DS3_RXDS3_CVP_P_B10 DS3_RXDS3_CVP_P_B11 DS3_RXDS3_CVP_P_B12 DS3_RXDS3_CVCP_P_B1 DS3_RXDS3_CVCP_P_B2 DS3_RXDS3_CVCP_P_B3 DS3_RXDS3_CVCP_P_B4 DS3_RXDS3_CVCP_P_B5 DS3_RXDS3_CVCP_P_B6 DS3_RXDS3_CVCP_P_B7 DS3_RXDS3_CVCP_P_B8 DS3_RXDS3_CVCP_P_B9 DS3_RXDS3_CVCP_P_B10 DS3_RXDS3_CVCP_P_B11 DS3_RXDS3_CVCP_P_B12 DS3_RXDS3FEBE_B1 DS3_RXDS3FEBE_B2 DS3_RXDS3FEBE_B3 DS3_RXDS3FEBE_B4 DS3_RXDS3FEBE_B5 DS3_RXDS3FEBE_B6 DS3_RXDS3FEBE_B7 DS3_RXDS3FEBE_B8 DS3_RXDS3FEBE_B9 DS3_RXDS3FEBE_B10 DS3_RXDS3FEBE_B11 DS3_RXDS3FEBE_B12 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3_PERR_CNT_B10[13:0] DS3_PERR_CNT_B11[13:0] DS3_PERR_CNT_B12[13:0] DS3_CPERR_CNT_B1[13:0] DS3_CPERR_CNT_B2[13:0] DS3_CPERR_CNT_B3[13:0] DS3_CPERR_CNT_B4[13:0] DS3_CPERR_CNT_B5[13:0] DS3_CPERR_CNT_B6[13:0] DS3_CPERR_CNT_B7[13:0] DS3_CPERR_CNT_B8[13:0] DS3_CPERR_CNT_B9[13:0] DS3_CPERR_CNT_B10[13:0] DS3_CPERR_CNT_B11[13:0] DS3_CPERR_CNT_B12[13:0] DS3_FEBE_CNT_B1[13:0] DS3_FEBE_CNT_B2[13:0] DS3_FEBE_CNT_B3[13:0] DS3_FEBE_CNT_B4[13:0] DS3_FEBE_CNT_B5[13:0] DS3_FEBE_CNT_B6[13:0] DS3_FEBE_CNT_B7[13:0] DS3_FEBE_CNT_B8[13:0] DS3_FEBE_CNT_B9[13:0] DS3_FEBE_CNT_B10[13:0] DS3_FEBE_CNT_B11[13:0] DS3_FEBE_CNT_B12[13:0] 592 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x51C0 0x51C1 0x51C2 0x51C3 0x51C4 0x51C5 0x51C6 0x51C7 0x51C8 0x51C9 0x51CA 0x51CB 0x51CC 0x51CD 0x51CE 0x51CF 0x51D0 0x51D1 0x51D2 0x51D3 0x51D4 0x51D5 0x51D6 0x51D7 0x5200-- 0x52D7 Register Name DS3_RXPLCPB1ECNT_B1 DS3_RXPLCPB1ECNT_B2 DS3_RXPLCPB1ECNT_B3 DS3_RXPLCPB1ECNT_B4 DS3_RXPLCPB1ECNT_B5 DS3_RXPLCPB1ECNT_B6 DS3_RXPLCPB1ECNT_B7 DS3_RXPLCPB1ECNT_B8 DS3_RXPLCPB1ECNT_B9 DS3_RXPLCPB1ECNT_B10 DS3_RXPLCPB1ECNT_B11 DS3_RXPLCPB1ECNT_B12 DS3_PLCPFEBECNT_B1 DS3_PLCPFEBECNT_B2 DS3_PLCPFEBECNT_B3 DS3_PLCPFEBECNT_B4 DS3_PLCPFEBECNT_B5 DS3_PLCPFEBECNT_B6 DS3_PLCPFEBECNT_B7 DS3_PLCPFEBECNT_B8 DS3_PLCPFEBECNT_B9 DS3_PLCPFEBECNT_B10 DS3_PLCPFEBECNT_B11 DS3_PLCPFEBECNT_B12 -- Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3_PLCP_B1ERRCNT_B1[15:0] DS3_PLCP_B1ERRCNT_B2[15:0] DS3_PLCP_B1ERRCNT_B3[15:0] DS3_PLCP_B1ERRCNT_B4[15:0] DS3_PLCP_B1ERRCNT_B5[15:0] DS3_PLCP_B1ERRCNT_B6[15:0] DS3_PLCP_B1ERRCNT_B7[15:0] DS3_PLCP_B1ERRCNT_B8[15:0] DS3_PLCP_B1ERRCNT_B9[15:0] DS3_PLCP_B1ERRCNT_B10[15:0] DS3_PLCP_B1ERRCNT_B11[15:0] DS3_PLCP_B1ERRCNT_B12[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B1[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B2[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B3[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B4[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B5[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B6[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B7[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B8[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B9[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B10[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B11[15:0] DS3_PLCP_G1_FEBE_ERRCNT_B12[15:0] Agere Systems Inc. 593 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) DS3 Register Map (continued) Table 676. DS3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Transmit Control Signals (Channel Based 1--16) 0x5300-- DS3_TDS3PLCPCT 0x530F L1_CHD [1--16] 0x5310 --0x532F -- R/W DS3_TDS3_PLCP[1-- 16][1:0] DS3_TPLC DS3_TPLC DS3_TPLC DS3_TPLC DS3_TPLC DS3_TPLC P_A2INV[1 P_POIB7IN P_B1INV[1 P_RAI_SW P_RAI_DIN P_FEBE_S --16] V[1--16] --16] ENB[1-- S[1--16] WENB[1-- 16] 16] DS3_TXCHID_TO_TSMAPPING[1--16][1:0][3:0] -- R/W DS3_TDS3 DS3_TDS3 DS3_TDS3 DS3_TDS3 DS3_TDS3 DS3_TDS3 DS3_TDS3 _AIS[1-- _IDLE[1-- _FINV[1-- _MINV[1-- _PINV[1-- _CPINV[1 _FEBEINS[ 16] 16] 16] 16] 16] --16] 1--16] DS3_TDS3 DS3_TDS3 _XDINS[1 _TFEAC_I --16] NS[1--16] DS3_TDS3_TFEAC_CODE[1--16][5:0] 0x53C0-- DS3_TDS3CTL_CH 0x53CF D[1--16] 0x53D0 -- 0x53EF -- -- Transmit PRBS Control Signals 0x53F0 DS3_TXPRBSCTL_ 1 DS3_TXPRBSCTL_ 2 R/W DS3_TPRB DS3_TPRB DS3_TPRB DS3_TPRB S_1BERRI S15OR20[ S_INV[1] S_DS3OR NS[1] 1] PLCP[1] DS3_TPRB DS3_TPRB DS3_TPRB DS3_TPRB S_1BERRI S15OR20[ S_INV[2] S_DS3OR NS[2] 2] PLCP[2] Transmit FEBE Insert Value 0x53F2 DS3_TXFEBEDINS R/W DS3_TBR CNT_RST Transmit FIFO Control 0x53F3 DS3_TXFIFO R/W -- DS3_TFIFO_MIN[5:0] DS3_TFIFO_MAX[5:0] DS3_TPLCP_FEBE_DINS[3:0] DS3_TPRBS_CHID_INS[1][5:0] 0x53F1 R/W DS3_TPRBS_CHID_INS[2][5:0] 594 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map Table 677. E3 Register Map Note: Shading denotes reserved bits. Addr 0x5000 0x5001 0x5002 Register Name DS3E3_VERR E3_SCRATCHR E3_CORW_ GPOSEL Type RO R/W R/W E3_COR_ COWN SEQ_RX TM_RX PT_TX E3_SCRATCH[15:0] TM_TX GPOSEL[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3E3_VER[7:0] Interface A Delta/Event Registers 0x5003 0x5004 0x5005 0x5006 0x5007 0x5008 0x5009 0x500A 0x500B 0x500C 0x500D 0x500E E3FRMD_A E3LOFD_A E3_TR_ MISMATCHD_A E3AISD_A E3_D_A E3_MA_SSMD_A E3_D_A E3_MA_PTD_A E3_PLCP_LOFD_A E3_PLCPOOFD_A E3_PLCPASD_A -- COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W -- E3_OOFD_A[12--1] E3_LOFD_A[12--1] E3_TR_MISMATCHD_A[12--1] E3_AISPAT_DETD_A[12--1] E3_PLCP_ZF_DMON[x]D E3_MA_SSMD_A[12--1] E3_G751_RAI_DETD_A[12--1]/E3_G832_MA_RDI_DETD_A[12--1] E3_MA_PTD_A[12--1] E3_PLCP_LOFD_A[12--1] E3_PLCP_OOFD_A[12--1] E3_PLCP_G1_ASD_A[12--1] Agere Systems Inc. 595 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface B Delta/Event Registers 0x500F 0x5010 0x5011 0x5012 0x5013 0x5014 0x5015 0x5016 0x5017 0x5018 0x5019 0x501A-- 0x5038 E3FRMD_B E3LOFD_B E3_TR_ MISMATCHD_B E3AISD_B E3_D_B E3_MA_SSMD_B E3_D_B E3_MA_PTD_B E3_PLCP_LOFD_B E3_PLCPOOFD_B E3_PLCP_G1_ ASD_B -- COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W COR/ W -- E3_OOFD_B[12--1] E3_LOFD_B[12--1] E3_TR_MISMATCHD_B[12--1] E3_AISPAT_DETD_B[12--1] E3_PLCP_ZF_DMON[x]D E3_MA_SSMD_B[12--1] E3_G751_RAI_DETD_B[12--1]/E3_G832_MA_RDI_DETD_B[12--1] E3_MA_PTD_B[12--1] E3_PLCP_LOFD_B[12--1] E3_PLCP_OOFD_B[12--1] E3_PLCP_G1_ASD_B[12--1] 596 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface A Mask Registers 0x5039 0x503A 0x503B 0x503C 0x503D 0x503E 0x503F 0x5040 0x5041 0x5042 0x5043 0x5044 E3FRMM_A E3LOFM_A E3SEFM_A E3AISM_A E3_M_A E3MAM_A E3_M_A E3_MA_PTM_A E3_PLCP_LOFM_A E3_PLCPOOFM_A E3_PLCPASM_A -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- Interface B Mask Registers 0x5045 0x5046 0x5047 0x5048 0x5049 0x504A 0x504B 0x504C 0x504D 0x504E 0x504F 0x5050-- 0x506E E3FRMM_B E3LOFM_B E3SEFM_B E3AISM_B E3_M_B E3MAM_B E3_M_B E3_MA_PTM_B E3_PLCP_LOFM_B E3_PLCPOOFM_B E3_PLCPASM_B -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- E3_OOFM_B[12--1] E3_LOFM_B[12--1] E3_SEFM_B[12--1] E3_AISPAT_DETM_B[12--1] E3_PLCP_ZF_DMONM E3_MA_SSMM_B[12--1] E3_G751_RAI_DETM_B[12--1]/E3_G832_MA_RDI_DETM_B[12--1] E3_MA_PTM_B[12--1] E3_PLCP_LOFM_B[12--1] E3_PLCP_OOFM_B[12--1] E3_PLCP_G1_ASM_B[12--1] E3_OOFM_A[12--1] E3_LOFM_A[12--1] E3_SEFM_A[12--1] E3_AISPAT_DETM_A[12--1] E3_PLCP_ZF_DMONM E3_MA_SSMM_A[12--1] E3_G751_RAI_DETM_A[12--1]/E3_G832_MA_RDI_DETM_A[12--1] E3_MA_PTM_A[12--1] E3_PLCP_LOFM_A[12--1] E3_PLCP_OOFM_A[12--1] E3_PLCP_G1_ASM_A[12--1] Agere Systems Inc. 597 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface A State Registers 0x506F 0x5070 0x5071 0x5072 0x5073 0x5074 0x5075 0x5076 0x5077 0x5078 0x5079 0x507A 0x507B 0x507C 0x507D 0x507E 0x507F 0x5080 0x5081 E3FRM_A E3LOF_A E3SEF_A E3AIS_A -- -- E3_A -- E3_PLCP_LOF_A E3_PLCPOOF_A E3_PLCPAS_A -- E3SSMCODE_A1 E3SSMCODE_A2 E3SSMCODE_A3 E3SSMCODE_A4 E3SSMCODE_A5 E3SSMCODE_A6 -- RO RO RO RO -- -- RO -- RO RO RO -- RO RO RO RO RO RO -- E3_MA_SSM_ CODE_A[1][3] E3_MA_SSM_ CODE_A[3][3] E3_MA_SSM_ CODE_A[5][3] E3_MA_SSM_ CODE_A[7][3] E3_MA_SSM_ CODE_A[9][3] E3_MA_SSM_ CODE_A[2][3] E3_MA_SSM_ CODE_A[4][3] E3_MA_SSM_ CODE_A[6][3] E3_MA_SSM_ CODE_A[8][3] E3_MA_SSM_ CODE_A[10][3] E3_MA_SSM_CODE_A[2][2:0] E3_MA_SSM_CODE_A[4][2:0] E3_MA_SSM_CODE_A[6][2:0] E3_MA_SSM_CODE_A[8][2:0] E3_MA_SSM_CODE_A[10][2:0] E3_MA_SSM_CODE_A[12][2:0] E3_MA_PT_CODE_A[2][2:0] E3_MA_PT_CODE_A[4][2:0] E3_MA_PT_CODE_A[6][2:0] E3_MA_PT_CODE_A[8][2:0] E3_MA_PT_CODE_A[10][2:0] E3_MA_PT_CODE_A[12][2:0] E3_MA_SSM_CODE_A[1][2:0] E3_MA_SSM_CODE_A[3][2:0] E3_MA_SSM_CODE_A[5][2:0] E3_MA_SSM_CODE_A[7][2:0] E3_MA_SSM_CODE_A[9][2:0] E3_MA_SSM_CODE_A[11][2:0] E3_MA_PT_CODE_A[1][2:0] E3_MA_PT_CODE_A[3][2:0] E3_MA_PT_CODE_A[5][2:0] E3_MA_PT_CODE_A[7][2:0] E3_MA_PT_CODE_A[9][2:0] E3_MA_PT_CODE_A[11][2:0] E3_PLCP_LOF_A[12--1] E3_PLCP_OOF_A[12--1] E3_PLCP_G1_AS_A[12--1] E3_G751_RAI_DET_A[12--1]/E3_G832_MA_RDI_DET_A[12--1] E3_OOF_A[12--1] E3_LOF_A[12--1] E3_SEF_A[12--1] E3_AISPAT_DET_A[12--1] E3_MA_SSM_ E3_MA_SSM_ CODE_A[11][3] CODE_A[12][3] 598 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface B State Registers 0x5082 0x5083 0x5084 0x5085 0x5086 0x5087 0x5088 0x5089 0x508A 0x508B 0x508C 0x508D 0x508E 0x508F 0x5090 0x5091 0x5092 0x5093 0x5094-- 0x50BA E3FRM_B E3LOF_B E3SEF_B E3AIS_B -- -- E3_B -- E3_PLCP_LOF_B E3_PLCPOOF_B E3_PLCPAS_B -- E3SSMCODE_B1 E3SSMCODE_B2 E3SSMCODE_B3 E3SSMCODE_B4 E3SSMCODE_B5 E3SSMCODE_B6 -- RO RO RO RO -- -- RO -- RO RO RO -- RO RO RO RO RO RO -- E3_MA_SSM_ CODE_B[1][3] E3_MA_SSM_ CODE_B[3][3] E3_MA_SSM_ CODE_B[5][3] E3_MA_SSM_ CODE_B[7][3] E3_MA_SSM_ CODE_B[9][3] E3_MA_SSM_ CODE_B[2][3] E3_MA_SSM_ CODE_B[4][3] E3_MA_SSM_ CODE_B[6][3] E3_MA_SSM_ CODE_B[8][3] E3_MA_SSM_ CODE_B[10][3] E3_MA_SSM_CODE_B[2][2:0] E3_MA_SSM_CODE_B[4][2:0] E3_MA_SSM_CODE_B[6][2:0] E3_MA_SSM_CODE_B[8][2:0] E3_MA_SSM_CODE_B[10][2:0] E3_MA_SSM_CODE_B[12][2:0] E3_MA_PT_CODE_B[2][2:0] E3_MA_PT_CODE_B[4][2:0] E3_MA_PT_CODE_B[6][2:0] E3_MA_PT_CODE_B[8][2:0] E3_MA_PT_CODE_B[10][2:0] E3_MA_PT_CODE_B[12][2:0] E3_MA_SSM_CODE_B[1][2:0] E3_MA_SSM_CODE_B[3][2:0] E3_MA_SSM_CODE_B[5][2:0] E3_MA_SSM_CODE_B[7][2:0] E3_MA_SSM_CODE_B[9][2:0] E3_MA_SSM_CODE_B[11][2:0] E3_MA_PT_CODE_B[1][2:0] E3_MA_PT_CODE_B[3][2:0] E3_MA_PT_CODE_B[5][2:0] E3_MA_PT_CODE_B[7][2:0] E3_MA_PT_CODE_B[9][2:0] E3_MA_PT_CODE_B[11][2:0] E3_PLCP_LOF_B[12--1] E3_PLCP_OOF_B[12--1] E3_PLCP_G1_AS_B[12--1] E3_G751_RAI_DET_B[12--1]/E3_G832_MA_RDI_DET_B[12--1] E3_OOF_B[12--1] E3_LOF_B[12--1] E3_SEF_B[12--1] E3_AISPAT_DET_B[12--1] E3_MA_SSM_ E3_MA_SSM_ CODE_B[11][3] CODE_B[12][3] Agere Systems Inc. 599 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Interface A Control Registers 0x50BB 0x50BC 0x50BD 0x50BE E3_RXMODE_A_1 E3_RXMODE_A_2 -- RDS3E3_A R/W R/W -- R/W E3_PLCP_ZF_TSSEL_A[3:0] Receive Interface B Control Registers 0x50BF 0x50C0 0x50C1 0x50C2 0x50C3-- 0x50CA E3_RXMODE_B_1 E3_RXMODE_B_2 -- RDS3E3_B -- R/W R/W -- R/W -- E3_PLCP_ZF_TSSEL_B[3:0] RDS3orE3_B[12--1] E3_RPRBS23_ B[1:0] E3_RE3PLCP_B[6][1:0] E3_RE3PLCP_B[12][1:0] E3_RE3PLCP_B[5][1:0] E3_RE3PLCP_B[11][1:0] E3_RE3PLCP_B[4][1:0] E3_RE3PLCP_B[10][1:0] E3_RE3PLCP_B[3][1:0] E3_RE3PLCP_B[9][1:0] E3_RE3PLCP_B[2][1:0] E3_RE3PLCP_B[8][1:0] E3_RE3PLCP_B[1][1:0] E3_RE3PLCP_B[7][1:0] RDS3orE3_A[12--1] E3_RPRBS23_ A[1:0] E3_RE3PLCP_A[6][1:0] E3_RE3PLCP_A[12][1:0] E3_RE3PLCP_A[5][1:0] E3_RE3PLCP_A[11][1:0] E3_RE3PLCP_A[4][1:0] E3_RE3PLCP_A[10][1:0] E3_RE3PLCP_A[3][1:0] E3_RE3PLCP_A[9][1:0] E3_RE3PLCP_A[2][1:0] E3_RE3PLCP_A[8][1:0] E3_RE3PLCP_A[1][1:0] E3_RE3PLCP_A[7][1:0] 600 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Common Parameters (Per Block) 0x50CB E3PROV_1 R/W E3_G751_RAI_DET_ CNTD[3:0] E3_G832_AIS_0CNT[3:0] E3_G751_AIS_0CNT[3:0] E3_PLCP_G1_AS_ CNTD[3:0] E3_PLCP_ZF_CNTD[3:0] E3_B1_ BITBLK E3_MA_PT_CNTD[3:0] E3_PLCP_G E3_PLCP_B 1_FEBE_BI 1_ TBLK BITBLK E3_G751_1 0or14BIT_F RMPAT E3_LOF_CLRCNT[4:0] E3_LOF_SETCNT[4:0] 0x50CC 0x50CD 0x50CE E3PROV_2 E3PROV_3 E3PROV_4 R/W R/W R/W E3_PLCP_LOF_CLRCNT[4:0] E3_PLCP_LOF_SETCNT[4:0] 0x50CF E3PROV_5 R/W E3_MA_SSM_CNTD[3:0] Receive E3 G.832 Multiframe Enable per Time Slot E3_G832_MA_RDI_CNTD[3:0] 0x50D0 0x50D1 0x50D2-- 0x50D3 E3_MA_MF_A E3_MA_MF_B -- R/W R/W -- E3_MA_MF_ENABLE_A[12--1] E3_MA_MF_ENABLE_B[12--1] Receive E3 G.832 Trail Identifier Monitor Mode per Time Slot 0x50D4 0x50D5 0x50D6 0x50D7 0x50D8-- 0x50DB E3_TR_MMODE_A1 E3_TR_MMODE_A2 E3_TR_MMODE_B1 E3_TR_MMODE_B2 -- R/W R/W R/W R/W -- Receive E3 PLCP Z1--Z3, F1 Byte State Values 0x50DC 0x50DD 0x50DE 0x50DF 0x50E0-- 0x50FF E3PLCP_MONA1 E3PLCP_MONA2 E3PLCP_MONB1 E3PLCP_MONB2 -- RO RO RO RO -- E3_PLCP_Z1_DMON_A[7:0] E3_PLCP_Z3_DMON_A[7:0] E3_PLCP_Z1_DMON_B[7:0] E3_PLCP_Z3_DMON_B[7:0] E3_PLCP_Z2_DMON_A[7:0] E3_PLCP_F1_DMON_A[7:0] E3_PLCP_Z2_DMON_B[7:0] E3_PLCP_F1_DMON_B[7:0] E3_TR_MMODE_A[6][1:0] E3_TR_MMODE_A[5][1:0] E3_TR_MMODE_A[4][1:0] E3_TR_MMODE_A[3][1:0] E3_TR_MMODE_A[2][1:0] E3_TR_MMODE_A[8][1:0] E3_TR_MMODE_B[2][1:0] E3_TR_MMODE_B[8][1:0] E3_TR_MMODE_A[1][1:0] E3_TR_MMODE_A[7][1:0] E3_TR_MMODE_B[1][1:0] E3_TR_MMODE_B[7][1:0] E3_TR_MMODE_A[12][1:0] E3_TR_MMODE_A[11][1:0] E3_TR_MMODE_A[10][1:0] E3_TR_MMODE_A[9][1:0] E3_TR_MMODE_B[6][1:0] E3_TR_MMODE_[5][1:0] E3_TR_MMODE_B[4][1:0] E3_TR_MMODE_B[3][1:0] E3_TR_MMODE_B[12][1:0] E3_TR_MMODE_B[11][1:0] E3_TR_MMODE_B[10][1:0] E3_TR_MMODE_B[9][1:0] Agere Systems Inc. 601 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Interface A Counters 0x5100 0x5101 0x5102 0x5103 0x5104 0x5105 0x5106 0x5107 0x5108 0x5109 0x510A 0x510B E3_MA_REI_ERRCNT _A1 E3_MA_REI_ERRCNT _A2 E3_MA_REI_ERRCNT _A3 E3_MA_REI_ERRCNT _A4 E3_MA_REI_ERRCNT _A5 E3_MA_REI_ERRCNT _A6 E3_MA_REI_ERRCNT _A7 E3_MA_REI_ERRCNT _A8 E3_MA_REI_ERRCNT _A9 E3_MA_REI_ERRCNT _A10 E3_MA_REI_ERRCNT _A11 E3_MA_REI_ERRCNT _A12 RO RO RO RO RO RO RO RO RO RO RO RO E3_MA_REI_ERRCNT_A1[13:0] E3_MA_REI_ERRCNT_A2[13:0] E3_MA_REI_ERRCNT_A3[13:0] E3_MA_REI_ERRCNT_A4[13:0] E3_MA_REI_ERRCNT_A5[13:0] E3_MA_REI_ERRCNT_A6[13:0] E3_MA_REI_ERRCNT_A7[13:0] E3_MA_REI_ERRCNT_A8[13:0] E3_MA_REI_ERRCNT_A9[13:0] E3_MA_REI_ERRCNT_A10[13:0] E3_MA_REI_ERRCNT_A11[13:0] E3_MA_REI_ERRCNT_A12[13:0] 602 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x510C 0x510D 0x510E 0x510F 0x5110 0x5111 0x5112 0x5113 0x5114 0x5115 0x5116 0x5117 0x5118-- 0x515F Register Name E3_B1_ERRCNT_A1 E3_B1_ERRCNT_A2 E3_B1_ERRCNT_A3 E3_B1_ERRCNT_A4 E3_B1_ERRCNT_A5 E3_B1_ERRCNT_A6 E3_B1_ERRCNT_A7 E3_B1_ERRCNT_A8 E3_B1_ERRCNT_A9 E3_B1_ERRCNT_A10 E3_B1_ERRCNT_A11 E3_B1_ERRCNT_A12 -- Type RO RO RO RO RO RO RO RO RO RO RO RO -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E3_B1_ERRCNT_A1[13:0] E3_B1_ERRCNT_A2[13:0] E3_B1_ERRCNT_A3[13:0] E3_B1_ERRCNT_A4[13:0] E3_B1_ERRCNT_A5[13:0] E3_B1_ERRCNT_A6[13:0] E3_B1_ERRCNT_A7[13:0] E3_B1_ERRCNT_A8[13:0] E3_B1_ERRCNT_A9[13:0] E3_B1_ERRCNT_A10[13:0] E3_B1_ERRCNT_A11[13:0] E3_B1_ERRCNT_A12[13:0] Agere Systems Inc. 603 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x5160 0x5161 0x5162 0x5163 0x5164 0x5165 0x5166 0x5167 0x5168 0x5169 0x516A 0x516B 0x516C 0x516D 0x516E 0x516F 0x5170 0x5171 0x5172 0x5173 0x5174 0x5175 0x5176 0x5177 0x5178-- 0x517F Register Name E3_PLCP_B1ERRCNT_A1 E3_PLCP_B1ERRCNT_A2 E3_PLCP_B1ERRCNT_A3 E3_PLCP_B1ERRCNT_A4 E3_PLCP_B1ERRCNT_A5 E3_PLCP_B1ERRCNT_A6 E3_PLCP_B1ERRCNT_A7 E3_PLCP_B1ERRCNT_A8 E3_PLCP_B1ERRCNT_A9 E3_PLCP_B1ERRCNT_A10 E3_PLCP_B1ERRCNT_A11 E3_PLCP_B1ERRCNT_A12 E3_PLCPFEBECNT_A1 E3_PLCPFEBECNT_A2 E3_PLCPFEBECNT_A3 E3_PLCPFEBECNT_A4 E3_PLCPFEBECNT_A5 E3_PLCPFEBECNT_A6 E3_PLCPFEBECNT_A7 E3_PLCPFEBECNT_A8 E3_PLCPFEBECNT_A9 E3_PLCPFEBECNT_A10 E3_PLCPFEBECNT_A11 E3_PLCPFEBECNT_A12 -- Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E3_PLCP_B1ERRCNT_A1[15:0] E3_PLCP_B1ERRCNT_A2[15:0] E3_PLCP_B1ERRCNT_A3[15:0] E3_PLCP_B1ERRCNT_A4[15:0] E3_PLCP_B1ERRCNT_A5[15:0] E3_PLCP_B1ERRCNT_A6[15:0] E3_PLCP_B1ERRCNT_A7[15:0] E3_PLCP_B1ERRCNT_A8[15:0] E3_PLCP_B1ERRCNT_A9[15:0] E3_PLCP_B1ERRCNT_A10[15:0] E3_PLCP_B1ERRCNT_A11[15:0] E3_PLCP_B1ERRCNT_A12[15:0] E3_PLCP_G1_FEBE_ERRCNT_A1[15:0] E3_PLCP_G1_FEBE_ERRCNT_A2[15:0] E3_PLCP_G1_FEBE_ERRCNT_A3[15:0] E3_PLCP_G1_FEBE_ERRCNT_A4[15:0] E3_PLCP_G1_FEBE_ERRCNT_A5[15:0] E3_PLCP_G1_FEBE_ERRCNT_A6[15:0] E3_PLCP_G1_FEBE_ERRCNT_A7[15:0] E3_PLCP_G1_FEBE_ERRCNT_A8[15:0] E3_PLCP_G1_FEBE_ERRCNT_A8[15:0] E3_PLCP_G1_FEBE_ERRCNT_A10[15:0] E3_PLCP_G1_FEBE_ERRCNT_A11[15:0] E3_PLCP_G1_FEBE_ERRCNT_A12[15:0] 604 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Interface B Counters 0x5180 0x5181 0x5182 0x5183 0x5184 0x5185 0x5186 0x5187 0x5188 0x5189 0x518A 0x518B 0x518C 0x518D 0x518E 0x518F 0x5190 0x5191 0x5192 0x5193 0x5194 0x5195 0x5196 0x5197 0x5198-- 0x51BF E3_MA_REI_ERRCNT_B1 E3_MA_REI_ERRCNT_B2 E3_MA_REI_ERRCNT_B3 E3_MA_REI_ERRCNT_B4 E3_MA_REI_ERRCNT_B5 E3_MA_REI_ERRCNT_B6 E3_MA_REI_ERRCNT_B7 E3_MA_REI_ERRCNT_B8 E3_MA_REI_ERRCNT_B9 E3_MA_REI_ERRCNT_ B10 E3_MA_REI_ERRCNT_ B11 E3_MA_REI_ERRCNT_ B12 E3_B1_ERRCNT_B1 E3_B1_ERRCNT_B2 E3_B1_ERRCNT_B3 E3_B1_ERRCNT_B4 E3_B1_ERRCNT_B5 E3_B1_ERRCNT_B6 E3_B1_ERRCNT_B7 E3_B1_ERRCNT_B8 E3_B1_ERRCNT_B9 E3_B1_ERRCNT_B10 E3_B1_ERRCNT_B11 E3_B1_ERRCNT_B12 -- RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO -- E3_MA_REI_ERRCNT_B1[13:0] E3_MA_REI_ERRCNT_B2[13:0] E3_MA_REI_ERRCNT_B3[13:0] E3_MA_REI_ERRCNT_B4[13:0] E3_MA_REI_ERRCNT_B5[13:0] E3_MA_REI_ERRCNT_B6[13:0] E3_MA_REI_ERRCNT_B7[13:0] E3_MA_REI_ERRCNT_B8[13:0] E3_MA_REI_ERRCNT_B9[13:0] E3_MA_REI_ERRCNT_B10[13:0] E3_MA_REI_ERRCNT_B11[13:0] E3_MA_REI_ERRCNT_B12[13:0] E3_B1_ERRCNT_B1[13:0] E3_B1_ERRCNT_B2[13:0] E3_B1_ERRCNT_B3[13:0] E3_B1_ERRCNT_B4[13:0] E3_B1_ERRCNT_B5[13:0] E3_B1_ERRCNT_B6[13:0] E3_B1_ERRCNT_B7[13:0] E3_B1_ERRCNT_B8[13:0] E3_B1_ERRCNT_B9[13:0] E3_B1_ERRCNT_B10[13:0] E3_B1_ERRCNT_B11[13:0] E3_B1_ERRCNT_B12[13:0] Agere Systems Inc. 605 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr 0x51C0 0x51C1 0x51C2 0x51C3 0x51C4 0x51C5 0x51C6 0x51C7 0x51C8 0x51C9 0x51CA 0x51CB 0x51CC 0x51CD 0x51CE 0x51CF 0x51D0 0x51D1 0x51D2 0x51D3 0x51D4 0x51D5 0x51D6 0x51D7 0x5200-- 0x52D7 Register Name E3_RXPLCPB1ECNT_B1 E3_RXPLCPB1ECNT_B2 E3_RXPLCPB1ECNT_B3 E3_RXPLCPB1ECNT_B4 E3_RXPLCPB1ECNT_B5 E3_RXPLCPB1ECNT_B6 E3_RXPLCPB1ECNT_B7 E3_RXPLCPB1ECNT_B8 E3_RXPLCPB1ECNT_B9 E3_RXPLCPB1ECNT_B10 E3_RXPLCPB1ECNT_B11 E3_RXPLCPB1ECNT_B12 E3_PLCPFEBECNT_B1 E3_PLCPFEBECNT_B2 E3_PLCPFEBECNT_B3 E3_PLCPFEBECNT_B4 E3_PLCPFEBECNT_B5 E3_PLCPFEBECNT_B6 E3_PLCPFEBECNT_B7 E3_PLCPFEBECNT_B8 E3_PLCPFEBECNT_B9 E3_PLCPFEBECNT_B10 E3_PLCPFEBECNT_B11 E3_PLCPFEBECNT_B12 -- Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E3_PLCP_B1ERRCNT_B1[15:0] E3_PLCP_B1ERRCNT_B2[15:0] E3_PLCP_B1ERRCNT_B3[15:0] E3_PLCP_B1ERRCNT_B4[15:0] E3_PLCP_B1ERRCNT_B5[15:0] E3_PLCP_B1ERRCNT_B6[15:0] E3_PLCP_B1ERRCNT_B7[15:0] E3_PLCP_B1ERRCNT_B8[15:0] E3_PLCP_B1ERRCNT_B9[15:0] E3_PLCP_B1ERRCNT_B10[15:0] E3_PLCP_B1ERRCNT_B11[15:0] E3_PLCP_B1ERRCNT_B12[15:0] E3_PLCP_G1_FEBE_ERRCNT_B1[15:0] E3_PLCP_G1_FEBE_ERRCNT_B2[15:0] E3_PLCP_G1_FEBE_ERRCNT_B3[15:0] E3_PLCP_G1_FEBE_ERRCNT_B4[15:0] E3_PLCP_G1_FEBE_ERRCNT_B5[15:0] E3_PLCP_G1_FEBE_ERRCNT_B6[15:0] E3_PLCP_G1_FEBE_ERRCNT_B7[15:0] E3_PLCP_G1_FEBE_ERRCNT_B8[15:0] E3_PLCP_G1_FEBE_ERRCNT_B9[15:0] E3_PLCP_G1_FEBE_ERRCNT_B10[15:0] E3_PLCP_G1_FEBE_ERRCNT_B11[15:0] E3_PLCP_G1_FEBE_ERRCNT_B12[15:0] 606 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Addr Register Name Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Transmit Control Signals (Channel Based 1--16) 0x5300-- 0x530F E3_ TDS3PLCPCTL1_ CHD[1--16] -- E3_TE3CTL_ CHD[1--16] -- R/W E3_TE3_ PLCP[1--16][1:0] TE3_PLCP TE3_PLCP TE3_PLCP _A2_INV _POIB7INV _B1INV [1--16] [1--16] [1--16] TE3_PLCP TE3_PLCP _G1_AS_D _FEBE_ INS[1--16] SWEN [1--16] TDS3orE3 0x5310-- 0x532F 0x53C0-- 0x53CF 0x53D0 -- 0x53F1 -- R/W TE3_AISIN TE3_TR_ TE3_FA_IN TE3_RAI_ TE3_MA_R TE3_MA_R TE3_B1IN S[1--16] INS[1--16] V[1--16] DINS DI_DINS EI_ERRIN V[1--16] [1--16] [1--16] S[1--16] TE3_MA_PTY_DINS[2:0] TE3_MA_SSM[1--16][3:0] -- Transmit FEBE Insert Value 0x53F2 0x53F3 E3_TXFEBEDINS -- R/W -- Transmit G.751 E3 PLCP Z1--Z3, F1 Insert Control 0x53F4 0x53F5 0x53F6 0x53F7 --0x53FF TXE3PLCP_P1 TXE3PLCP_P2 TXE3PLCP_P3 -- R/W R/W R/W -- TE3_PLCP_Z1_DINS[7:0] TE3_PLCP_Z3_DINS[7:0] TE3_PLCP_ZF_CHID[5:0] TE3_PLCP_Z2_DINS[7:0] TE3_PLCP_F1_DINS[7:0] TE3_PLCP_FEBE_DINS[3:0] Agere Systems Inc. 607 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) E3 Register Map (continued) Table 677. E3 Register Map (continued) Note: Shading denotes reserved bits. Transmit E3 G.832 Trail Trace (TR) Insert Registers (128 Locations) 0x5400 0x5401 0x5402 0x5403 0x5404 0x5405 0x5406 0x5407 0x5408 0x5409 0x540A 0x540B 0x540C 0x540D 0x540E 0x540F 0x5410-- 0x547F TXTRACE[1]_B1 TXTRACE[1]_B2 TXTRACE[1]_B3 TXTRACE[1]_B4 TXTRACE[1]_B5 TXTRACE[1]_B6 TXTRACE[1]_B7 TXTRACE[1]_B8 TXTRACE[2]_B1 TXTRACE[2]_B2 TXTRACE[2]_B3 TXTRACE[2]_B4 TXTRACE[2]_B5 TXTRACE[2]_B6 TXTRACE[2]_B7 TXTRACE[2]_B8 TXTRACE [3--16]_B[1--8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TE3_TR_DINS[1][1][7:0] TE3_TR_DINS[1][3][7:0] TE3_TR_DINS[1][5][7:0] TE3_TR_DINS[1][7][7:0] TE3_TR_DINS[1][9][7:0] TE3_TR_DINS[1][11][7:0] TE3_TR_DINS[1][13][7:0] TE3_TR_DINS[1][15][7:0] LSB TE3_TR_DINS[2][1][7:0] TE3_TR_DINS[2][3][7:0] TE3_TR_DINS[2][5][7:0] TE3_TR_DINS[2][7][7:0] TE3_TR_DINS[2][9][7:0] TE3_TR_DINS[2][11][7:0] TE3_TR_DINS[2][13][7:0] TE3_TR_DINS[2][15][7:0] LSB E3_G832_TR Messages 3--16 TE3_TR_DINS[1][0][7:0] MSB TE3_TR_DINS[1][2][7:0] TE3_TR_DINS[1][4][7:0] TE3_TR_DINS[1][6][7:0] TE3_TR_DINS[1][8][7:0] TE3_TR_DINS[1][10][7:0] TE3_TR_DINS[1][12][7:0] TE3_TR_DINS[1][14][7:0] TE3_TR_DINS[2][0][7:0] MSB TE3_TR_DINS[2][2][7:0] TE3_TR_DINS[2][4][7:0] TE3_TR_DINS[2][6][7:0] TE3_TR_DINS[2][8][7:0] TE3_TR_DINS[2][10][7:0] TE3_TR_DINS[2][12][7:0] TE3_TR_DINS[2][14][7:0] 608 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface DS3/E3 Block (continued) Appendix: DS3 to STS-1 Mapping DS3 information is mapped into an STS-1 frame as shown in Table 678. Table 678. STS-1 Mapping of DS3 Information J1 R R R R POH R R R R R R R R R R R R R R C1 C1 C1 C1 C1 C1 C1 C1 C1 25I 25I 25I 25I 25I 25I 25I 25I 25I R R R R R R R R R C2 C2 C2 C2 C2 C2 C2 C2 C2 I I I I I I I I I 25I 25I 25I 25I 25I 25I 25I 25I 25I R R R R R R R R R C3 C3 C3 C3 C3 C3 C3 C3 C3 I I I I I I I I I 25I 25I 25I 25I 25I 25I 25I 25I 25I Note: R = rrrr_rrrr, C1 = rr_c_iiii_i, C2 = cc_rr_rrrr, C3 = cc_rr_oo_r_s, and I = iiii_iiii, where r = reserved, i = information (payload) bit, c = stuff control bit, s = stuff opportunity bit, and o = overhead communications channel bit (reserved). Information is carried in the i bits. As can be seen, there are at 621 i bits per STS row, and an opportunity for one more i bit per row, to be carried in the stuff bit, if the stuff control bits indicate so. When a majority of the c bits are 0, then the stuff bit carries information. The o and r bits are set to undefined. The i (information) bits are organized as shown in Figure 61, into a DS3 multiframe. 680 bits = M-SUBFRAME X1 X2 P1 P2 M1 M2 M3 84D 84D 84D 84D 84D 84D 84D F1 F1 F1 F1 F1 F1 F1 84D 84D 84D 84D 84D 84D 84D C11 84D F2 F2 F2 F2 F2 F2 F2 84D 84D 84D 84D 84D 84D 84D C12 84D C22 84D C32 84D C42 84D C52 84D C62 84D C72 84D F3 F3 F3 F3 F3 F3 F3 84D 84D 84D 84D 84D 84D 84D C13 84D C23 84D C33 84D C43 84D C53 84D C63 84D C73 84D F4 F4 F4 F4 F4 F4 F4 84D 84D 84D 84D 84D 84D 84D 7 ROWS = 1 MULTIFRAME = 4760 bits = 44736 kbits/s C21 84D C31 84D C41 84D C51 84D C61 84D C71 84D M-SUBFRAME ALIGNMENT SIGNAL F1F2F3F4 = 1001 MULTIFRAME ALIGNMENT SIGNAL M1M2M3 = 010 D = DATA 5-8324(F)r.3 Figure 61. DS3 Multiframe Format Agere Systems Inc. 609 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 DS3/E3 Block (continued) Appendix: DS3 to STS-1 Mapping (continued) The information bits are segmented into 85 bits. Eight of these segments are grouped together to form an M-subframe, also called a row. Seven rows are grouped together to form one DS3 multiframe. Each of the 85-bit segments consists of 84 d (or data) bits and 1 overhead bit. The overhead bits are used to convey framing and status. The F1, F2, F3, and F4 bits are collectively called the M-subframe alignment signal and are fixed to the pattern 1001 (F1 = 1, F2 = 0, F3 = 0, F4 = 1). The M1, M2, and M3 bits are collectively called the multiframe alignment signal and are fixed to the pattern 010 (M1 = 0, M2 = 1, M3 = 0). The X, P, and C bits are explained later in this document. As can be seen, there are 84 bits x 8 blocks/row x 7 rows = 4704 data bits per multiframe. In this DS3 block, these data bits can either carry payloads directly mapped into these bits (the payload could be ATM cells or HDLC packets or any other format) or ATM cells carried within a PLCP frame. If ATM cells are carried within a PLCP frame, their mapping is shown in Figure 62, with the mapping nibble aligned, with each nibble starting after each overhead bit (reference G.804 02/98 7.2, page 7). However, this DS3 block does not require the data to be nibble aligned. FRAMING A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 POI P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 P01 P00 4 bytes POH Z6 Z5 Z4 Z3 Z2 Z1 X B1 G1 X X C1 PLCP PAYLOAD 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53-byte ATM CELL 53 bytes TRAILER 13 OR 14 NIBBLES 5-8325(F)r.4 OBJECT OF BIP-8 CALCULATION Note: A1A2 = F6 28, POI = path overhead indicator, POH = path overhead, and X = unassigned. Figure 62. PLCP Mapping of ATM Cells In PLCP ATM cell mapping, the data bits are organized as twelve rows. Each row consists of two framing bytes, one path overhead indicator byte, one path overhead byte, and one 53-byte ATM cell. The twelfth row also contains a 13 or 14 nibble trailer. 610 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Receive Sequencer (RXS) Block Introduction The receive sequencer extracts the logical channels from SONET time slots. A total of 16 channels may be mapped in to 48 SONET STS-1s. A channel may consist of any arbitrary number of STS-1s in any order. A fully pointer based channel constructor can construct up to 16 channels. Each channel may consist of any number of STS-1s such that the sum of all STS-1s contributing to 16 channels is less than or equal to 48. In addition to packet over SONET (POS) application, the receive sequencer also supports channel construction from packet over fiber (POF), too. Unlike in POS, only a single channel construction is supported in packet over fiber mode. The RXS supports OC-48, OC-12, and OC-3 rates for both POS and POF modes. Note: In OC-3 mode, only time slots 0, 4, and 8 are active in the RXS map registers (Table 681 and Table 682). To use POF in OC-3 mode, it is necessary to provision the RXS maps to assign all 12 time slots from the slice carrying the stream to the intended channel. This is different from normal (non-POF) programming in OC-3 mode. Channel construction information to the receive sequencer is provided through sequence map registers. Two sets of sequence map registers are provided. At any time, one sequence map register is active and the other one is standby. The standby sequence map register may be provisioned for addition of new channels or deletion of old channels. The standby sequence map may be made active by toggling a bit in the RXS control register. A hitless service is guaranteed on all active channels while some other channels are resizing. A sequence map register has three fields. Bit field [11:8] defines the channel ID [0--15] associated with certain time slot in a given slice. Bit field [5:4] defines the slice ID [A--D] associated with a time slot that belongs to the channel id specified in channel id field. Bit field [3:0] defines a time slot [0--11] that is associated with the slice id and the channel ID field. In summary, a sequence map register defines the channel id of any time slot of any slice. The sequence map register is programmed in such a way that the time slots of slices that belong to a particular channel appear in the order at which the channel constituting bytes will be stitched together to form a channel output. Up to 16 channels will be constructed by the RXS. A fair round-robin sequence arbitrator will send out the constructed channels to the data engine. Agere Systems Inc. 611 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Receive Sequencer (RXS) Block (continued) RXS PRBS Monitor Two independent PRBS monitors are provided in the RXS block that monitor the incoming data on a programmable channel ID basis. Within the MARS2G5 P-Pro device, the DS3/E3 block is the source of the PRBS pattern while the RXS PRBS monitor function is a possible sink point for the generated PRBS patterns. Figure 63 shows the location of the PRBS generators and monitors within the device. PT D S 3R X /S E 3 DE Line OHP XC PRBS MON PRBS MON(x2) DS3/E3 UTOPIA SPE PP (PRBS INS) DE Figure 63. MARS2G5 P-Pro PRBS Monitor/Generator Locations The test-pattern monitors contain self-synchronizing detectors that monitor 215 - 1, 220 - 1(QRSS), or 223 - 1 PRBS sequences. These detected sequences can be expected to be inverted or noninverted. When the monitor is out of sync, the device continually monitors the input data for matches to the expected data pattern. When the device detects 32 matches in a row, it declares itself in sync and the error monitor is enabled. If the device detects eight consecutive mismatches, the test-pattern monitor declares itself out of sync and starts searching again. When in sync, the device counts the number of times the input data differs from the expected data in an 8-bit saturating counter. This counter is reset when a 0-to-1 transition is detected on the MPU_READ signal. When the update of the error counter is complete, the MPU_READ_FINISH signal is asserted. Table 684 and Table 686 summarize the PRBS control and status registers, respectively. 612 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Receive Sequencer (RXS) Block (continued) RXS Register Descriptions RXS Global Registers Table 679. (RXSVERSION) Version Control (RO) Address 0x5800 Bit 7:0 Name RXSVERSION[7:0] Function Indicates Version Number of Block. Reset Default 0x01 Table 680. RXS_CONTROL, Receive Sequencer Control Register (R/W) Address 0x5801 Bit 15:12 Name RXS_SL[A--D]_PM Function In OC-3 or OC-12 mode, only one of these bits may be set, corresponding to the slice carrying the ingress stream. Ingress is limited to a single stream for those two modes since RXS can't use multiple clocks. In OC-48 mode, all 4 bits must be set, since all four slices carry data. 0 = Slice [A--D] is off in POF mode. 1 = Slice [A--D] is on in POF mode. 11:10 9:8 -- RXS_MODE Reserved. 00 = Normal DS3 input to RXS. 01 = Reserved. 10 = Fiber input to RXS. 11 = All zero input to RXS. Reserved. 0 = Use X sequence map register as working map. 1 = Use Y sequence map register as working map. Reset Default 0x0000 7:1 0 -- RXS_XY_MAP Agere Systems Inc. 613 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Receive Sequencer (RXS) Block (continued) RXS Register Descriptions (continued) Table 681. RXS_TS[0--11][A--D], X Sequence Map Register (R/W) Note: All unused sequence map registers must be set to 0xFFFF. In OC-3 mode, only time slots 0, 4, and 8 are active. Address 0x5802-- 0x5831 Bit 15:12 11:8 Name -- RXS_CID_TS [0--11][A--D][3:0] -- Reserved. Channel ID [0--15] for TS0--TS11 Slice A--Slice D. These bits in each register of this 48 register bank indicate the channel ID [0--15] of TS[0--11] for slice [A--D]. Reserved. Function Reset Default 0x3F3F 7:6 5:4 RXS_SRCSLICE_TS Source Slice A--Slice D for TS0--TS11 Slice A--Slice D. [0--11][A--D][1:0] These bits assign an input slice [A--D] to a given TS[0--11] in a given slice [A--D]. 00 = D, 01 = C, 10 = B, 11 = A. RXS_SRCTS_TS [0--11][A--D][3:0] Source TS0--TS11 for TS0--TS11 Slice A--Slice D. These bits assign an input TS[0--11] to a given TS[0--11] in a given slice [A--D]. 3:0 Table 682. RYS_TS[0--11][A--D], Y Sequence Map Register (R/W) Note: All unused sequence map registers must be set to 0xFFFF. In OC-3 mode, only time slots 0, 4, and 8 are active. Address 0x5832-- 0x5861 Bit 15:12 11:8 Name -- RYS_CID_TS [0--11][A--D][3:0] -- Reserved. Channel ID [0--15] for TS0--TS11 Slice A--Slice D. These bits in each register of this 48 register bank indicate the channel ID [0--15] of TS[0--11] for slice [A--D]. Reserved. Function Reset Default 0x3F3F 7:6 5:4 RYS_SRCSLICE_TS Source Slice A--Slice D for TS0--TS11 Slice A--Slice [0--11][A--D][1:0] D. These bits assign an input slice [A--D] to a given TS[0-- 11] in a given slice [A--D]. 00 = D, 01 = C, 10 = B, 11 = A. RYS_SRCTS_TS [0--11][A--D][3:0] Source TS0--TS11 for TS0--TS11 Slice A--Slice D. These bits assign an input TS[0--11] to a given TS[0--11] in a given slice [A--D]. 3:0 614 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Receive Sequencer (RXS) Block (continued) RXS Register Descriptions (continued) Table 683. DS3 Support Registers Address 0x5862 Bit 15:12 Name Slice_Match_ Param[15:12] Destination_ TimeSlot_Ptr -- Slice_Match_ Param[9:8] Destination_ Slice_Ptr Slice_Match_ Param[7:4] Source_TimeSlot_ Ptr -- Slice_Match_ Param[1:0] Source_Slice_Ptr Slice_Match_ Inst[15:4] Match_Counter_ Threshold -- Slice_Match_Inst[1] Sample_Match_ Holding_Counter Slice_Match_Inst[0] Slice_Match_ Start_Inst Slice_Match_ Stat[15:4] Sample_Count_ Holding -- Function Destination Time-Slot Pointer. This pointer indicates the destination time slot that will be monitored to accept a new slice at this location. Reserved. Destination-Slice Pointer. This pointer indicates the destination slice that will be monitored to accept a new slice at this location. Source Time-Slot Pointer. This pointer indicates the source time slot that will be monitored to move a slice to a different slice. Reserved. Source-Slice Pointer. This pointer indicates the source slice that will be monitored to move this slice to a different slice. Match-Counter Threshold. This threshold sets the sample match count threshold value. Once sample match counter is equal to or greater than this value, the match status will be set. Reserved. Sample Match Holding Counter. 0 = Keep holding register unchanged. 1 = Sample contents of the sample match counter in to the sample count holding register. Slice Match Start Instruction. 0 = Stop slice match. 1 = Start slice match between time slots and slices specified in Slice_Match_Param. Sample Count Holding Register. Instantaneous slice match counter value can be seen by setting Slice_Match_Inst[1] to 1 followed by setting it to 0. Once Slice_Match_Stat[0] converges, this field is set to the final value of the slice match counter. Reserved. 0x0000 0x7AF5 Reset Default 0x6E7A 11:10 9:8 7:4 3:2 1:0 0x5863 15:4 3:2 1 0 0x5864 15:4 3:1 0 Slice_Match_Stat[0] Slice-Match Status. Slice_Match_Status 0 = Indicates slice mismatch. 1 = Indicates slice match between time slots and slices specified in Slice_Match_Param. Agere Systems Inc. 615 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Receive Sequencer (RXS) Block (continued) RXS Register Descriptions (continued) Table 684. RXS PRBS Control Register for Monitor 1 (R/W) Address 0x5870 Bit 15 Name MPU_CORWN Function Control for alarm signals; controls PRBS status values for both monitors. 1 = Clear-on-read (COR) operation of event registers. 0 = Clear-on-write (COW). 14 13 12 MPU_READ1 -- PRBS_INV1 A 0-to-1 transition on this signal will cause an update to the PRBS_ERRCNT1[7:0] read only register. Reserved. Allows an inverted pattern to be expected. 0 = Normal pattern expected. 1 = Inverted pattern expected. 11:10 9:8 -- PRBS_ PATTERN1[1:0] Reserved. Control signal to select the PRBS pattern expected. 00 = Disable. 01 = 215. 10 = 220. 11 = 223 pattern expected. Reset Default 0x0000 5:0 PRBS_CIDSEL1[5:0] Channel ID to monitor the PRBS sequence. Valid values are 0 to 47, all illegal values disable the PRBS monitor. Table 685. RXS PRBS Control Register for Monitor 2 (R/W) Address 0x5871 Bit 15 14 13 12 Name -- MPU_READ2 -- PRBS_INV2 Reserved. A 0-to-1 transition on this signal will cause an update to the PRBS_ERRCNT2[7:0] read only register. Reserved. Allows an inverted pattern to be expected. 0 = Normal pattern expected. 1 = Inverted pattern expected. 11:10 9:8 -- PRBS_PATTERN2 Reserved. Control signal to select the PRBS pattern expected. 00 = Disable. 01 = 215. 10 = 220. 11 = 223 pattern expected. 5:0 PRBS_CIDSEL2 Channel ID to monitor the PRBS sequence. Valid values are 0 to 47, all illegal values disable the PRBS monitor. Function Reset Default 0x0000 616 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Receive Sequencer (RXS) Block (continued) RXS Register Descriptions (continued) Table 686. RXS PRBS Status Register for Monitor 1 (Mixed) Address 0x5872 Bit 15 14 13 Name SYNC1D (COR/W) SYNC1M (R/W) SYNC1 (RO) Function Delta register to indicate a change of state to the SYNC1 value. Mask register for SYNC1D delta bit. 1 = Masked from contributing to interrupt pin. State register for PRBS monitor. 0 = In-sync. 1 = Out-of-sync. 12 MPU_READ_ FINISH1 (COR/W) -- Active-high event indicating the MPU_READ1 operation is complete. This indicates the PRBS_ERRCNT1[7:0] is stable. This signal must be polled. Reserved. 0 1 Reset Default 0 1 11:8 7:0 0x0 0x00 PRBS_ PRBS saturating error counter. ERRCNT1[7:0] (RO) Table 687. RXS PRBS Status Register for Monitor 2 (Mixed) Address 0x5873 Bit 15 14 13 Name SYNC2D (COR/W) SYNC2M (R/W) SYNC2 (RO) Function Delta register to indicate a change of state to the SYNC2 value. Mask register for SYNC2D delta bit. 1 = Masked from contributing to interrupt pin. State register for PRBS monitor. 0 = In-sync. 1 = Out-of-sync. 12 MPU_READ_ FINISH2 (COR/W) -- Active-high event indicating the MPU_READ2 operation is complete. This indicates the PRBS_ERRCNT2[7:0] is stable. This signal must be polled. Reserved. 0 1 Reset Default 0 0 11:8 7:0 0x0 0x00 PRBS_ PRBS saturating error counter. ERRCNT2[7:0] (RO) Agere Systems Inc. 617 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Receive Sequencer (RXS) Block (continued) RXS Register Maps Table 688. Sequencer Register Map 1 Field Definition Note: All unused sequence map registers must be set to 0xFFFF. Shading denotes reserved bits. Addr 0x5800 0x5801 Symbol RXSVERSION RXS_CONTROL Type RO R/W RXS_SLA_PM RXS_SLB_PM RXS_SLC_PM RXS_SLD_PM RXS_MODE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXSVERSION[7:0] RXS_XY_MAP Time Slot 0 Sequence X Map Register 0x5802 0x5803 0x5804 0x5805 RXS_TS0A RXS_TS0B RXS_TS0C RXS_TS0D R/W R/W R/W R/W RXS_CID_TS0A[3:0] RXS_CID_TS0B[3:0] RXS_CID_TS0C[3:0] RXS_CID_TS0D[3:0] Time Slot 1 Sequence X Map Register 0x5806 0x5807 0x5808 0x5809 RXS_TS1A RXS_TS1B RXS_TS1C RXS_TS1D R/W R/W R/W R/W RXS_CID_TS1A[3:0] RXS_CID_TS1B[3:0] RXS_CID_TS1C[3:0] RXS_CID_TS1D[3:0] Time Slot 2 Sequence X Map Register 0x580A 0x580B 0x580C 0x580D RXS_TS2A RXS_TS2B RXS_TS2C RXS_TS2D R/W R/W R/W R/W RXS_CID_TS2A[3:0] RXS_CID_TS2B[3:0] RXS_CID_TS2C[3:0] RXS_CID_TS2D[3:0] Time Slot 3 Sequence X Map Register 0x580E 0x580F 0x5810 0x5811 RXS_TS3A RXS_TS3B RXS_TS3C RXD_TS3D R/W R/W R/W R/W RXS_CID_TS3A[3:0] RXS_CID_TS3B[3:0] RXS_CID_TS3C[3:0] RXS_CID_TS3D[3:0] Time Slot 4 Sequence X Map Register 0x5812 0x5813 0x5814 0x5815 RXS_TS4A RXS_TS4B RXS_TS4C RXS_TS4D R/W R/W R/W R/W RXS_CID_TS4A[3:0] RXS_CID_TS4B[3:0] RXS_CID_TS4C[3:0] RXS_CID_TS4D[3:0] RXS_SRCSLICE_TS4A[1:0] RXS_SRCSLICE_TS4B[1:0] RXS_SRCSLICE_TS4C[1:0] RXS_SRCSLICE_TS4D[1:0] RXS_SRCTS_TS4A[3:0] RXS_SRCTS_TS4B[3:0] RXS_SRCTS_TS4C[3:0] RXS_SRCTS_TS4D[3:0] RXS_SRCSLICE_TS3A[1:0] RXS_SRCSLICE_TS3B[1:0] RXS_SRCSLICE_TS3C[1:0] RXS_SRCSLICE_TS3D[1:0] RXS_SRCTS_TS3A[3:0] RXS_SRCTS_TS3B[3:0] RXS_SRCTS_TS3C[3:0] RXS_SRCTS_TS3D[3:0] RXS_SRCSLICE_TS2A[1:0] RXS_SRCSLICE_TS2B[1:0] RXS_SRCSLICE_TS2C[1:0] RXS_SRCSLICE_TS2D[1:0] RXS_SRCTS_TS2A[3:0] RXS_SRCTS_TS2B[3:0] RXS_SRCTS_TS2C[3:0] RXS_SRCTS_TS2D[3:0] RXS_SRCSLICE_TS1A[1:0] RXS_SRCSLICE_TS1B[1:0] RXS_SRCSLICE_TS1C[1:0] RXS_SRCSLICE_TS1D[1:0] RXS_SRCTS_TS1A[3:0] RXS_SRCTS_TS1B[3:0] RXS_SRCTS_TS1C[3:0] RXS_SRCTS_TS1D[3:0] RXS_SRCSLICE_TS0A[1:0] RXS_SRCSLICE_TS0B[1:0] RXS_SRCSLICE_TS0C[1:0] RXS_SRCSLICE_TS0D[1:0] RXS_SRCTS_TS0A[3:0] RXS_SRCTS_TS0B[3:0] RXS_SRCTS_TS0C[3:0] RXS_SRCTS_TS0D[3:0] 618 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Receive Sequencer (RXS) Block (continued) RXS Register Maps (continued) Table 688. Sequencer Register Map 1 Field Definition (continued) Note: All unused sequence map registers must be set to 0xFFFF. Shading denotes reserved bit. Addr Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Time Slot 5 Sequence X Map Register 0x5816 0x5817 0x5818 0x5819 RXS_TS5A RXS_TS5B RXS_TS5C RXS_TS5D R/W R/W R/W R/W RXS_CID_TS5A[3:0] RXS_CID_TS5B[3:0] RXS_CID_TS5C[3:0] RXS_CID_TS5D[3:0] Time Slot 6 Sequence X Map Register 0x581A 0x581B 0x581C 0x581D RXS_TS6A RXS_TS6B RXS_TS6C RXS_TS6D R/W R/W R/W R/W RXS_CID_TS6A[3:0] RXS_CID_TS6B[3:0] RXS_CID_TS6C[3:0] RXS_CID_TS6D[3:0] Time Slot 7 Sequence X Map Register 0x581E 0x581F 0x5820 0x5821 RXS_TS7A RXS_TS7B RXS_TS7C RXS_TS7D R/W R/W R/W R/W RXS_CID_TS7A[3:0] RXS_CID_TS7B[3:0] RXS_CID_TS7C[3:0] RXS_CID_TS7D[3:0] Time Slot 8 Sequence X Map Register 0x5822 0x5823 0x5824 0x5825 RXS_TS8A RXS_TS8B RXS_TS8C RXS_TS8D R/W R/W R/W R/W RXS_CID_TS8A[3:0] RXS_CID_TS8B[3:0] RXS_CID_TS8C[3:0] RXS_CID_TS8D[3:0] Time Slot 9 Sequence X Map Register 0x5826 0x5827 0x5828 0x5829 RXS_TS9A RXS_TS9B RXS_TS9C RXS_TS9D R/W R/W R/W R/W RXS_CID_TS9A[3:0] RXS_CID_TS9B[3:0] RXS_CID_TS9C[3:0] RXS_CID_TS9D[3:0] Time Slot 10 Sequence X Map Register 0x582A 0x582B 0x582C 0x582D RXS_TS10A RXS_TS10B RXS_TS10C RXS_TS10D R/W R/W R/W R/W RXS_CID_TS10A[3:0] RXS_CID_TS10B[3:0] RXS_CID_TS10C[3:0] RXS_CID_TS10D[3:0] RXS_SRCSLICE_TS10A[1:0] RXS_SRCSLICE_TS10B[1:0] RXS_SRCSLICE_TS10C[1:0] RXS_SRCSLICE_TS10D[1:0] RXS_SRCTS_TS10A[3:0] RXS_SRCTS_TS10B[3:0] RXS_SRCTS_TS10C[3:0] RXS_SRCTS_TS10D[3:0] RXS_SRCSLICE_TS9A[1:0] RXS_SRCSLICE_TS9B[1:0] RXS_SRCSLICE_TS9C[1:0] RXS_SRCSLICE_TS9D[1:0] RXS_SRCTS_TS9A[3:0] RXS_SRCTS_TS9B[3:0] RXS_SRCTS_TS9C[3:0] RXS_SRCTS_TS9D[3:0] RXS_SRCSLICE_TS8A[1:0] RXS_SRCSLICE_TS8B[1:0] RXS_SRCSLICE_TS8C[1:0] RXS_SRCSLICE_TS8D[1:0] RXS_SRCTS_TS8A[3:0] RXS_SRCTS_TS8B[3:0] RXS_SRCTS_TS8C[3:0] RXS_SRCTS_TS8D[3:0] RXS_SRCSLICE_TS7A[1:0] RXS_SRCSLICE_TS7B[1:0] RXS_SRCSLICE_TS7C[1:0] RXS_SRCSLICE_TS7D[1:0] RXS_SRCTS_TS7A[3:0] RXS_SRCTS_TS7B[3:0] RXS_SRCTS_TS7C[3:0] RXS_SRCTS_TS7D[3:0] RXS_SRCSLICE_TS6A[1:0] RXS_SRCSLICE_TS6B[1:0] RXS_SRCSLICE_TS6C[1:0] RXS_SRCSLICE_TS6D[1:0] RXS_SRCTS_TS6A[3:0] RXS_SRCTS_TS6B[3:0] RXS_SRCTS_TS6C[3:0] RXS_SRCTS_TS6D[3:0] RXS_SRCSLICE_TS5A[1:0] RXS_SRCSLICE_TS5B[1:0] RXS_SRCSLICE_TS5C[1:0] RXS_SRCSLICE_TS5D[1:0] RXS_SRCTS_TS5A[3:0] RXS_SRCTS_TS5B[3:0] RXS_SRCTS_TS5C[3:0] RXS_SRCTS_TS5D[3:0] Agere Systems Inc. 619 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Receive Sequencer (RXS) Block (continued) RXS Register Maps (continued) Table 688. Sequencer Register Map 1 Field Definition (continued) Note: All unused sequence map registers must be set to 0xFFFF. Shading denotes reserved bits. Addr Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Time Slot 11 Sequence X Map Register 0x582E 0x582F 0x5830 0x5831 RXS_TS11A RXS_TS11B RXS_TS11C RXS_TS11D R/W R/W R/W R/W RXS_CID_TS11A[3:0] RXS_CID_TS11B[3:0] RXS_CID_TS11C[3:0] RXS_CID_TS11D[3:0] Time Slot 0 Sequence Y Map Register 0x5832 0x5833 0x5834 0x5835 RYS_TS0A RYS_TS0B RYS_TS0C RYS_TS0D R/W R/W R/W R/W RYS_CID_TS0A[3:0] RYS_CID_TS0B[3:0] RYS_CID_TS0C[3:0] RYS_CID_TS0D[3:0] Time Slot 1 Sequence Y Map Register 0x5836 0x5837 0x5838 0x5839 RYS_TS1A RYS_TS1B RYS_TS1C RYS_TS1D R/W R/W R/W R/W RYS_CID_TS1A[3:0] RYS_CID_TS1B[3:0] RYS_CID_TS1C[3:0] RYS_CID_TS1D[3:0] Time Slot 2 Sequence Y Map Register 0x583A 0x583B 0x583C 0x583D RYS_TS2A RYS_TS2B RYS_TS2C RYS_TS2D R/W R/W R/W R/W RYS_CID_TS2A[3:0] RYS_CID_TS2B[3:0] RYS_CID_TS2C[3:0] RYS_CID_TS2D[3:0] Time Slot 3 Sequence Y Map Register 0x583E 0x583F 0x5840 0x5841 RYS_TS3A RYS_TS3B RYS_TS3C RYS_TS3D R/W R/W R/W R/W RYS_CID_TS3A[3:0] RYS_CID_TS3B[3:0] RYS_CID_TS3C[3:0] RYS_CID_TS3D[3:0] Time Slot 4 Sequence Y Map Register 0x5842 0x5843 0x5844 0x5845 RYS_TS4A RYS_TS4B RYS_TS4C RYS_TS4D R/W R/W R/W R/W RYS_CID_TS4A[3:0] RYS_CID_TS4B[3:0] RYS_CID_TS4C[3:0] RYS_CID_TS4D[3:0] RYS_SRCSLICE_TS4A[1:0] RYS_SRCSLICE_TS4B[1:0] RYS_SRCSLICE_TS4C[1:0] RYS_SRCSLICE_TS4D[1:0] RYS_SRCTS_TS4A[3:0] RYS_SRCTS_TS4B[3:0] RYS_SRCTS_TS4C[3:0] RYS_SRCTS_TS4D[3:0] RYS_SRCSLICE_TS3A[1:0] RYS_SRCSLICE_TS3B[1:0] RYS_SRCSLICE_TS3C[1:0] RYS_SRCSLICE_TS3D[1:0] RYS_SRCTS_TS3A[3:0] RYS_SRCTS_TS3B[3:0] RYS_SRCTS_TS3C[3:0] RYS_SRCTS_TS3D[3:0] RYS_SRCSLICE_TS2A[1:0] RYS_SRCSLICE_TS2B[1:0] RYS_SRCSLICE_TS2C[1:0] RYS_SRCSLICE_TS2D[1:0] RYS_SRCTS_TS2A[3:0] RYS_SRCTS_TS2B[3:0] RYS_SRCTS_TS2C[3:0] RYS_SRCTS_TS2D[3:0] RYS_SRCSLICE_TS1A[1:0] RYS_SRCSLICE_TS1B[1:0] RYS_SRCSLICE_TS1C[1:0] RYS_SRCSLICE_TS1D[1:0] RYS_SRCTS_TS1A[3:0] RYS_SRCTS_TS1B[3:0] RYS_SRCTS_TS1C[3:0] RYS_SRCTS_TS1D[3:0] RYS_SRCSLICE_TS0A[1:0] RYS_SRCSLICE_TS0B[1:0] RYS_SRCSLICE_TS0C[1:0] RYS_SRCSLICE_TS0D[1:0] RYS_SRCTS_TS0A[3:0] RYS_SRCTS_TS0B[3:0] RYS_SRCTS_TS0C[3:0] RYS_SRCTS_TS0D[3:0] RXS_SRCSLICE_TS11A[1:0] RXS_SRCSLICE_TS11B[1:0] RXS_SRCSLICE_TS11C[1:0] RXS_SRCSLICE_TS11D[1:0] RXS_SRCTS_TS11A[3:0] RXS_SRCTS_TS11B[3:0] RXS_SRCTS_TS11C[3:0] RXS_SRCTS_TS11D[3:0] 620 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Receive Sequencer (RXS) Block (continued) RXS Register Maps (continued) Table 688. Sequencer Register Map 1 Field Definition (continued) Note: All unused sequence map registers must be set to 0xFFFF. Shading denotes reserved bits. Addr Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Time Slot 5 Sequence Y Map Register 0x5846 0x5847 0x5848 0x5849 RYS_TS5A RYS_TS5B RYS_TS5C RYS_TS5D R/W R/W R/W R/W RYS_CID_TS5A[3:0] RYS_CID_TS5B[3:0] RYS_CID_TS5C[3:0] RYS_CID_TS5D[3:0] Time Slot 6 Sequence Y Map Register 0x584A 0x584B 0x584C 0x584D RYS_TS6A RYS_TS6B RYS_TS6C RYS_TS6D R/W R/W R/W R/W RYS_CID_TS6A[3:0] RYS_CID_TS6B[3:0] RYS_CID_TS6C[3:0] RYS_CID_TS6D[3:0] Time Slot 7 Sequence Y Map Register 0x584E 0x584F 0x5850 0x5851 RYS_TS7A RYS_TS7B RYS_TS7C RYS_TS7D R/W R/W R/W R/W RYS_CID_TS7A[3:0] RYS_CID_TS7B[3:0] RYS_CID_TS7C[3:0] RYS_CID_TS7D[3:0] Time Slot 8 Sequence Y Map Register 0x5852 0x5853 0x5854 0x5855 RYS_TS8A RYS_TS8B RYS_TS8C RYS_TS8D R/W R/W R/W R/W RYS_CID_TS8A[3:0] RYS_CID_TS8B[3:0] RYS_CID_TS8C[3:0] RYS_CID_TS8D[3:0] Time Slot 9 Sequence Y Map Register 0x5856 0x5857 0x5858 0x5859 RYS_TS9A RYS_TS9B RYS_TS9C RYS_TS9D R/W R/W R/W R/W RYS_CID_TS9A[3:0] RYS_CID_TS9B[3:0] RYS_CID_TS9C[3:0] RYS_CID_TS9D[3:0] Time Slot 10 Sequence Y Map Register 0x585A 0x585B 0x585C 0x585D RYS_TS10A RYS_TS10B RYS_TS10C RYS_TS10D R/W R/W R/W R/W RYS_CID_TS10A[3:0] RYS_CID_TS10B[3:0] RYS_CID_TS10C[3:0] RYS_CID_TS10D[3:0] RYS_SRCSLICE_TS10A[1:0] RYS_SRCSLICE_TS10B[1:0] RYS_SRCSLICE_TS10C[1:0] RYS_SRCSLICE_TS10D[1:0] RYS_SRCTS_TS10A[3:0] RYS_SRCTS_TS10B[3:0] RYS_SRCTS_TS10C[3:0] RYS_SRCTS_TS10D[3:0] RYS_SRCSLICE_TS9A[1:0] RYS_SRCSLICE_TS9B[1:0] RYS_SRCSLICE_TS9C[1:0] RYS_SRCSLICE_TS9D[1:0] RYS_SRCTS_TS9A[3:0] RYS_SRCTS_TS9B[3:0] RYS_SRCTS_TS9C[3:0] RYS_SRCTS_TS9D[3:0] RYS_SRCSLICE_TS8A[1:0] RYS_SRCSLICE_TS8B[1:0] RYS_SRCSLICE_TS8C[1:0] RYS_SRCSLICE_TS8D[1:0] RYS_SRCTS_TS8A[3:0] RYS_SRCTS_TS8B[3:0] RYS_SRCTS_TS8C[3:0] RYS_SRCTS_TS8D[3:0] RYS_SRCSLICE_TS7A[1:0] RYS_SRCSLICE_TS7B[1:0] RYS_SRCSLICE_TS7C[1:0] RYS_SRCSLICE_TS7D[1:0] RYS_SRCTS_TS7A[3:0] RYS_SRCTS_TS7B[3:0] RYS_SRCTS_TS7C[3:0] RYS_SRCTS_TS7D[3:0] RYS_SRCSLICE_TS6A[1:0] RYS_SRCSLICE_TS6B[1:0] RYS_SRCSLICE_TS6C[1:0] RYS_SRCSLICE_TS6D[1:0] RYS_SRCTS_TS6A[3:0] RYS_SRCTS_TS6B[3:0] RYS_SRCTS_TS6C[3:0] RYS_SRCTS_TS6D[3:0] RYS_SRCSLICE_TS5A[1:0] RYS_SRCSLICE_TS5B[1:0] RYS_SRCSLICE_TS5C[1:0] RYS_SRCSLICE_TS5D[1:0] RYS_SRCTS_TS5A[3:0] RYS_SRCTS_TS5B[3:0] RYS_SRCTS_TS5C[3:0] RYS_SRCTS_TS5D[3:0] Agere Systems Inc. 621 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Receive Sequencer (RXS) Block (continued) RXS Register Maps (continued) Table 688. Sequencer Register Map 1 Field Definition (continued) Note: All unused sequence map registers must be set to 0xFFFF. Shading denotes reserved bits. Addr Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Time Slot 11 Sequence Y Map Register 0x585E 0x585F 0x5860 0x5861 RYS_TS11A RYS_TS11B RYS_TS11C RYS_TS11D R/W R/W R/W R/W RYS_CID_TS11A[3:0] RYS_CID_TS11B[3:0] RYS_CID_TS11C[3:0] RYS_CID_TS11D[3:0] RYS_SRCSLICE_TS11A[1:0] RYS_SRCSLICE_TS11B[1:0] RYS_SRCSLICE_TS11C[1:0] RYS_SRCSLICE_TS11D[1:0] RYS_SRCTS_TS11A[3:0] RYS_SRCTS_TS11B[3:0] RYS_SRCTS_TS11C[3:0] RYS_SRCTS_TS11D[3:0] Table 689. Sequencer Register Map 2 Field Definition Addr Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DS3 Support Registers 0x5862 0x5863 Slice_Match_Para Slice_Match_Inst R/W R/W Destination Time-Slot Pointer Destination Slice Pointer Match Counter Threshold Source Time-Slot Pointer Source Slice Pointer Sample Match Holding Counter Slice Match Start Instruction Slice Match Status 0x5864 Slice_Match_Stat R Sample Count Holding PRBS Control Registers 0x5870 0x5871 PRBS Control Reg1 PRBS Control Reg2 R/W R/W MPU_ CORWN MPU_ READ1 MPU_ READ2 PRBS_ INV1 PRBS_ INV2 PRBS_PATTERN1[1:0] PRBS_PATTERN2[1:0] PRBS Status Registers 0x5872 PRBS Status Reg1 Mixed SYNC1D SYNC1M (COR/W) (R/W) SYNC1 (RO) MPU_ READ_ FINISH1 (COR/W) MPU_ READ_ FINISH2 (COR/W) PRBS_ERRCNT1[7:0] (RO) PRBS_CIDSEL1[5:0] PRBS_CIDSEL2[5:0] 0x5873 PRBS Status Reg2 Mixed SYNC2D SYNC2M (COR/W) (R/W) SYNC2 (RO) PRBS_ERRCNT2[7:0] (RO) 622 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block The data engine block interfaces with the UTOPIA (UT) Block on page 716 and the DS3/E3 Block on page 486. Data Engine Block--Subblocks The data engine consists of six major subblocks: 1. 2. 3. 4. 5. 6. Data Engine Block--ATM Framer/Frame Inserter Subblock on page 624. Data Engine Block--CRC Generator/Checker Subblock on page 636. Data Engine Block--CRC Generator/Checker Subblock on page 636. Data Engine Block--PPP Detach Subblock on page 645. Data Engine Block--Data Engine Counter Subblock on page 648. Data Engine Block--Channel Distribution and Allocation Subblock on page 651. Agere Systems Inc. 623 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--ATM Framer/Frame Inserter Subblock Overview The purpose of the ATM framer is to delineate incoming cell boundaries. Conversely, the purpose of the frame inserter is to insert the HEC field in the header. This is used in ATM mode. In Figure 64, an ATM cell is shown. HEADER H0 H1 H2 H3 HEC PAYLOAD D0--D47 5-8290(F) Figure 64. ATM Cell Format The basic idea with HEC framing is that the framer slides along on a bit-by-bit or byte-by-byte basis and checks for 5 bytes where the fifth byte is the HEC for the first 4. Capabilities Number of Channels The ATM framer/frame inserter supports 16 channels. HEC Framing In ATM mode, ATM framing is done on the incoming ATM streams using the alpha-delta framer state machine specified in I.432. Frame hunt is done on a byte-by-byte basis, except in cell UNI mode, where it is done on a perbit basis. 624 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--ATM Framer/Frame Inserter Subblock (continued) Capabilities (continued) Data Passing Data is not passed unless the framer is in the synchronized state. Cell-Based UNI The ATM framer supports a cell-based UNI for ATM mode (as per I.432) when PayloadControl[7] = 1. In this mode, HEC framing is done on a per-bit basis. This implies that frame detection is required over 32 different positions for the incoming bit stream. HEC The ATM framer/frame inserter generates and checks HEC fields for ATM cells. The HEC field is the fifth byte in the ATM cell. The HEC is used to detect bit errors and correct single bit errors in the ATM cell header. The HEC field is filled with the value of a CRC calculation, which is performed over the first 4 bytes of the header. The HEC field contains the ones complement sum (modulo 2) of: The remainder of the division (modulo 2) by the generator polynomial of the product of x8 by the information in the first 4 bytes of the ATM cell. 0x55 The HEC generator polynomial is g(x) = x8 + x2 + x + 1 The result of the CRC calculation is placed with the least significant bit right justified in the HEC field. HEC Errors Cells with header errors are handled in I.432 compliance when the channel's Rx payload control register is configured for smart discard. In this mode, a single-bit header error is corrected, and the cell is passed to the UTOPIA block, as long as the error occurs in isolation. If two or more cells in a row have single-bit errors, only the first will be passed to the UTOPIA block. All cells with multiple header errors are discarded. Two less restrictive modes are also provided. In discard mode, all single-bit errors are corrected and passed to the UTOPIA block. In no discard mode, all received cells are passed to the UTOPIA bus. No corrections are made. Discard mode selection does not affect the alpha-delta framer, which operates on the raw data prior to any error correction. The framer will transition to hunt, and data delivery will stop, once alpha consecutive errored cell headers have been received. Idle/Unassigned Cells The ATM framer generates idle cells when there are no user cells available, and discards these cells in the receive direction. Agere Systems Inc. 625 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--ATM Framer/Frame Inserter Subblock (continued) Architecture HEC Framer Following this is a HEC framer. This circuit hunts for the frame in 1 of 4 or 1 of 32 possible positions (depending on whether the channel is in bit sync or byte sync modes). The framer follows a state machine as shown in Figure 65. Here, the first hit causes a transition to the presync state, and after delta consecutive hits on the HEC (spaced 53 bytes apart), the framer state moves to the sync state. At this point, data is allowed to pass through. DELTA HITS PRESYNC HIT BEFORE DELTA HITS FAILURE BEFORE DELTA HITS FIRST HIT ALPHA MISSES SYNCHRONIZED MISS BEFORE ALPHA MISSES HUNT BIT/BYTE HUNT MISS 5-8294(F)r.1 Figure 65. Alpha-Delta Framer State Machine 626 Agere Systems Inc. Data Sheet August 19, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--HDLC Framer and Escaper Subblock Introduction This section provides a description of the HDLC framer and escaper subblock of the DE-48. The framer operates on received (ingress) data while the escaper operates on transmitted (egress) data. Data bytes are tagged with a channel number indicating the logical channel with which the data is associated. The HDLC framer and escaper supports up to 16 independent channels. The HDLC framer can be provisioned on a per-channel basis to operate in either byte-synchronous or bit-synchronous mode. In byte-synchronous mode, the HDLC framer and escaper operates as described in RFC1662, Section 4 and ISO(R)/IEC(R) 3309 Section 4.5.2.2. In bit-synchronous mode, the HDLC framer and escaper operates as described in RFC1662, Section 5, and ISO/IEC 3309 Section 4.5.1. Features The HDLC framer/escaper supports 16 channels. The HDLC framer/escaper operates on the following payload types as indicated by the PayloadType[2:0] bits found in Table 740, Tx Payload Type and Control (R/W) on page 698 and Table 741, Tx Payload Type and Payload Control Summary Table on page 699. No other payload types will be passed through: -- PPP--PayloadType[2:0] = 0x0. -- CRC--PayloadType[2:0] = 0x1. -- HDLC--PayloadType[2:0] = 0x2. -- Transparent Payload--PayloadType[2:0] = 0x6. The HDLC framer/escaper supports X43 + 1 scrambling and descrambling. The post-scrambling and unscrambling mode operates on the entire datastream, including flags, in compliance with RFC2615. An optional prescrambling mode operates on packet data and FCS only, before HDLC escaping and flag insertion. Agere Systems Inc. 627 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--HDLC Framer and Escaper Subblock (continued) Byte-Synchronous Mode In Byte-Synchronous mode, the HDLC framer delineates incoming packet boundaries, and unescapes escaped characters within a packet. HDLC escaper inserts HDLC flags at packet boundaries and escapes any 0x7D and 0x7E characters within a packet. This is used in PPP, HDLC, and CRC modes. Packet Boundaries The escaper marks the beginning and end of packets with the flag byte 0x7E. Escaping Bytes within a packet are escaped to hide occurrences of the value 0x7D and 0x7E. Escaping is done on a byte basis with 0x7E being escaped to 0x7D5E, and 0x7D being escaped to 0x7D5D. Interpacket Fill The HDLC escaper for PPP, CRC, and HDLC modes use the HDLC flag 0x7E as the fill character between packets, with at least one 0x7E inserted between packets. Abort The HDLC escaper for PPP, CRC, and HDLC modes mark abort end-of-packets with 0x7D7E. Escaper Dry Mode (Intra-Packet Fill) The HDLC escaper for PPP, CRC, and HDLC modes provide stuffing for dry periods with 0x7D20 (NUL) if dry mode is enabled (PayloadControl[2] = 1). Otherwise, the abort sequences written (0x7D7E). Framer Dry Mode The HDLC framer for PPP, CRC, and HDLC modes only support dry compression if dry mode is provisioned (PayloadControl[2] = 1). Otherwise the framer provide normal unescaping on the 0x7D20 sequence resulting in 0x00. Unescaping Unescaping for PPP, CRC, and HDLC modes is performed on all characters preceded by a 0x7D except 0x7E, and 0x20 if dry mode is enabled (see previous requirement). Unescaping any sequence outside of 0x7D5D and 0x7D5E will result in an error. Packet Size The HDLC framer for PPP, CRC, and HDLC modes will discard any packets less than four bytes in length. Framer Transparent Payload For transparent payload, the HDLC framer (beyond matching the delay through this block) will do nothing except translate the FrameMarker[2:0] signal into EOPMarker[3:0]. 628 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Examples of Byte-Synchronous Mode Escaper Operation The examples shown below illustrate the operation of the byte-synchronous HDLC escaper. The first line represents the unencoded data to be transmitted, and the second line illustrates the required output from the escaper. Flag, dry, and abort bytes are drawn using patterns illustrated in the legend below. PAYLOAD BYTE BLANK BYTE 7E FLAG BYTE 7D 20 DRY FILL SEQUENCE 7D 7E ABORT SEQUENCE 7D XX ESCAPED BYTE 5-8308(F) Figure 66. Legend for Escaper Examples EOP y z SOP a b 7E d 7D 7D EOP g SOP a b c y z 7E 7E a b 7D 5E d 7D 5D 7D 5D g 7E a b 5-8309(F) Figure 67. Escaping and EOP Agere Systems Inc. 629 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--HDLC Framer and Escaper Subblock (continued) Examples of Byte-Synchronous Mode Escaper Operation (continued) DRY 7E f g h 7E j k ABORT 7D 7D 5E f 7D 20 7D 20 7D 20 g h 7D 5E j k 7D 5D 7D 7E 7E 5-8310(F) Figure 68. Escaping Dry and Abort DRY 7E f ABORT 7D b c 7D 5E f 7D 20 7D 20 7D 7E 7E 7E 7E 7E 7D 5D b c 5-8311(F) Figure 69. Aborting a Dry 630 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--HDLC Framer and Escaper Subblock (continued) Examples of Byte-Synchronous Mode Framer Operation The examples shown below illustrate the operation of the byte-synchronous HDLC framer. The first line represents the received encoded data, and the second line illustrates the packed output of the framer. Flag, dry, and abort bytes are drawn using patterns as in the figures above. y z 7E 7E a b 7D 5E d 7D 5D 7D 5D g 7E a b c y z EOP a SOP b 7E d 7D 7D g EOP a SOP b c 5-8312(F) Figure 70. Framing and EOP 7D 5e f 7D 20 7D 20 7D 20 g h 7D 5E j k 7D 5D 7D 7E 7E 7E f g h 7E j k 7D ABORT 5-8313(F)r.1 Figure 71. Framing Dry and Abort 7D 5e f 7D 20 7D 20 7D 20 7D 7E 7E 7E 7D 5D b c d e 7E f ABORT 7D SOP b c 5-8314(F) Figure 72. Aborting a Dry Agere Systems Inc. 631 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--HDLC Framer and Escaper Subblock (continued) Bit-Synchronous Mode In bit-synchronous mode, the HDLC framer delineates incoming packet boundaries and removes bit-stuffing within a packet. HDLC escaper inserts HDLC flags at packet boundaries and performs bit-stuffing within a packet following each sequence of five ones 11111. Bit-synchronous HDLC mode supports transmission and reception of PPP traffic carried within a DS3 payload. Packet Boundaries The escaper marks the beginning and end of packets by inserting the HDLC flag 0x7E (01111110). The device can be configured to insert one to four flags between packets. Additional fill will be inserted beyond the provisioned number of flags if the start of the next packet is not available yet. Payload Size Prior to bit-stuffing, transmitted packets consist of an integral number of bytes (octets). Bit Order Within a Byte Bits can be sent least significant bit first to most significant bit on a byte-by-byte basis. Or most significant bit first to least significant bit, again on a byte-by-byte basis. Stuffing The escaper inserts (stuffs) a 0 bit following each occurrence of five consecutive 1s in a packet. Interpacket Fill The bitmode HDLC escaper can transmit either HDLC flags or all 1s as fill between packets when the start of the next packet is not yet available. When the all 1s pattern is selected, the escaper will bracket the fill with two to four HDLC flags. How these are allocated depends on the provisioned number of flags between packets and, if that number is three, on the leading/trailing setting: One or two flags--one flag before the fill and one after. Three flags, leading--two flags before the fill and one after. Three flags, trailing--one flag before the fill and two after. Four flags--two flags before the fill and two after. Abort Abort is transmitted by the escaper as a sequence of seven or more consecutive ones. Abort is recognized by the framer as a sequence of seven or more consecutive ones. 632 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--HDLC Framer and Escaper Subblock (continued) Bit-Synchronous Mode (continued) Dry Mode (Intrapacket Fill) Dry mode is not supported. Escaper Transparent Payload Transparent payload is not supported. Unstuffing Within a packet (between flag bytes), the HDLC framer removes zero bits stuffed by the transmitter. To do this, it replaces all occurrences of the bit string 111110 with 11111. Framer Bit Alignment After unstuffing, the framer packs the message bits into bytes. The first bit of a received packet is aligned with the first bit of a byte. Unstuffed Packet Size After unstuffing, a packet consists of an integral number of bytes. Agere Systems Inc. 633 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--HDLC Framer and Escaper Subblock (continued) Examples of Bit-Synchronous Mode Framer Operation The examples shown below illustrate the operation of the bit-synchronous HDLC framer. The first line represents the received encoded data, and the second line illustrates the packed output of the framer. A B C D 9F B7 D8 F8 A B C D 79 F7 C9 F8 1001111 1101101111101100011111000011110011111011111001001111110 FLAG DF C7 C7 9F A B C D FA DF C7 C7 9F 5-8315(F) Figure 73. Bit-Synchronous HDLC Framer Operation A B C D 9F B7 D8 F8 A B C D 7F FF FD F8 10011111101101111101100011111000011111111111111111111101111110 ABORT FLAG DF C7 C7 A B C D DF C7 C7 XX 5-8316(F) Figure 74. Bit-Synchronous HDLC Abort 634 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--HDLC Framer and Escaper Subblock (continued) Examples of Bit-Synchronous Mode Escaper Operation The examples shown below illustrate the operation of the bit-synchronous HDLC escaper. The first line represents the received encoded data and the second line illustrates the packed output of the escaper. FA E3 E3 79 A B C D A B C D 7C(EOP) XX XX XX 01111110111110010111000111110000110111100101111100001111110 7E F9 71 F0 A B C D DE 5F 0F CF 5-8317(F)r.1 Figure 75. Bit-Synchronous HDLC Escaper Operation FA E3 E3 79 A B C D A B C D ABORT XX XX XX 011111101111100101110001111100001101111001111111110111111001111110 7E F9 71 F0 A B C D DE 7F DF 9F 5-8318(F)r.1 Figure 76. Bit-Synchronous HDLC Escaper Abort Agere Systems Inc. 635 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--CRC Generator/Checker Subblock Overview The purpose of the CRC-16/32 generator and checker is to generate and check CRC-16/32 frame check sequences on data that is being received and transmitted through the data engine on multiple channels. This is used in PPP and CRC modes. Receive The CRC checker circuit is required to check a 16-bit and 32-bit CRC. In order to flag the end of the packet (2 or 4 bytes prior) as bad or OK, it is necessary to store the previous word before checking the CRC. Based on the fact that the data is arriving 4 bytes at a time, and the minimum CRC is 2 bytes, it is desirable to check the CRC by calculating the CRC in the same fashion as generating it: namely, calculate the CRC over the packet data and compare it to the incoming CRC bytes. This situation is shown in Figure 77. Here, the CRC-16 would be calculated up to byte C in the first word, and compared to bytes D and A. If the calculated CRC matches, the EOP marker will be set either to byte C of the first word (if the CRC is supposed to be removed) or byte A of the second word (if the CRC is supposed to remain attached). Otherwise, the BadMarker will be pointed on the byte where the EOP marker was received. TIME INPUT TO CRC A B C D A B C D FIRST PACKET EOP START OF NEXT PACKET BLANK FROM 0x7E HDLC FLAG PACKET BYTES CRC-16 BYTES TIME OUTPUT FROM CRC CRC KEPT A B C D A B C D PLACE EOP TIME A B C D A B C D CRC REMOVED PLACE EOP 5-8276(F)r.1 Figure 77. CRC-16 Checker Data Arriving Across Two Words 636 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--CRC Generator/Checker Subblock (continued) Receiver (continued) There can also be 32-bit CRCs. In general, the scheme is the same, but if the CRC is to be removed, the EOP marker will need to be shifted 4 bytes instead of two. Refer to Figure 78. TIME INPUT TO CRC A B C D A B C D FIRST PACKET EOP START OF NEXT PACKET BLANK FROM 0x7E HDLC FLAG PACKET BYTES CRC-32 BYTES TIME OUTPUT FROM CRC CRC KEPT A B C D A B C D PLACE EOP TIME A B C D A B C D CRC REMOVED PLACE EOP 5-8277(F)r.1 Figure 78. CRC-32 Check Arriving Across Two Words Note: When the EOP marker is shifted to strip the CRC, the payload markers that indicate valid data for the CRC values are now set low. For CRC-16, two payload markers are set low. For CRC-32, that number is four. Agere Systems Inc. 637 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--CRC Generator/Checker Subblock (continued) Receiver (continued) REGISTER FILE STATE REGISTER FILE PREVIOUS BYTES ABCD[31:0] ABCD[31:0] CRC RUNNING 5-8279(F) Figure 79. A CRC-16/32 Checker Circuit Here, the previous bytes are stored, and a combinatorial logic circuit calculates the running CRC, and when the EOP marker arrives, it compares the CRC with the 2 or 4 bytes before the EOP marker. Based on the results of this, the EOP marker or bad marker is set at the new end of packet. 638 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--CRC Generator/Checker Subblock (continued) Transmit In the transmit direction, the EOP marker is moved 2 to 4 bytes backwards, so the previous bytes are not required. Here, the running CRC is calculated, and when the end of packet is found, the CRC bytes are inserted and the EOP marker moved. The figure below shows the treatment of incoming bytes into the CRC generator. The general premise is that the CRC generator logic searches for the EOP marker and attaches its calculated value directly after the EOP. The block must also shift the EOP marker by 2 or 4 bytes and must set high the payload markers corresponding to the CRC bytes high. TIME INPUT TO CRC A B C D A B C D FIRST PACKET EOP START OF NEXT PACKET PACKET BYTES CRC-16/CRC-32 BYTES BLANK BYTES TIME OUTPUT FROM CRC A B CRC-32 CASE A B C D C D PLACE EOP READ IN FROM STORAGE TIME A B C D A B C D CRC-16 CASE PLACE EOP 5-8280(F) Figure 80. Normal CRC-16 and CRC-32 Cases For HDLC-type packets, there should still be at least one byte of spacing between packets for the insertion of the HDLC blank flag (0x7E). Agere Systems Inc. 639 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--CRC Generator/Checker Subblock (continued) Transmit (continued) The CRC generator also searches for an implied start of packet. An implied start of packet corresponds to the first valid byte (payload marker bit is high) following an end of packet. Upon an implied start of packet, the CRC value is defaulted to 0xFFFFFFFF(or 0xFFFF for CRC-16) and the calculation restarts. Figure 81 shows the block diagram of the CRC generator. REGISTER FILE STATE ABCD[31:0] CRC ABCD[31:0] RUNNING 5-8281(F)r.1 Figure 81. CRC Generator Block Diagram 640 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--CRC Generator/Checker Subblock (continued) Examples of CRC Insertion/Testing This section, describes the different cases on the CRC transmit side. The figure below shows several cases with varying positions for the EOP marker. INPUT TO CRC TIME INSERTED CRC BYTES A B C D A B C D BLANK BYTES PAYLOAD MARKER EOP MARKER OUTPUT FROM CRC B C D CRC-32 CASE PACKET BYTES TIME A PAYLOAD MARKER EOP MARKER TIME A PAYLOAD MARKER EOP MARKER B C D A B C D B C D A OUTPUT FROM CRC CRC-16 CASE 5-8282(F) INPUT TO CRC TIME A B C D A B C D PAYLOAD MARKER EOP MARKER TIME A PAYLOAD MARKER EOP MARKER OUTPUT FROM CRC B C D CRC-16 CASE B C D A B C D OUTPUT FROM CRC CRC-32 CASE TIME A PAYLOAD MARKER EOP MARKER B C D A 5-8283(F) Figure 82. Assorted CRC Generator Cases Agere Systems Inc. 641 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--CRC Generator/Checker Subblock (continued) Examples of CRC Insertion/Testing (continued) PACKET BYTES INSERTED CRC BYTES A B C D A B C D BLANK BYTES PAYLOAD MARKER EOP MARKER INPUT TO CRC TIME TIME A PAYLOAD MARKER EOP MARKER TIME A PAYLOAD MARKER EOP MARKER B C D A B C D B C D A B C D OUTPUT FROM CRC CRC-32 CASE OUTPUT FROM CRC CRC-16 CASE 5-8284(F) INPUT TO CRC TIME A B C D A BC D PAYLOAD MARKER EOP MARKER OUTPUT FROM CRC B C D CRC-32 CASE TIME A PAYLOAD MARKER EOP MARKER B C D A TIME A PAYLOAD MARKER EOP MARKER B C D A B C D OUTPUT FROM CRC CRC-16 CASE 5-8285(F) Figure 83. Assorted CRC Generator Cases 642 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--CRC Generator/Checker Subblock (continued) Examples of CRC Insertion/Testing (continued) Receive This section, describes the different cases on the CRC receive side. The figure below shows several cases with varying positions for the EOP marker. INPUT TO CRC TIME A PAYLOAD MARKER EOP MARKER B C D A B C D PACKET BYTES CRC BYTES BLANK BYTES OUTPUT FROM CRC TIME A B C D A BC D CRC-32 CASE CRC STRIPPED PAYLOAD MARKER EOP MARKER 5-8286(F) INPUT TO CRC TIME A PAYLOAD MARKER EOP MARKER OUTPUT FROM CRC TIME A BC D A BC D CRC-32 CASE CRC STRIPPED B C D A B C D PAYLOAD MARKER EOP MARKER 5-8287(F) Figure 84. Assorted CRC Checker Cases Agere Systems Inc. 643 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--CRC Generator/Checker Subblock (continued) Examples of CRC Insertion/Testing (continued) INPUT TO CRC TIME A PAYLOAD MARKER EOP MARKER B C D A B C D PACKET BYTES CRC BYTES BLANK BYTES OUTPUT FROM CRC TIME A B C D A BC D CRC-32 CASE CRC STRIPPED PAYLOAD MARKER EOP MARKER 5-8288(F)r.3 INPUT TO CRC TIME A PAYLOAD MARKER EOP MARKER OUTPUT FROM CRC TIME A B C D A BC D CRC-32 CASE CRC STRIPPED B C D A B C D PACKET BYTES CRC BYTES BLANK BYTES PAYLOAD MARKER EOP MARKER 5-8289(F)r.2 Figure 85. Assorted CRC Checker Cases 644 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--PPP Detach Subblock PPP Header Detach The PPP detach function matches the PPP header (corresponding to the first 4 bytes of the PPP uncompressed frame or first 2 bytes of the PPP compressed frame) to a set of fixed or provisionable values for each channel and outputs frames in accordance with payload control register settings. The address and control field bytes are assumed to be 0xFF03. The block supports two fixed protocol fields (0x0021 corresponding to the IP protocol field and 0x8021). Additionally, 12 provisionable registers, PPP_Rx_HDRmn (mn = 00, 01, 02, . . . , 11), are supported on-chip to allow a large number of protocols to be recognized in the receive (ingress) data path of the chip (see register descriptions). The PPP detach function supports compressed or uncompressed header fields, optionally matching two fixed (one corresponding to IP protocol) 16-bit protocol fields. This optional PPP header check allows PPP (normal or compressed (i.e., no FF03)) to be checked and the header optionally stripped. Packets that fail to match one of the provisioned headers or the two default headers can optionally be discarded. This function supports optionally matching 12 programmable 16-bit protocol fields. The PPP detach function provides bad PPP frame counts through a 28-bit counter per channel and provides bad CRC field counts per channel. The function can optionally discard packets if header fields do not match on a per-channel basis. It can also optionally strip header fields only if they do match on a per-channel basis. A PPP frame has the following two formats: Uncompressed PPP Packet 1 byte 1 byte 1 byte 0x7E address field 0xFF control field 0x03 Compressed PPP Packet 1 byte 2 bytes 64 kbytes 0x7E protocol field data 4 bytes CRC field 1 byte 0x7E 2 bytes 64 kbytes protocol field data 4 bytes CRC field 1 byte 0x7E Each channel has a 16-bit register, PPP_Rx_CHK_CHn (n = 0, 1, 2, or 3), that can be provisioned (see register descriptions, page 693). If the header bytes do not match and payload control[10] = 0, the entire PPP frame is discarded for a given channel. Otherwise, if the header bytes do not match and payload control[7] = 1, the PPP frame is marked as bad and not discarded for a given channel. Bad packet counting is based upon the following criteria: Header Fields. The PPP bad header counter, PM_BHC_n (n = 0, 1, 2, 3), counts for PPP frames with various header errors/mismatches as provisioned in the registers. CRC Field. The CRC bad packet counter, PM_BPC_n (n = 0, 1, 2, 3), increments if a CRC error is found in channel n. Note: Each channel only has one bad packet counter. Agere Systems Inc. 645 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--PPP Detach Subblock (continued) PPP Header Detach (continued) When a channel is configured for PPP mode, header/CRC stripping is controlled by the values in registers 0x6680--0x668F, 0x66B0--0x66BB, and 0x66C0--0x66CF. PPP headers can have either a 32-bit format or a 16-bit format. PPP packets with a 32-bit header are said to be uncompressed, and PPP packets with 16-bit headers are said to be compressed. In uncompressed PPP headers, the first 2 bytes must have a fixed value of 0xFF03, and the second 2 bytes represent the protocol value. In compressed PPP headers, the two bytes of the header are the protocol value. The PPP detach block first examines each incoming packet to determine whether or not it matches one of the desired protocol values. The matching process is controlled by the value in the PPP_RX_CHK registers, 0x66C0 through 0x66CF (for channels 0 through 15, respectively). MARS2G5 P-Pro can recognize both compressed and uncompressed headers, with a variety of PPP protocol values. It can keep/discard each packet based on whether the PPP header type (compressed or uncompressed) and/ or protocol value matches one of the expected values or not. Bits [15:14] of PPP_RX_CHK register control the PPP matching mode as follows: Bit 15 Bit 14 0 0 0 1 Wildcard match mode. Passes all packets with uncompressed PPP headers. In other words, all packets starting with the value 0xFF03 are matched. Pass only packets with uncompressed PPP headers and one of more of the 14 PPP protocol values that can be specifically selected (as described below). In other words, packets are matched if the first 2 bytes are 0xFF03 and the following bytes are one of the (possibly several) specifically selected protocol values. Pass only packets with compressed PPP headers and a PPP protocol value that is specifically selected by settings described below. In other words, packets are matched if the first 2 bytes are one of the (possibly several) specifically selected protocol values. Pass only packets with a PPP protocol value that is specifically selected by settings described below (i.e., protocol values are matched without regard to whether or not the header is compressed). In other words, this represents a combination #1 and #2 above. A packet is matched if the first 2 bytes are 0xFF03 and following 2 bytes are any one of the specifically selected protocol values OR if the first 2 bytes of the packet match any one of the specifically selected protocol values. 1 0 1 1 In addition to the wildcard matching mode that passes any protocol value, the MARS2G5 P-Pro can filter for packets with up to 14 specific protocol values. Two of these values are already in common use and are hardcoded, while the remaining twelve can be selected by software to allow future growth. The 14 specific protocol values that can be matched are as follows: 0. S/W defined protocol value #1 (in 0x66B0: PPP_RX_HDR0) 1. S/W defined protocol value #2 (in 0x66B1: PPP_RX_HDR1) 2. S/W defined protocol value #3 (in 0x66B2: PPP_RX_HDR2) 3. S/W defined protocol value #4 (in 0x66B3: PPP_RX_HDR3) 4. S/W defined protocol value #5 (in 0x66B4: PPP_RX_HDR4) 5. S/W defined protocol value #6 (in 0x66B5: PPP_RX_HDR5) 6. S/W defined protocol value #7 (in 0x66B6: PPP_RX_HDR6) 7. S/W defined protocol value #8 (in 0x66B7: PPP_RX_HDR7) 8. S/W defined protocol value #9 (in 0x66B8: PPP_RX_HDR8) 9. S/W defined protocol value #10 (in 0x66B9: PPP_RX_HDR9) 10. S/W defined protocol value #11 (in 0x66BA: PPP_RX_HDR10) 11. S/W defined protocol value #12 (in 0x66BB: PPP_RX_HDR11) 12. A fixed value of 0x0021 13. A fixed value of 0x8021 646 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--PPP Detach Subblock (continued) PPP Header Detach (continued) Bits [13:0] of the PPP_RX_CHK register represent a 14-bit field that selects one or more of the above protocol values for matching. The bit numbers for the corresponding protocol values are given in the first column of the list above. If a bit is set to one, then the corresponding protocol value is used for matching. If a bit is set to zero, then that value is not used for matching. If a received packet is matched for both header-type (based on bits [15:14] of PPP_RX_CHK) and protocol value (based on the specific values selected in bits [13:0] of PPP_RX_CHK), then it is passed along for further processing. If a received packet is not matched, then it is discarded. If a received packet is matched and passed along for further processing, the values in the PPP_PROTOCOL_CONTROL registers (0x6680--0x668F: channels 0 to 15, respectively) determine whether or not the header and CRC are stripped. In a manner similar to that described above, bits [13:0] of the PPP_PROTOCOL_CONTROL registers allow selection of one or more specific protocol values. Note that at this point the protocol value has been determined and it is unimportant whether the PPP header has been compressed or not. If the protocol value matches one of the ones selected by bits [13:0], then both the PPP header and the trailing CRC are removed from the packet before it is passed on for further processing. Otherwise, the PPP header and trailing CRC are left on the packet. It is not possible to selectively strip only the PPP header or the trailing CRC. Agere Systems Inc. 647 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Data Engine Counter Subblock Introduction The purpose of this section is to provide an overview of the implementation of the data engine counter (DECNT) subblock. Overview The purpose of the DE counter block is to be able to keep track of the number of packets passing through each channel. This information will be read in by the microprocessor used to monitor performance in each channel. Implementation The DE counter block is made up of sixty-four 28-bit counters. The 64 counters are divided into four groups each containing 16 counters, one for each channel. The four groups are listed below: ATM single-bit error/HDLC invalid sequence ATM discarded cell/ATM errored header CRC bad packet PPP bad header The ability to share the ATM/HDLC error counters lies in the fact that each channel has a choice of ATM or HDLC data. So, theoretically, it is impossible for an ATM single-bit error and an HDLC invalid sequence to occur on the same channel. However, it should be noted that the HDLC/ATM counters can increment by more than 1 in any given clock cycle. The MPU_PMRST signal, on its rising edge, starts a process that transfers the counter values to register files. Since only 1 value can be transferred in one cycle of the system clock (i.e., one cycle of the 77.76 MHz clock), the transfer will take 64 clock cycles. As each value is written into the register file, the counter gets reset so that no errors go unnoticed in the transfer. Figure 86 DE Counter Block, on page 649, shows a diagram of the DE counter block. Note: The MPU_PMRST signal is clocked to the MPU_CLK (microprocessor clock) domain. However, due to its static nature (period ~1 second), the need to retime the MPU_PMRST signal is minimal and was not implemented in the design. The counters themselves receive error signals from other blocks in the data engine. If a bad packet signal is received, the block will enable one of the four counters for a particular error. The block uses the 2-bit error channel ID value to determine which of the counters to enable. As mentioned above, the ATM/HDLC counters can increment by more than one (1) on a given clock cycle. The design for those counters is slightly more complicated (using 2-bit adders). All counters are designed not to overflow, meaning that once the counter has saturated (0xFFFFFFF), the counter will not increment to 0x0000000 upon the next increment, but will remain saturated until reset by the MPU_PMRST signal. 648 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Data Engine Counter Subblock (continued) COUNTER RESET PULSES COUNTER VALUES MUX CONTROL TRANSFER PROCESS ATM/HDLC COUNTERS (1ST PAIR) INTERRUPTS ATM/HDLC COUNTERS (2ND PAIR) ERROR SIGNALS INTERRUPTS CRC BAD PACKET COUNTERS INTERRUPTS PPP BAD HEADER COUNTERS INTERRUPTS COUNTER VALUES COUNTER VALUES COUNTER VALUES COUNTER STORAGE WRITE ENABLE DECNT_DOUT COUNTER VALUE INTERRUPT STATUS INTERRUPT GENERATION ADDRESS DECODER READ ADDRESS MUX CONTROL MPU_WENP MPU_ADDR MPU_RENP CORIRQ CORWN MPU MPU_PMRST 5-8320(F)r.4 Figure 86. DE Counter Block Agere Systems Inc. 649 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Data Engine Counter Subblock (continued) Since the counters have 28-bit values, two MPU transfers are needed to read the value of a counter. Therefore, 128 MPU transfers are needed to read all 64 counters (i.e., two transfers per counter for each of the 64 counters). Counter values are transferred to holding registers following a PMRST and should be read within a PMRST cycle to properly obtain the counter values. Each of the counters is capable of triggering an interrupt every time the incident occurs. The interrupt is disabled upon start-up. 650 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock Channel Distribution and Allocation Subblock Description The channel distribution and allocation (CDA) subblock requests data from the UTOPIA for various logical channel. The data request generated by the CDA is proportional to the STS concatenation rate. The sequence of Tx channel polling requests made to the UTOPIA interface is simply generated through table look up. Two software provisionable tables (MAP0 and MAP1) each with 48 time slots is provided to generate channel id for UTOPIA. A control register with a selection bit (CDA_MAP_CNTL) controls which table is continuously addressed by a by-48 TS counter to generate the actual channel request IDs. The inactive sequence map can be both read and written via the microprocessor interface for provisioning and verification. The active map cannot be accessed by the microprocessor. When the control register selection bit is changed, the change will first clockcross from MPU_CLK domain to SYS_CLK domain. The actual change occurs when the counter cycles which ensures that only complete sequences are used. The temporal interpretation of each of the 48 memory slots is an STS-1 of channel bandwidth. Therefore, each channel of STS-n bandwidth should occupy exactly n time slots of a map. While the position of all of the channel time slots happens to be arbitrary, it is recommended that the occupied time slots for each active channel be dispersed in the map as evenly as possible to help minimize peak FIFO occupancy (i.e., to minimize the burstiness of the channel requests). Functions of each block in the CDA are given next. TS Counter The time-slot counter is a modulo 48 counter. It counts from 0 to 47. It is used as an index to the channel ID lookup table in MAP0 and MAP1. When the counter wraps around to 0, the provisioned switching of the working map from one to another will take effect if there is a change of value in CDA_MAP_CNTL as shown in Table 702, CDA MAP Control Register (R/W) on page 681. Registers Refer to DE register map and DE register description for information. Agere Systems Inc. 651 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps The CDA map is part of the logic in the Tx data engine (DE). It allocates the bandwidth of the DE among the channels (1 to 16) that are provisioned. One entry in the CDA map corresponds to 52 Mbits/s worth of traffic. The following rules must be followed when programming the CDA maps. 1. The bandwidth of a channel must be less than or equal to the allocation specified in the CDA map. This ensures that the PT FIFOs will not underflow. This means that for a channel mapped into an STS-Nc SONET path, the CDA map must contain at least N entries for that channel. (For STM-Mc, the CDA map must contain at least 3*M entries for the corresponding channel.) 2. The entries in the CDA map must be programmed to maximally distribute the entries for a given channel. In other words, it is desirable to avoid having consecutive identical entries in the CDA MAP. This ensures that data for each channel flows smoothly (i.e., nonbursty) so that the PT FIFOS will not overflow. Note: The order of entries in the CDA map has no relation to the order of SONET time slots. There are two CDA maps; at any time one is active and the other is inactive. Selection of the active map is done by writing CDA_MAP_CNTL[0] bit 0 of 0x60BF (Table 702) to 1 or 0. Note: Reads and writes always occur to the inactive map, regardless of the address being used. There is no way to read the active map. Once the selection has been made by writing to 0x60BF, it takes up to 617 ns for the change to take place (48/77.76 MHz). This can be viewed by reading register 0x60BF and looking at bit 1. 0x60BF [bit1] represents the map that is currently active. When bit 0 and bit 1 match (i.e., are either 00 or 11), it is safe to write to a CDA map. If they are different (i.e., are either 10 or 01), it is not safe to write to the CDA map, since a map change is pending (i.e., a write could end up in either the active or inactive map.) 3. When switching maps, the MPU must poll bit 1 of 0x60BF before writing a new map. It can only proceed if bit 1 and bit 0 are identical. The code that follows represents a TCL script implementation of such a handshake. 652 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Procedure to Select a Map as Active and Handshake with MARS2G5 P-Pro to Ensure It Is Active Before Proceeding proc cda_select_map {map {tries 20}} { tadmwrite 0x60BF $map set waitval [expr $map | ($map<<1)] for {set i 0} { $i < $tries } { incr i } { set tmprd [tadmread 0x60BF] if {$tmprd == $waitval} { break } } if {$tmprd != $waitval} { puts "ERROR: CDA_SELECT_MAP $map: timeout!" } } Entries in the CDA map are 6 bits wide. There is also a don't use bit, located in bit 6. 4. All entries in the CDA map must be in the range 0--15 inclusive. 5. The don't use bit should never be set to 1. Agere Systems Inc. 653 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Examples of Programming the CDA Map Note: The value * means any channel ID, and in the official scripts is substituted with the value 0. Example 0: Two channels, dual OC-3c. cda_dump [ cda_calculate_map { {0 STS-3c} {4 STS-3c} } ] CH0: STS-3c needs 3 time slots. CH4: STS-3c needs 3 time slots. INFO: Largest configured channel is {STS-3}. INFO: Total configured bandwidth is {STS-6}. 04********** ****04****** ********04** ************ 654 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 1: One channel OC-48c. cda_dump [ cda_calculate_map { ] {0 STS-48c} } CH0: STS-48c needs 48 time slots. INFO: Largest configured channel is {STS-48}. INFO: Total configured bandwidth is {STS-48}. 000000000000 000000000000 000000000000 000000000000 Agere Systems Inc. 655 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 2: Four channel OC-3c cda_dump [ cda_calculate_map { {0 STS-3c} {4 STS-3c} {8 STS-3c} {12 STS-3c} } ] CH0: STS-3c needs 3 time slots. CH4: STS-3c needs 3 time slots. CH8: STS-3c needs 3 time slots. CH12: STS-3c needs 3 time slots. INFO: Largest configured channel is {STS-3}. INFO: Total configured bandwidth is {STS-12}. 0 4 8 12 * * * * * * * * * * * * 0 4 8 12 * * * * * * * * * * * * 0 4 8 12 ************ 656 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 3: 16 channel OC-3c cda_dump [ cda_calculate_map { {0 STS-3c} {1 STS-3c} {2 STS-3c} {3 STS-3c} {4 STS-3c} {5 STS-3c} {6 STS-3c} {7 STS-3c} {8 STS-3c} {9 STS-3c} {10 STS-3c} {11 STS-3c} {12 STS-3c} {13 STS-3c} {14 STS-3c} {15 STS-3c} } ] Agere Systems Inc. 657 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) CH0: STS-3c needs 3 time slots. CH1: STS-3c needs 3 time slots. CH2: STS-3c needs 3 time slots. CH3: STS-3c needs 3 time slots. CH4: STS-3c needs 3 time slots. CH5: STS-3c needs 3 time slots. CH6: STS-3c needs 3 time slots. CH7: STS-3c needs 3 time slots. CH8: STS-3c needs 3 time slots. CH9: STS-3c needs 3 time slots. CH10: STS-3c needs 3 time slots. CH11: STS-3c needs 3 time slots. CH12: STS-3c needs 3 time slots. CH13: STS-3c needs 3 time slots. CH14: STS-3c needs 3 time slots. CH15: STS-3c needs 3 time slots. INFO: Largest configured channel is {STS-3}. INFO: Total configured bandwidth is {STS-48}. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 658 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 4: Four channel OC-12c cda_dump [ cda_calculate_map { {0 STS-12c} {4 STS-12c} {8 STS-12c} {12 STS-12c} } ] CH0: STS-12c needs 12 time slots. CH4: STS-12c needs 12 time slots. CH8: STS-12c needs 12 time slots. CH12: STS-12c needs 12 time slots. INFO: Largest configured channel is {STS-12}. INFO: Total configured bandwidth is {STS-48}. 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 Agere Systems Inc. 659 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 5: Four channels OC-24c, 13c, 6c, and 5c cda_dump [ cda_calculate_map { {0 STS-24c} {4 STS-13c} {8 STS-6c} {12 STS-5c} } ] CH0: STS-24c needs 24 time slots. CH4: STS-13c needs 13 time slots. CH8: STS-6c needs 6 time slots. CH12: STS-5c needs 5 time slots. INFO: Largest configured channel is {STS-24}. INFO: Total configured bandwidth is {STS-48}. 0 4 0 4 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 660 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 6: Five channels all OC-9c cda_dump [ cda_calculate_map { {0 STS-9c} {3 STS-9c} {6 STS-9c} {9 STS-9c} {12 STS-9c} } ] CH0: STS-9c needs 9 time slots. CH3: STS-9c needs 9 time slots. CH6: STS-9c needs 9 time slots. CH9: STS-9c needs 9 time slots. CH12: STS-9c needs 9 time slots. INFO: Largest configured channel is {STS-9}. INFO: Total configured bandwidth is {STS-45}. 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 * * * Agere Systems Inc. 661 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 7: Nine channels all OC-5c cda_dump [ cda_calculate_map { {0 STS-5c} {2 STS-5c} {4 STS-5c} {6 STS-5c} {8 STS-5c} {10 STS-5c} {12 STS-5c} {14 STS-5c} {15 STS-5c} } ] CH0: STS-5c needs 5 time slots. CH2: STS-5c needs 5 time slots. CH4: STS-5c needs 5 time slots. CH6: STS-5c needs 5 time slots. CH8: STS-5c needs 5 time slots. CH10: STS-5c needs 5 time slots. CH12: STS-5c needs 5 time slots. CH14: STS-5c needs 5 time slots. CH15: STS-5c needs 5 time slots. 662 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) INFO: Largest configured channel is {STS-5}. INFO: Total configured bandwidth is {STS-45}. ================================================== 0 2 4 6 8 10 12 14 15 15 0 2 4 6 8 10 12 14 15 * 0 2 4 6 8 10 12 14 15 * 0 2 4 6 8 10 12 14 15 * 0 2 4 6 8 10 12 14 ================================================== Agere Systems Inc. 663 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 8: Two channels OC-24c cda_dump [ cda_calculate_map { {1 STS-24c} {2 STS-24c} } ] CH1: STS-24c needs 24 time slots. CH2: STS-24c needs 24 time slots. INFO: Largest configured channel is {STS-24}. INFO: Total configured bandwidth is {STS-48}. 121212121212 121212121212 121212121212 121212121212 664 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 9: Complicated 9 channel example cda_dump [ cda_calculate_map { {0 STS-7c} {2 STS-4c} {4 STS-7c} {6 STS-5c} {8 STS-5c} {10 STS-7c} {12 STS-4c} {14 STS-4c} {15 STS-4c} } ] Agere Systems Inc. 665 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) CH0: STS-7c needs 7 time slots. CH2: STS-4c needs 4 time slots. CH4: STS-7c needs 7 time slots. CH6: STS-5c needs 5 time slots. CH8: STS-5c needs 5 time slots. CH10: STS-7c needs 7 time slots. CH12: STS-4c needs 4 time slots. CH14: STS-4c needs 4 time slots. CH15: STS-4c needs 4 time slots. INFO: Largest configured channel is {STS-7}. INFO: Total configured bandwidth is {STS-47}. 0 4 10 6 8 8 2 0 4 10 12 12 14 6 0 4 10 8 2 14 15 0 4 10 6 12 14 8 0 4 10 2 15 15 6 0 4 10 8 12 14 * 0 4 10 6 2 15 666 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--Channel Distribution and Allocation Subblock (continued) Operation and Programming of the CDA Maps (continued) Example 10: Four channels, 24c, 12c, 6c, 6c cda_dump [ cda_calculate_map { {0 STS-24c} {4 STS-12c} {8 STS-6c} {12 STS-6c} } ] CH0: STS-24c needs 24 time slots. CH4: STS-12c needs 12 time slots. CH8: STS-6c needs 6 time slots. CH12: STS-6c needs 6 time slots. INFO: Largest configured channel is {STS-24}. INFO: Total configured bandwidth is {STS-48}. 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 0 4 0 8 0 4 0 12 Agere Systems Inc. 667 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--GFP General Framing Procedure Subblock Introduction The purpose of this section is to provide the implementation details for the generic framing procedure (GFP) framing and frame insertion mechanisms contained within the data engine block. The functionality is similar to simple data link (SDL, RFC 2823). SDL was intended as an extension of PPP for the encapsulation of packet data over SONET/SDH and for the use in packet-over-wavelength applications. MARS2G5 P-Pro is compliant with RFC 2823 in all respects. Overview Generic framing procedure (GFP) is a framing procedure for octet-aligned, variable-length payload for subsequent mapping into SONET/SDH synchronous payload envelopes as defined in ANSI T1.105.02 and ITU-T G.709 and G707. GFP packets are mapped into SONET/SDH frames row-wise, similar to the mapping of ATM or PPP protocols. The proposed C2 byte signal label definitions for GFP are 0x17 for X43 scrambling and 0x19 for the set-reset X48 scrambling. CRC-16 based frame delineation with the CRC calculated over the 2-byte packet length indicator (PLI) field. Single-bit and some double-bit header error correction. Multiple-bit (uncorrected) header error detection. Transmit-side header and payload error insertion functionality (single or multibit). X48 independently running set-reset scrambler with scrambler state update message functionality. Programmable scrambler update interval. x43 self-synchronous scrambler. Support for packet sizes from a minimum of 4 octets to a maximum of 655535 octets. Optional CRC-16/32 payload frame check sequence with optional CRC stripping. Packet-over-wavelength operation (i.e., no SONET frame insertion). SONET/SDH/OTN mapping of GFP payload. Two user-programmable 6-byte OAM messages. Provisionable offset field from 0 to 32 octet for link layer procedures (e.g., MPLS tags). For GFP compliance, the offset field must be provisioned to 0. Three independent parallel framers for improved reframe times after loss of synchronization. The MARS2G5 P-Pro GFP frame is shown in Figure 87 (a) without (b) and with the optional frame check sequence (FCS) applied to the payload. The frame consist of a 4-octet header (packet length indication + CRC-16 calculated over the packet length indicator), a 0--65535 octet payload area containing the encapsulated packet data (with associated packet headers), and an optional CRC-16 or CRC-32 field calculated over the payload area. In MARS2G5 P-Pro, there is an optional offset field that is used for link layer procedures as shown in Figure 88e. The layer 2 master device that sends GFP packet data to the device (MARS2G5 P-Pro) must insert the packet length header field at the appropriate location in the data stream, which is positioned in the first 2 bytes of the header. When using a UTOPIA 3+ interface, these bytes must occur as the 2 most significant bytes during the bus cycle where TxSOP is asserted. The MARS2G5 P-Pro generates and inserts the necessary CRC-16 header field over the packet length indicator. The layer 2 master sends the payload area header and data to the device. The MARS2G5 P-Pro calculates the optional CRC-16/32 over the payload area and attaches it to the end of the packet. 668 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--GFP General Framing Procedure Subblock (continued) Overview (continued) PACKET DATA/ PAYLOAD AREA PACKET LENGTH CRC-16 PACKET DATA/PAYLOAD AREA PACKET LENGTH A. GFP encapsulation of packet data without CRC (GFP mode) CRC-16/32 PACKET LENGTH CRC-16 PACKET DATA/PAYLOAD AREA CRC-16/32 PACKET LENGTH B. GFP encapsulation of information with CRC (GFP-CRC mode) 1630(F) Figure 87. GFP Encapsulations of Packet Data PLI = 0 IDLE FRAME NO PAYLOAD NO FCS 0x0000 HEADER CRC-16 (A) PLI = 1 RESERVED OAM MESSAGE USED FOR SCRAMBLER STATE UPDATE IN MARS2G5 P-Pro 0x0001 HEADER CRC-16 OA & M MESSAGE (48 bits) MARS2G5 P-Pro SCRAMBLER STATE UPDATE MESSAGE (B) PAYLOAD CRC-16 PLI = 2 OAM A MESSAGE 0x0002 HEADER CRC-16 (C) A MESSAGE (48 bits) PAYLOAD CRC-16 PLI = 3 OAM B MESSAGE 0x0002 HEADER CRC-16 (D) B MESSAGE (48 bits) PAYLOAD CRC-16 PACKET LENGTH HEADER CRC-16 LINK LAYER PROCEDURES PACKET DATA PAYLOAD CRC-16 0--8, 10, 12, 14, 16, 20, 24, 32 bytes BASED ON OFFSET PROVISIONING (OFFSET MUST BE SET TO 0 FOR GFP COMPLIANCE). (E) 1631(F)TDAT Figure 88. Special-Purpose GFP Header Definitions Agere Systems Inc. 669 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Control Messages The lower values of the packet length indicator (PLI) field are reserved for GFP control purposes. The absolute minimum value of the PLI field is an information carrying GFP PDU is 4 octets. GFP assigns special meaning to PLI field values in the 0--3 range. The PDU formats for these messages are depicted shown in Figure 88. The FCS for the control message payload is generated using the same general procedure as for the core header CRC16 computation. Single bit errors contained within the payload section of special message 1--3 are corrected using the payload CRC-16. Multibit errors are detected but not corrected. The PLI value of 0 is defined as the interpacket fill header, and when no packet data is present, this 32-bit word is transmitted as shown in Figure 88a. In MARS2G5 P-Pro, the PLI value of 1, which is not defined specifically in the GFP proposals, is defined for use with the x48 scrambler and carries 6 bytes or a 48-bit scrambler state update message from the source scrambler to the destination descrambler as shown in Figure 88b. The PLI values of 2 and 3 are used to encapsulate six byte layer 1 messages between the source and destination. The format for the special-purpose headers is shown in Figure 88c and d. The MARS2G5 P-Pro provides a programmable offset value as a placeholder for inclusion of specific data-link header information. The layer 2 master device connected to the MARS2G5 P-Pro should not include this offset value as part of its packet-length header. The MARS2G5 P-Pro accounts for the offset as an addition to the packet length provided by the layer 2 device, on the receive side the packet-length header must be added to the offset value to indicate the location of the start of the next packet. Link layer or layer one messaging must negotiate the offset value field between transmitter and receiver prior to transmission. The GFP standards proposal includes the link-layer header information as part of the packet data (payload header fields). Therefore, this header is included in the calculation of the PLI value by the master device. So, in order for the MARS2G5 P-Pro implementation to operate in a GFP compliant mode, the offset must be provisioned to a value of 0. 670 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Frame Delineation/Frame Insertion GFP frames are delineated using a modified version of the HEC algorithm specified for ATM in ITU-T I.432. The frame delineation algorithm differs in two basic ways from ITU-T I.432. 1. The algorithm uses the packet length indicator (PLI) field of the 4-byte packet length header for determining the end of the GFP frame. 2. The HEC field calculation uses a 16-bit polynomial to generate the CRC-16 over the PLI. Receive Direction The GFP framer state machine has three states, HUNT, presynchronization, and synchronization state as shown in Figure 89. The HUNT state accepts the incoming GFP frames and checks for a CRC-16 that matches the sequence of the last four octets. Once a match is found, the framer enters the presynchronization state. The presynchronization state checks the frame delineation for a correct CRC-16. The start of the next frame and the location of the next CRC-16 field is determined by the value in the packet length indicator field (PLI value). The PLI value is added to the size of the header, the length of the CRC field, and the provisioned offset value (PLI + CRC16 + 0). This process continues until delta consecutive correct CRC-16s are confirmed, once confirmed the synchronization state is entered. All framers continue operating until one framer enters the synchronization state. The state machine returns to the HUNT state if no CRC-16 are found while in any state. When the device is in the HUNT state, three simultaneous hunt engines are used to find the frame bounder to ensure adequate reframe times. Idle frames (GFP interpacket fill frames) are used in the delineation process and discarded. The PLI header can optionally be stripped from ingress packets being sent to the extended UTOPIA interface output. Single-bit and some double-bit errors can be corrected on the PLI field using the CRC-16 frame check sequence (FCS). Correction only occurs when the framer is in the synchronization state. Uncorrected multibit errors are detected but not corrected. Both single-bit and multibit errors are counted in 28-bit saturation counters. The payload CRC-16/32 can be used to detect payload errors, but does not provide error correction capabilities. The payload CRC-16/32 field can optionally be stripped on ingress packets. Agere Systems Inc. 671 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Frame Delineation/Frame Insertion (continued) Transmit Direction The layer 2 master device must provide MARS2G5 P-Pro GFP packets with the PLI field attached to the start of the packet in the transmit direction. The MARS2G5 P-Pro will generate the CRC-16 over the header and attach it as the 3rd or 4th bytes of the outgoing packet. The generating polynomial used for the creation of the header CRC-16 field is X16 + X12 + X5 + 1. The X43, X48, or no scrambling is applied to the payload area of the packet and scrambled. CRC-16/32 is attached to the end of the packet. The MARS2G5 P-Pro also provides a provisional option to suppress the insertion of a payload area CRC. The CRC-16/32 generating polynomials used over the payload are as follows: CRC-16--X16 + X12 + X5 + 1 CRC-32--X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4+ X2 + X+ 1 CRC-16s FOUND PRESYNCHRONIZATION SYNCHRONIZATION SECOND CRC-16 NOT FOUND CRC-16 MATCH FOUND CORRECTABLE CRC-16 FOUND CORRECTABLE CRC-16 NOT FOUND HUNT NO CRC-16 MATCH FOUND 1632(F) Figure 89. Special-Purpose GFP Header Definitions 672 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Scrambling/Descrambling Scrambling of GFP frames are required to provide security against payload information replicating the frame synchronous (or OTUk) scrambling word used at the OTUk/SONET/SDH section layer. Figure 90 illustrates the GFP compliant scrambler and descrambler process. For GFP compliance, all octets of the GFP payload area are scrambled using a 1 + X43 self-synchronous scrambler. At the transmitter, scrambling is enabled starting at the first transmitted octet after the header CRC-16 field, and is disabled after the last transmitted octet of the GFP frame including the payload CRC-16. The activation of the receiver descrambler depends on the present state of the header CRC-16 check algorithm. The scrambler is disabled in the HUNT and PRESYNC states as shown in Figure 89. In the SYNC state, the descrambler is enabled only for the octets between the HEC field and the end of the assumed GFP frame. When the scrambler/descrambler is disabled, its state is retained. The scrambling is done least significant bit first. The MARS2G5 P-Pro provides two methods for scrambling/descrambling data on the link for passing GFP packets that are the X43 self-synchronous scrambler/descrambler and X48 free-running set-reset scrambler. The first approach uses a lower complexity and less robust X43 self-synchronization scrambler; the scrambler is considered self-synchronous because synchronization is maintained by the data itself. This is less secure to malicious attacks than the X48 free-running set-reset scrambler. The diagram for the X43 self-synchronous scrambler/descrambler is shown in Figure 90 and the diagram for the X48 free-running set-reset scrambler is shown in Figure 91. The X43 scrambler uses the X43 + 1 primitive polynomial for its output sequence generation. In GFP, scrambling is done over the payload area, which includes the offset field and the CRC-16/32 payload FCS, but not the 4-byte header (PLI + CRC-16) field dc balanced Barker-like sequence of length 32. The 4-byte header is modulo 2 added (exclusive ORed) to 0xB6AB31E0 prior to transmission and on reception is removed before the frame delineation. Although GFP over SONET does not necessitate a dc balanced header, the approach facilitates the usage of GFP channels directly over wavelength (bypass SONET framing). The first approach uses a lower complexity and less robust X43 self-synchronization scrambler similar to the scramblers used for the PPP/HDLC/ATM protocols. Figure 90 shows the diagram of the X43 self-synchronization scrambler. The scrambler is self-synchronous because synchronization is maintained by the data itself. This is less secure to malicious attacks than the X48 free-running set-reset scrambler. Agere Systems Inc. 673 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Scrambling/Descrambling (continued) INPUT DATA + D D0 C Q D D1 C Q PRIMITIVE POLYNOMIAL x43 + 1 D D42 C Q CLOCK SCRAMBLED DATA OUT (A) x43 SELF-SYNCHRONOUS SCRAMBLER INPUT DATA D D0 C Q D D1 C Q PRIMITIVE POLYNOMIAL x43 + 1 D D42 C Q CLOCK + UNSCRAMBLED DATA OUT (B) x43 SELF-SYNCHRONOUS DESCRAMBLER 1633(F)r.1 Figure 90. X43 Self-Synchronous Scrambler/Descrambler The X48 scrambler provides an alternative to the standards compliant X43 scrambler used for PPP/HDLC/ATM and the diagram is shown in Figure 91. The X48 scrambler initializes at 0xFFFFFFFFFFFF when the link enters the presynchronization state and free runs from this starting point. The scrambler has a X48 + X28 + X27 + X+ 1 generating polynomial and input data to the scrambler is exclusive ORed with the output of the generated sequence. To synchronize the receivers scramble-state with the transmitters scrambler-state, scrambler-state update messages must be sent periodically from the transmitter to the receiver. This is accomplished using the special-purpose scrambler state messages shown in Figure 88b. The scrambler state update messages can be sent by configuring the scrambler state transmit mode register. The provisionable resolution interval can be configured to be either packet or 32-bit words. The default configuration is for one scrambler-state update message to be sent every eight packets, independent of the packet size. 674 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Scrambling/Descrambling (continued) INPUT DATA + + + + D D0 C Q D D1 C Q D D26 C Q D D27 C Q D D47 C Q CLOCK SCRAMBLED DATA OUT GENERATING POLYNOMIAL x48 + x28 + x27 + x + 1 1634(F)r.1 Figure 91. X48 Set-Reset Scrambler The state machine for scrambler synchronization is shown in Figure 92. The scrambler starts in an out-of-frame state and is required to be in synchronization before data can pass through the device. Data will flow once the scrambler is in the synchronization state and will continue to flow in the postsynchronization state. Data will stop flowing when the scrambler is in the presynchronization or out-of-frame states. The scrambler is initialized on reset to a value of 0xFFFFFFFFFFFF and zero-detect circuitry is used to ensure that a state of 0x000000000000 is never reached. If an all-zero pattern is detected, the scrambler state is reset to its default value. The scrambler moves from the out-of-frame state to the presynchronization state on a state special message transfer. If the next scrambler message sent by the transmitter results in a state match at the receiver, then the scrambler will go into synchronization and begin to pass data. If the presynchronization state, a state mismatch occurs, a synchronization slip results and the receive-side scrambler accepts the next error-free scrambler state message transfer as its new scrambler-state and matches future messages with this newly updated message. When in the synchronization state, a state match will maintain scrambler synchronization; however, a state mismatch will result in a soft error and cause a transition to the postsynchronization state. Data will continue to pass in this state; however, another mismatch will result in a synchronization slip and the state transitions to presynchronization. This will then require the receive-side scrambler to update its state on the next available validated scrambler update message received. When operating in any of the four scrambler states, lack of proper frame delineation will result in the scrambler going to the out-of-frame state. MARS2G5 P-Pro provides the option to disable scrambling on the payload. When scrambling is active, it is performed over the entire payload area including the attached CRC-16/32 for both types of scramblers. Agere Systems Inc. 675 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block--GFP General Framing Procedure Subblock (continued) GFP Scrambling/Descrambling (continued) STATE MISMATCH SYNCHRONIZATION STATE MATCH STATE MATCH OUT OF FRAME STATE MATCH STATE MISMATCH/ TRANSFER OUT OF FRAME POSTSYNCHRONIZATION OUT OF FRAME PRESYNCHRONIZATION STATE TRANSFER OUT OF FRAME STATE MISMATCH/ TRANSFER OUT OF FRAME 1635(F)r.1 Figure 92. X48 Scrambler Synchronization State Machine Packet-Over-Wavelength Mode The packet-over-wavelength mode is used for packet delivery over a link where SONET overhead insertion and extraction are bypassed. Since no SONET overhead is inserted, the TOHP and PT/SPE blocks must be configured for bypass mode. In transmitting from the MARS2G5 P-Pro to the line, the data engine passes the full payload received from the UTOPIA interface to the line at the full-line rate with no loss of bandwidth for overhead insertion. The FIFO dynamics are slightly different than in the SONET/SDH mode in this case, since there is no dead time form overhead insertion and less backpressure to the master device as a result. In the packet-over-wavelength mode, there is no SONET byte interleaving on a predefined time-slot basis; then no channelization can be done and only one channel can be active sending data. 676 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers DE Register Descriptions Table 690. General Registers (RO) Address 0x6000 Bit 15:8 7:0 Name -- DE_VERSION[7:0] Reserved. Version ID. The version of the block will increment each time a change occurs to the block functionality. Indicates version number for version 2.0. Indicates version number for version 2.2. Indicates version number for version 2.3. 0x03 0x07 Function Reset Default 0x00 0x02 Table 691. CORWN Register (R/W) Address 0x6001 Bit 15:1 0 Name -- DE_CORWN Reserved. Data Engine Registers Clear on Read Clear on Write. 0 = Clear on write. 1 = Clear on read. Table 692. TXMUX Mask Register (R/W) Address 0x6003 Bit 15:3 2:0 Name -- TXMASK Reserved. Bit 2: ATM mask. Bit 1: GFP mask. Bit 0: HDLC mask. DE Tx output is the logic OR of the outputs from HDLC, ATM, and GFP. When a mask bit is set to one, the output from the corresponding frame inserter is disabled (zero). These masks are useful to isolate the malfunctioning blocks. Table 693. RXMUX Mask Register (R/W) Address 0x6004 Bit 15:3 2:0 Name -- RXMASK Reserved. Bit 2: ATM mask. Bit 1: GFP mask. Bit 0: HDLC mask. DE Rx output is the logic OR of the outputs from HDLC, ATM, and GFP. When a mask bit is set to one, the output from the corresponding framer is disabled (zero). These mask are useful to isolate the malfunctioning blocks. Agere Systems Inc. 677 0x0 Function Reset Default 0x0 Function Reset Default Function Reset Default 0x0 0 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 694. FIFO Control (FC) Bandwidth Register (R/W) Address 0x6005 Bit 15:0 Name [15:0] Function FIFO Control (FC) Bandwidth Register. Must be set to 0x1F0A. Reset Default 0x1F07 Table 695. DE Scratch Register (R/W) Address 0x6007 Bit 15:0 Name Function Reset Default 0x0 DE_SCRATCH[15:0] DE Scratch Register. Diagnostic register used by the microprocessor. Has no effect on the device operation. Table 696. Counter Interrupts (COR/COW) Address 0x6010 Bit 15:0 Name DE_CNT_INT[15:0] Function Counter Interrupt. Active-high counter interrupt bit on a per-channel basis. This bit will remain set in COW mode until it is written with a 1, even if the underlying interrupt in 0x6ACn (channel #n) is cleared or the mask bit in 0x6A8n (channel #n) is set. Each bit is the ORing of all counter errors. An error event can be inhibited from contributing to the interrupt by setting the appropriate mask bit. These interrupts will generate a block-level interrupt. Bit-i corresponds to Channel-i interrupt. Note: This bit indicates that the counter is experiencing an interrupt. This bit will not clear on a read or a write of this register. To clear a bit in this register, it is first necessary to clear the interrupts in any unmasked bit positions in the corresponding channel packet counter interrupt register 0x6ACn (channel #n). Only then should the COW/COR operation to register 0x6010 be performed. Table 697. GFP Message Interrupts (COR/COW) Address 0x6011 Bit 15:1 0 Name -- GFP_MS_INT Reserved. GFP Message Sent Interrupt. This bit indicates that the GFP frame inserter is experiencing an interrupt. This bit will not clear on a read or a write of this register, but will clear when the GFP frame insert interrupt is read. This interrupt will generate a DE48 interrupt. 0 Function Reset Default Reset Default 0x0000 678 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 698. Composite Interrupt Register for GFP Interrupts at the Channel Level (COR/COW) Address 0x6012 Bit 15:0 Name GFP[15:0] Function This is the composite interrupt register for GFP interrupts at the channel level. Each bit in this register corresponds to a channel with the least significant bit representing the composite interrupt for channel 0 and the most significant bit representing the composite interrupt for channel 15. A bit is set in this register location when its associated channel has 1 or more unmasked bits in its GFP_IRQ register set, i.e., if a bit in 0x660n is 1 and the corresponding bit in 0x65Cn is 0, then bit n will be set. This is a COR/COW register--the bit in 0x6012 will remain set in COW mode until it is written with a 1, even if the underlying interrupt in 0x660n (channel #n) is cleared or the mask bit in 0x65Cn (channel #n) is set. Note: To clear a bit in this register, it is first necessary to clear the interrupts in any unmasked bit positions in the corresponding channel GFP_INT register. Only then should the COW/COR operation to register 0x6012 be performed. Reset Default 0x0000 Agere Systems Inc. 679 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 699. ATM Frame State Interrupts (COR/COW) Address 0x6013 Bit 15:0 Name ATM_FS_INT[0:15] Function Reset Default 0x0000 ATM Frame State Interrupt. This interrupt is generated when the ATM frame state is transitioned from sync to hunt. This register clears when read or written as defined by register 0x6001 (Table 691). These interrupts will generate a DE48 interrupt. Refer to register 0x6346 (Table 715) for information on masking these interrupts. Table 700. ATM Cool Interrupts (COR/COW) Address 0x 6014 Bit 15:0 Name Function Reset Default 0x0000 ATM_COOL_INT[0:15] ATM All-Cool Interrupt. This interrupt is generated when the payload in received idle and/or unassigned cells deviates from an incrementing pattern. This register clears when read or written as defined by register 0x6001 (Table 691). These interrupts will generate a DE48 interrupt. Table 715 contains the enable (register 0x6347 bit 1) masks (register 0x6348) for these interrupts. 680 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 701. CDA MAP0 Register (R/W) Address 0x6080-- 0x60AF Bit 15:7 6:4 3:0 Name -- -- Reserved. Reserved. Must be written to 0. Function Reset Default -- 0x40 CDA_M0_CH0[3:0]-- Used to define the channel ID for time slot 0 to 47. CDA_M0_CH47[3:0] Table 702. CDA MAP Control Register (R/W) Address 0x60BF Bit 15:2 1 0 Name -- CDA_MAP_CNTL[1] CDA_MAP_CNTL[0] Reserved. Map Control Status (RO). Map Control Register (R/W). Select MAP0 or MAP1 as working map. A working map is not available for update. Only the nonworking map is available for MPU update. 0 = Select MAP0. 1 = Select MAP1. Table 703. CDA MAP1 Register (R/W) Address 0x60C0-- 0x60EF Bit 15:7 6:4 3:0 Name -- -- Reserved. Reserved. Must be written to 0. Function Reset Default 0x00 0x40 Function Reset Default 0x0000 0 0 CDA_M1_CH0[3:0]-- Used to define the channel ID for time slot from 0 to 47. CDA_M1_CH47[3:0] Table 704. ATM Framer Idle Cell Match Mask (R/W) Address (0x6100-- 0x6101) -- (0x611E-- 0x611F) Bit 31:0 Name ATM_IDM_0-- ATM_IDM_15 Function ATM Idle Cell Match Mask Channel 0--Channel 15. This 32-bit register defines which of the 32 bits will be used for comparison between the idle cell register and the header data in the ATM framer. A 1 indicates that the corresponding bit in the ATM idle cell register should be compared. Reset Default 0xFFFFFFFF Agere Systems Inc. 681 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 705. ATM_LCD[0--15] (R/W) Address 0x6120 -- 0x612F Bit 15:6 5:0 Name -- Reserved. Function Reset Default 0x0010 ATM_LCD[0--15] Indicates number of allowable period ATM framer for channels [5:0] 0--15 allowed to be out of sync before LCD is declared for channel 0--15. The definition of period is specified in explanation for register address 0x6130. These bits are reserved in V1AAA. Table 706. ATM_LCDCLK (R/W) Address 0x6130 Bit 15:0 Name ATM_LCDCLK [15:0] Function As mentioned in Table 705, this register defines the number of 77.76 MHz clock that constitutes a period to declare LCD. These bits are reserved in V1AAA. Reset Default 0x25F7 Table 707. ATM_IN_LCD_MASK (R/W) Address 0x6131 Bit 15:0 Name ATM_IN_LCD_ MASK[15:0] Function When set (logic 1), the associated event/delta is inhibited from contributing to the interrupt on a per-channel basis. When cleared, a DE48 interrupt is generated when the corresponding bit in register 0x6133 is 1 (combinatorial mask). These bits are reserved in V1AAA. Reset Default 0xFFFF Table 708. ATM_OUT_LCD_MASK (R/W) Address 0x6132 Bit 15:0 Name ATM_OUT_LCD_ MASK[15:0] Reset Default When set (logic 1), the associated event/delta is inhibited from 0xFFFF contributing to the interrupt on a per-channel basis. When cleared, a DE48 interrupt is generated when the corresponding bit in register 0x6134 is 1 (combinatorial mask). These bits are reserved in V1AAA. Function Table 709. ATM_IN_LCD (COR/COW) Address 0x6133 Bit 15:0 Name ATM_IN_LCD [15:0] Function A 1 indicates that the corresponding channel has transitioned into the LCD state. These bits are reserved in V1AAA. Reset Default 0x0000 Table 710. ATM_OUT_LCD (COR/COW) Address 0x6134 682 Bit 15:0 Name ATM_OUT_LCD [15:0] Function A 1 indicates that the corresponding channel has transitioned out of the LCD state. These bits are reserved in V1AAA. Reset Default 0x0000 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 711. ATM Framer Idle Cell (R/W) Address 0x6180-- 0x6181 Bit 31:0 Name ATM_IDC_0 Reset Default ATM Idle Cell Register Channel 0. This 32-bit regis- 0x00000001 ter will store the expected header value for idle cells. If the ATM framer sees a header for an ATM packet that matches this register at the bit positions designated by the ATM idle cell match mask, the packet will be treated as an idle cell. ATM Idle Cell Register Channel 1 to Channel 15. 0x00000001 See above. Function (0x6182-- 0x6183) -- (0x619E-- 0x619F) 31:0 ATM_IDC_1-- ATM_IDC_15 Table 712. ATM Unassigned Cell Match/Register (R/W) Address 0x6200-- 0x6201 Bit 31:0 Name ATM_USM_0 Function ATM Unassigned Cell Match Mask Channel 0. This 32-bit register defines which of the 32 bits will be used for comparison between the unassigned cell register and the header data in the ATM framer. A 1 indicates that the corresponding bit in the ATM unassigned cell register should be compared. ATM Unassigned Cell Match Mask Channel 1 to Channel 15. See above. Reset Default 0xFFFFFFFF (0x6202-- 0x6203) -- (0x621E-- 0x621F) 31:0 ATM_USM_1-- ATM_USM_15 0xFFFFFFFF Agere Systems Inc. 683 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 713. ATM Unassigned Cell (R/W) Address 0x6280-- 0x6281 Bit 31:0 Name ATM_USG_0 Function ATM Unassigned Cell Register Channel 0. This 32-bit register will store the expected header value for unassigned cells. If the ATM framer sees a header for an ATM packet that matches this register at the bit positions designated by the ATM unassigned cell match mask, the packet will be treated as an unassigned cell. ATM Unassigned Cell Register Channel 1 to Channel 15. See above. Reset Default 0x00000000 0x6282-- 0x6283) -- (0x629E-- 0x629F) 31:0 ATM_USG_1-- ATM_USG_15 0x00000000 Table 714. ATM Frame State Channel [0--15] Registers (RO) Address 0x6300 Bit 15:2 1:0 Name -- ATM_ST_0[1:0] Reserved. ATM Frame State Channel 0. Indicates the frame state of each channel. In x43 scrambling mode (or no scrambling mode), 0x2 indicates that the ATM framer has successfully synchronized and can start passing data. ATM_ST_0[1:0] = 00--Hunt. ATM_ST_0[1:0] = 01--Presync. ATM_ST_0[1:0] = 10--Sync. ATM_ST_0[1:0] = 11--Undefine. Use this register to check for the presence of an ongoing LCD condition that started prior to device initialization. 0x6301-- 0x630F 15:0 ATM_ST_1-- ATM_ST_15 ATM Frame State Channel 1 to Channel 15. See above for description. 0x0000 Function Reset Default 0x0000 0x0 684 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 715. ATM Configuration Registers (R/W) Address Bit Name X43 Framing Register 0x6340 15:12 11:8 -- ATM_X43[11:8] Reserved. X43 Alpha. This register will define the alpha value for the X43 Alpha_Delta framer, which is the number of consecutive incorrect ATM cells that must be received in order to transition from the sync state to the hunt state. Reserved. X43 Delta. This register will define the delta value for the X43 Alpha_Delta framer, which is the number of consecutive correct ATM cells that must be received in order to transition from the presync state to the sync state. Reserved. Reserved. Reserved. Reserved. Reserved. Must be set to 0xFFFF. 0x0 0x7 Function Reset Default 7:6 5:0 -- ATM_X43[5:0] 00 0x06 0x6341 0x6342 0x6343 0x6344 0x6345 0x6346 15:0 15:0 15:0 15:0 15:0 15:0 -- -- -- -- -- 0x0708 0x0810 0x1018 0x0018 0xFFFF 0xFFFF ATM_FS_INTM[0:15] Frame State Interrupt Mask. When active (logic 1), the associated event/delta is inhibited from contributing to the interrupt on a per-channel basis. Otherwise, an interrupt is generated when the ATM frame state transitions from synchronization to hunt state. ATM Debug Rx Register -- ATM_COOL -- ATM_COOL_ INTM[0:15] Reserved. ATM All-Cool Enable. This bit must be set to 1 for proper functioning of the all-cool interrupt (Table 700). Reserved. 0x6347 15:2 1 0 0x000 0x0 0x1 0x6348 15:0 0xFFFF ATM All-Cool Interrupt Mask. When active (logic 1), the associated event/delta is inhibited from contributing to the interrupt on a per-channel basis. Otherwise, an interrupt is generated on any deviation from an incrementing data pattern in the payloads of received idle/unassigned cells. Note: To avoid unexpected interrupts, channels must be in sync and receiving idle cells before unmasking. 0x6349 15:1 0 -- -- Reserved. Reserved. For Internal Use Only. 0x0000 0x0 Agere Systems Inc. 685 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 716. Rx Channel [0--15] Payload Type and Control (R/W) Address 0x6380 Bit 15:13 12:0 Name RX_PCTL_0[15:13] RX_PCTL_0[12:0] Function Channel 0 Payload Type. Defines the payload type being received. Channel 0 Payload Control. Allows for different options when receiving data, such as pre- or post-unscrambling, PPP header discard, etc. Channel 1--15 Payload Type and Control. See description above and Table 717. Reset Default 111 000000 000000 0 0xE000 0x6381-- 0x638F 15:0 RX_PCTL_1-- RX_PCTL_15 686 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 717. Rx Payload Type and Payload Control Summary Table Payload Control[12:0] Type[15:13] 12 11 000 PPP 001 CRC 010 HDLC 011 ATM 100 GFP 101 CRC GFP 110 Transparent Payload 111 Not defined * No discard--pass all ATM cells with no error correction. Discard--discard cells with multiple-bit header errors. Correct and pass all cells with single-bit header errors. Smart discard--discard cells with multiple-bit header errors, and only correct and pass the first of back-to-back single-bit header errors. 10 0 = discard 1 = no discard 9 8 Bit Sync 1 = no invert 0 = invert Bit Sync 1 = no invert 0 = invert Bit Sync 1 = no invert 0 = invert 7 0 = byte sync 1 = bit sync 6 0 = header stripped 1 = header on 5 4 3 2 1 0 0 = CRC-16 0 = CRC stripped 0 = CRC reversed 0 = no dry mode 1 = CRC-32 1 = CRC on 1 = CRC normal 1 = dry mode 00 = no unscrambling 01 = post-unscrambling 10 = pre-unscrambling 11 = undefined 00 = no unscrambling 01 = post-unscrambling 10 = pre-unscrambling 11 = undefined 00 = no unscrambling 01 = post-unscrambling 10 = pre-unscrambling 11 = undefined 00 = no discard* 01 = discard 10 = smart discard 11 = undefined 0 = byte sync 1 = bit sync 0 = CRC-16 0 = CRC stripped 0 = CRC reversed 0 = no dry mode 1 = CRC-32 1 = CRC on 1 = CRC normal 1 = dry mode 0 = byte sync 1 = bit sync 0 = no dry mode 1 = dry mode 0 = X43 scrambler 0 = scrambler on 0 = byte sync 1 = scrambler off 1 = bit sync Unassigned Cell 0 = discard 1 = passthrough 0 = length stripped 1 = length on 0 = idle cell discard 1 = idle cell passthrough 0 = X43 scrambler 0 = scrambler on 0 = byte sync 1 = X48 scrambler 1 = scrambler off 1 = bit sync See Table 717 below for 0 = X43 scrambler 0 = scrambler on 0 = byte sync description of bits [12:10]. 1 = X48 scrambler 1 = scrambler off 1 = bit sync 0 = no align 1 = frame align Length offset = 0x0 to 0xF 0 = length 0 = CRC-16 0 = CRC stripped Length offset = 0x0 to 0xF stripped 1 = CRC-32 1 = CRC on 1 = length on Table 717. Rx Payload Type and Payload Control Summary Table (continued) Note: This is an expansion of Table 717 for Rx payload type CRC GFP bits [12:10] and applies to only version 2.2 and 2.3 of the device. 12 0 = Indicates non-GFP mode. 1 = Must be set to1 in CRC-GFP mode. 11 0 = PLI field unchanged. 1 = Subtract four from the PLI field if the CRC-32 bytes are stripped. 10 0 = Start CRC calculation after first 32 bits of payload (i.e., assume null extension header. 1 = Start CRC calculation after first 64 bits of payload (i.e., assume linear extension header. Agere Systems Inc. 687 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine (DE) Block (continued) DE Register Descriptions (continued) Table 718. GFP State Register (R/W, RO) Note:This register is nonfunctional for all versions of the device. In version 2.3 of the device, the function of this register has been moved to registers 0x6600--0x660F (Table 727). Address 0x6400 Bit 15:8 7:4 Name -- GFP_ST_0 Reserved. Audit CHID (R/W). Indicates which channel is selected for audit. To get the GFP state in a particular channel, write the channel ID into bit 7:4. Then read this register, GFP state is in bit 3:0. 3:2 GFP Frame State (RO). Indicates the frame state of each channel. 00 = Out of frame. 01 = Presync. 10 = Sync. 11 = Undefined. 1:0 GFP Scram State (RO). Indicates the X48 sync state of each channel. 00 = Hunt. 01 = Sync. 10 = Postsync. 11 = Undefined. Table 719. Registers 0x6470--0x6473 A Message Mailbox Registers (RO) Address 0x6440 -- 0x644F Bit 15:0 Name GFP_AMM0_1 -- GFP_AMM15_1 Function A Message Mailbox Channel 0--15. These registers will store the first 16 bits of a valid A message. Reset Default 0x0000 0x0 0x0 0x0000 Function Reset Default Table 720. A Message Mailbox Registers (RO) Address 0x6480 -- 0x648F Bit 15:0 Name GFP_AMM0_2 -- GFP_AMM15_2 Function A Message Mailbox Channel 0--15. These registers will store the middle 16 bits of a valid A message. Reset Default 0x0000 688 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine (DE) Block (continued) DE Register Descriptions (continued) Table 721. Registers 1168--1171 A Message Mailbox Registers (RO) Address 0x64C0 -- 0x64CF Bit 15:0 Name GFP_AMM0_3 -- GFP_AMM15_3 Function A Message Mailbox Channel 0--15. These registers will store the last 16 bits of a valid A message. Reset Default 0x0000 Table 722. Registers 1184--1187 B Message Mailbox Registers (RO) Address 0x6500 -- 0x650F Bit 15:0 Name GFP_BMM0_1 -- ADL_BMM15_1 Function B Message Mailbox Channel 0--15. These registers will store the first 16 bits of a valid B message. Reset Default 0x0000 Table 723. B Message Mailbox Registers (RO) Address 0x6540 -- 0x654F Bit 15:0 Name GFP_BMM0_2 -- GFP_BMM15_2 Function B Message Mailbox Channel 0--15. These registers will store the middle 16 bits of a valid B message. Reset Default 0x0000 Table 724. B Message Mailbox Registers (RO) Address 0x6580 -- 0x658F Bit 15:0 Name GFP_BMM0_3 -- GFP_BMM15_3 Function B Message Mailbox Channel 0--15. These registers will store the last 16 bits of a valid B message. Reset Default 0x0000 Agere Systems Inc. 689 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine (DE) Block (continued) DE Register Descriptions (continued) Table 725. GFP Interrupt Masks R/W Address 0x65C0 -- 0x65CF Bit -- Name Function Reset Default 0x00FF GFP_IRQEN_CH0 GFP Interrupt Mask Channel 0--15. When active (logic 1), -- the associated event/delta is inhibited from contributing to GFP_IRQEN_CH15 the interrupt on a per-channel basis. -- -- -- -- -- -- -- -- -- -- Reserved. B_Message Reception. A_Message Reception. Uncorrectable Special Payload Error. Uncorrectable Bit Error. Reserved. Must be set to 1. Single Bit Error. Scrambler Out of Sync. Framer State Mask Bit. Must be set to 1. This bit applies to only version 2.3 of the device. Framer Out of Sync. This bit applies to only versions 2.0 and 2.2 of the device. 15:8 7 6 5 4 3 2 1 0 0 0x00 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Determining the Per-Channel Framer State (Applies to Only Version 2.3 of the Device) Bit 4 and bit 0 of registers 0x6600--0x660F (Table 727) are used to determine the per-channel framer state. The following table indicates the per-channel framer state (see bit 0 of registers 0x6600--0x660F (Table 727)). Table 726. Per-Channel Framer State Uncorrectable Bit Error (Bit 4) 0 0 1 1 Framer State (Bit 0) 0 1 0 1 Per-Channel Framer State Out of frame In frame Undefined (not possible) Framing was lost since the last read of this register. Perform a COW, and then read again to confirm if framing is still lost. 690 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine (DE) Block (continued) DE Register Descriptions (continued) Table 727. GFP Interrupts (COW) Address 0x6600 -- 0x660F Bit -- Name GFP_IRQ_CH0 -- GFP_IRQ_CH15 -- -- -- -- -- -- -- -- -- Function GFP Interrupt Channel 0--15. Used to record various occurrences within the GFP framer. The bits will generate an interrupt if defined by the interrupt mask, but the register values here are independent of the interrupt mask values. Reserved. B_Message Reception. A_Message Reception. Uncorrectable Special Payload Error. Uncorrectable Bit Error. Reserved. Single Bit Error. Scrambler Out of Sync. Framer State. This bit is a state bit and must always be masked to prevent constant presentation of an interrupt to the MPU. Bit 0 of registers 0x65C0--0x65CF (Table 725) is the mask bit. The value contained in this bit will persist until a COW is performed, or until a transition (from 0 to 1) occurs on the signal. To determine the per-channel frame state, see Table 726. This bit applies to only version 2.3 of the device. 0 -- Framer Out of Sync. This bit applies to only versions 2.0 and 2.2 of the device. Table 728. GFP Receive Configuration Registers (R/W) Address 0x6640 Bit -- 15:5 4 Name -- -- GFP_MODE Function CRC-16 Framing Register. Reserved. Framer Mode. When set, this bit disables all but the first framer. A 1 implies single framer mode. When cleared to 0, all three framers are used to acquire frame lock. Framer Delta. This register defines the delta value for the CRC-16 framer. A value of 0 programmed into this register implies a delta value of 1. Reset Default 0x0001 0x000 0 0x0 Reset Default 0x0000 15:8 7 6 5 4 3 2 1 0 0x00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 3:0 GFP_DELTA 0x1 Agere Systems Inc. 691 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 729. PPP Detach Channel 0--15 PPP Protocol Check (R/W) Address 0x6680 Bit -- Name -- Function Channel 0 PPP Protocol Check. Instead of using the Rx payload control register to control stripping, this register can be used to control whether to keep or strip both CRC and PPP header fields as indicated below. If a protocol check is enabled and matches, the indicated header field will be stripped. See PPP Header Detach on page 645 for a detailed explanation. Reserved. A 1 value in this bit will enable a protocol 0x8021 check. A 1 value in this bit will enable a protocol 0x0021 check. A 1 value in the bit i enables the corresponding protocol stored in the register--PPP_RX_HDR[i], for checking. PPP_PROTOCOL _CONTROL1 -- PPP_PROTOCOL _CONTROL15 Channel 1--15 PPP Protocol Check. See above. Reset Default 0x0000 15:14 13 12 11:0 0x6681-- 0x668F 15:0 -- PPP_PROTOCOL _CONTROL0 00 0 0 0x000 0x0000 Table 730. PPP Detach Programmable PPP Protocol Register 0--11 (R/W) Address 0x66B0-- 0x66BB Bit 15:0 Name PPP_RX_HDR0-- PPP_RX_HDR11 Function Reset Default Programmable PPP Protocol Register 0--11. This regis- 0x0000 ter defines the 2-byte protocol that can be used by all channels to validate the receiving PPP packets. This can be used to compare any received PPP headers from different channels to this value. If there is a mismatch, then the bad header counter will increment by one. 692 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 731. PPP Detach Channel 0--15 PPP Header Search (R/W) Address 0x66C0 Bit -- Name -- Function Channel 0 PPP Header Search. This register will control the headers that channel 0 PPP detach block looks for. If there is a match with any of the headers, a good packet will be noted in the counter. Otherwise, a bad header will be noted in a separate counter. Controls the way the PPP headers are searched for and passed through. 00 = Wildcard match mode. Passes all packets with uncompressed PPP headers. In other words, all packets starting with the value 0xFF03 are matched. 01 = Pass only packets with uncompressed PPP headers and one of more of the 14 PPP protocol values that can be specifically selected (as described below). In other words, packets are matched if the first 2 bytes are 0xFF03 and the following bytes are one of the (possibly several) specifically selected protocol values. 10 = Pass only packets with compressed PPP headers and a PPP protocol value that is specifically selected by settings described below. In other words, packets are matched if the first 2 bytes are one of the (possibly several) specifically selected protocol values. 11 = Pass only packets with a PPP protocol value that is specifically selected by settings described below. (i.e., protocol values are matched without regard to whether or not the header is compressed). In other words, this represents a combination #1 and #2 above. A packet is matched if the first 2 bytes are 0xFF03 and following 2 bytes are any one of the specifically selected protocol values OR if the first 2 bytes of the packet match any one of the specifically selected protocol values. 13 12 11:0 0x66C1-- 0x66CF 15:0 A 1 value in this bit will enable a search for the 16-bit fixed value 0x8021. A 1 value in this bit will enable a search for the 16-bit fixed value 0x0021. A 1 value in bit i will enable a search of the 16-bit value in the corresponding register PPP_RX_HDR[i]. PPP_RX_CHK_CH1 Channel 1--15 PPP Header Search. See above. -- PPP_RX_CHK_CH15 0 0 0x000 0x0000 Reset Default 0x0000 15:14 PPP_RX_CHK_CH0 00 Agere Systems Inc. 693 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 732. ATM Null Cell Register in TX (R/W) Address 0x6700-- 0x6701 Bit 15:0 Name NULL_CELL_CH0 [31:16] 0x6700 [15:0] 0x6701 Function ATM Null Cell MSB Channel 0. This defines the 4 bytes (H0H1H2H3) of a null ATM cell. (i.e., 31:0 = H0H1H2H3 with H0H1 at 0x6700, H2H3 at 0x6701). It is important to always provision all bytes (i.e., write both the low and the high 16-bit word) whenever changing any of these values, even if the user only wants to change one or two of the header bytes. Otherwise, if only one half is written, the other half may be corrupted. The order of writing does not matter, since either the high half or the low half can be written first. It is important to remember to program both halves of the word. Reset Default* 0x0000 -- 0x0001 (0x6702-- 0x6703) -- (0x671E-- 0x671F) 15:0 NULL_CELL_CH1-- ATM Null Cell MSB Channel 1--15. See above. NULL_CELL_CH15 0x0000 -- 0x0001 * The reset default of the least significant byte (bits [7:0]) of the combined registers forming the 32-bit parameter is 0x01. 694 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 733. ATM Header Error Register in Tx (R/W) Address 0x6780 Bit -- Name -- Function ATM Tx Debug Control. Used for debug purposes to inject errors, and use and incrementing payload sequence for NULL cells. Error Strobe. Writing a 1 to this register initiates the injection of a single or double shot error injection, assuming one of these two modes is selected. Incrementing NULL Cell Payload Sequence. This bit governs whether 0x6A is used for the payload of NULL cells, or whether an incrementing 8-bit count is used (0x00 --0xFF). A 1 selects the incrementing sequence. This can be used with a detector in the receiver. Reserved. Reset Default 0x0000 15 -- 0 14 -- 0 13:8 7:4 3:2 -- 0x0 0x0 00 ATM_HEADER_ERR Error Channel ID. The logical channel to inject header errors. -- Error Type. These bits control the injection of a walking error pattern into the headers of all outgoing cells. 00 = No errors. 01 = Single bit errors. 10, 11 = Double bit errors. 1:0 -- Error Fire Mode. These bits control the mode of operation of the error injection. 00 = Continuous injection. 01 = Single shot (isolated cell). 10, 11 = Double shot (i.e., 2 back-to-back cells). 00 0x6781 15:1 0 -- -- Reserved. Reserved. For Internal Use Only. -- 0x0 Table 734. CRC Transmit Registers (R/W) Address 0x6790 Bit 15:0 Name CRC_ERR[15:0] Function CRC Error Injection for Channels 15 to 0. This register is used to configure which channels will generate a single bit error within the CRC. When 1, a single bit CRC error is inserted into channel i. Reset Default 0x0000 Agere Systems Inc. 695 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 735. GFP Transmit Registers (R/W) Address 0x67A0 0x67A1 0x67A2 0x67A3 Bit 15:0 15:0 15:0 -- 14:6 7:4 3:1 0 -- Name GFPFI_MSG_1 GFPFI_MSG_2 GFPFI_MSG_3 Function GFP Message. These registers will store the first 16 bits of a header for a special message to be sent. GFP Message. These registers will store the middle 16 bits of a header for a special message to be sent. GFP Message. These registers will store the last 16 bits of a header for a special message to be sent. Reserved. Channel ID. Defines which channel the special message will be transmitted on. Reserved. Message Bit. 0 = A message. 1 = B message. 0x67A4 15:0 GFPFI_INT GFP State Transmit Interval. Defines the number of packets (or dWords) separating scrambler state transmissions. Use register GFPFI_MODE register to determine if units are packets or dwords. GFP State Transmit Mode. Interrupt Enable. When active (logic 1), the associated event/delta is inhibited from contributing to the interrupt on a per-channel basis. In this case, used to signal the sending of a special message (A or B message). Reserved. Message Bit. 0 = GFP state transmit interval (register 0x67A4) is measured in packets. 1 = GFP state transmit interval (register 0x67A4) is measured in dwords. * To transmit the GFP message. The controls in this register (0x67A3) must be set up first. The message must then be entered, beginning with register 0x67A0 then 0x67A1. When the last 2 bytes of the message are written to register 0x67A2, the message is immediately queued for transmission. Reset Default 0x0000 0x0000 0x0000 0x0000 GFPFI_MSG_TYPE GFP Message Type*. -- 0x0008 0x67A5 -- 15 GFPFI_MODE -- 0x8000 0x1 14:1 0 -- -- 0x0 0x0 696 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 736. GFP Transmit Registers (RO) Address 0x67A6 Bit 15:0 15:1 0 Name GFPFI_INTR -- Status Register. Reserved. Message Sent Interrupt. When 1, this indicates that a GFP special message has been sent. This value may be cleared when read or written. Function Reset Default 0x0000 Table 737. GFP Transmit Registers (R/W) Address 0x67A7 Bit 15 Name -- Function Header Error Strobe. Write to a 1 to start header errors. Each error will start in the next bit position, effectively walking through the entire header. Payload Error Strobe. Write to a 1 to start payload (message or scramstate) errors. Each error will start in the next bit position, effectively walking through the entire payload. Reserved. Payload Error Mode. 1 = one shot, 0 = continuous. Header Error Mode. 1 = one shot, 0 = continuous. Error Channel ID. Specifies the channel on which the errors are to be sent. Payload Error. This value indicates the number of errors to insert in the payload of special packets on a given channel for debug purposes. The error injection is done using a walking ones pattern to cover all possibilities. 00 = No errors. 01 = Single error. 10 = Double error. 11 = Undefined. 1:0 -- Header Error. This value indicates the number of errors to insert in the GFP header on a given channel for debug purposes. The error injection is done using a walking ones pattern to cover all possibilities. 00 = No errors. 01 = Single error. 10 = Double error. 11 = Undefined. 0x0 Reset Default 0 14 -- 0 13:10 9 8 7:4 3:2 -- -- -- -- -- 0000 0 0 0000 0x0 Agere Systems Inc. 697 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 738. HDLC-Tx Dry Character Address 0x67B0 Bit 15:8 7:0 Name DRY_CHARACTER [15:8] DRY_CHARACTER [7:0] Reserved. Dry Character. This register will define the dry character value for HDLC-TX. Function Reset Default 0x00 0x00 Table 739. HDLC-Tx FIFO Threshold Address 0x67B1 Bit 15:8 7:0 Name HDLC_FIFO_TH [15:8] HDLC_FIFO_TH [7:0] Reserved. This register will define the FIFO threshold used in the blank feedback control for HDLC-TX. Must remain set at 0x38 for proper operation. See Table 741. Function Reset Default 0x00 0x38 Table 740. Tx Payload Type and Control (R/W) Address 0x67C0 Bit 15:13 12:0 Name TX_PCTL_0[15:13] TX_PCTL_0[12:0] Function Channel 0 Payload Type. Defines the payload type being received. Channel 0 Payload Control. Allows for different options when transmitting data, such as pre- or postscrambling, dry mode, PPP header discard, etc. Channel 1--15 Payload Type and Control. See description above and Table 741. Reset Default 111 000000 000000 0 0xE000 0x67C1-- 0x67F 15:0 TX_PCTL_1-- TX_PCTL_15 698 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 741. Tx Payload Type and Payload Control Summary Table Payload Control[12:0] Payload Type[15:13] 000 PPP 001 CRC 010 HDLC 011 ATM 100 GFP 101 CRC GFP 110 Transparent Payload 111 Not Defined See Table 741 below for description of bits [12:10]. 12 0 = leading 1 = trailing 11 10 9 8 7 0 = HDLC byte 1 = HDLC bit 6 5 0 = CRC-16 1 = CRC-32 4 3 2 1 0 00 = 1 flag between packet Bit-Sync Inter-Pckg-Fill Bit Sync 01 = 2 flags between packets 0 = 7E 1 = no invert 0 = invert 10 = 3 flags between packets 1 = FF 11 = 4 flags between packets 00 = 1 flag between packet Bit-Sync Inter-Pckg-Fill Bit Sync 01 = 2 flags between packets 0 = 7E 1 = no invert 10 = 3 flags between packets 1 = FF 0 = invert 11 = 4 flags between packets 00 = 1 flag between packet Bit-Sync Inter-Pckg-Fill Bit Sync 01 = 2 flags between packets 0 = 7E 1 = no invert 10 = 3 flags between packets 1 = FF 0 = invert 11 = 4 flags between packets 0 = X43 scrambler 0 = scrambler on 1 = scrambler off 0 = scrambler on 1 = scrambler off 0 = scrambler on 1 = scrambler off 0 = CRC reversed 0 = no dry mode 1 = CRC normal 1 = dry mode 00 = no scrambling 01 = postscrambling 10 = prescrambling 11 = undefined 00 = no scrambling 01 = postscrambling 10 = prescrambling 11 = undefined 00 = no scrambling 01 = postscrambling 10 = prescrambling 11 = undefined 0 = leading 1 = trailing 0 = HDLC byte 1 = HDLC bit 0 = CRC-16 1 = CRC-32 0 = CRC reversed 0 = no dry mode 1 = CRC normal 1 = dry mode 0 = leading 1 = trailing 0 = HDLC byte 1 = HDLC bit 0 = no dry mode 1 = dry mode 0 = X43 scrambler 1 = X48 scrambler 0 = X43 scrambler 1 = X48 scrambler 0 = CRC-16 1 = CRC-32 Table 741. Tx Payload Type and Payload Control Summary Table (continued) Note: This is an expansion of Table 741 for Rx payload type CRC GFP bits [12:10] and applies to only version 2.2 and 2.3 of the device. 12 0 = Indicates non-GFP mode. 1 = Must be set to 1 in CRC-GFP mode. 11 0 = PLI field unchanged. 1 = Add four to the PLI field to include CRC-32 bytes. 10 0 = Start CRC calculation after first 32 bits of payload (i.e., assume null extension header). 1 = Start CRC calculation after first 64 bits of payload (i.e., assume linear extension header). Agere Systems Inc. 699 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 742. ATM/HDLC/GFP Framer--Condition Counter 1 (PMRST Update) (RO) Address 0x6800-- 0x6801 Bit 31:0 31:28 27:16 15:0 Name PM_FC1_0 Reserved MSB of register LSB of register Function ATM/HDLC/GFP Counter 1 Channel 0. Keeps a count of conditions detected by the data framer in the particular channel. This value is updated upon PMRST and the real-time counter value is reset to zero. This register can represent only one of the following based upon the channel's payload type. 1. ATM single-bit error. 2. HDLC invalid sequence. 3. GFP corrected header. (0x6802-- 0x6803) -- (0x681E-- 0x681F) 31:0 PM_FC1_1-- PM_FC1_15 ATM/HDLC/GFP Counter 1 Channel 1--15. See above. 0x0000000 Reset Default 0x0000000 Table 743. ATM/HDLC/GFP Framer--Condition Counter 2 (PMRST Update) (RO Address 0x6880-- 0x6881 Bit 31:0 31:28 27:16 15:0 Name PM_FC2_0 Reserved MSB of register LSB of register Function ATM/HDLC/GFP Counter 2 Channel 0. Keeps a count of conditions detected by the data framer in the particular channel. This register can represent only one of the following based upon the channel's payload type. 1. ATM discarded cell. 2. ATM errored header. 3. GFP errored header. This value is updated upon PMRST, and the real-time counter value is reset to zero. (0x6882-- 0x6883) -- (0x689E-- 0x689F) 31:0 PM_FC2_1-- PM_FC2_15 ATM/HDLC/GFP Counter 2 Channel 1--15. See above. 0x0000000 Reset Default 0x0000000 700 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 744. CRC Checker--Bad Packet Counter (PMRST Update) (RO) Address 0x6900-- 0x6901 Bit 31:0 31:28 27:16 15:0 31:0 Name PM_BPC_0 Reserved MSB of register LSB of register PM_BPC_1-- PM_BPC_15 Function CRC Bad Packet Counter Channel 0. Keeps a count of bad packets detected by the CRC checker. This value is updated upon PMRST, and the real-time counter value is reset to zero. CRC Bad Packet Counter Channel 1--15. See above. Reset Default 0x0000000 (0x6902-- 0x6903) -- (0x691E-- 0x691F) 0x0000000 Table 745. PPP Detach--Bad Header Counter (PMRST Update) (RO) Address 0x6980-- 0x6981 Bit 31:0 31:28 27:16 15:0 31:0 Name PM_BHC_0 Reserved MSB of register LSB of register PM_BHC_1-- PM_BHC_15 Function Reset Default PPP Bad Header Counter Channel 0. Keeps a count 0x0000000 of bad packets detected by the PPP detach block. This value is updated upon PMRST, and the real-time counter value is reset to zero. PPP Bad Header Counter Channel 1--15. See above. 0x0000000 (0x6982-- 0x6983) -- (0x699E-- 0x699F) Table 746. Interrupts and Interrupt Masks for Packet Counters (R/W) Address 0x6A80 Bit -- Name -- Function Channel 0 Data Interrupt Mask. When active (logic 1), the associated event/delta is inhibited from contributing to the interrupt on a per-channel basis. Reserved. Reserved. PPP Bad Header. CRC Bad Packet. ATM/HDLC/GFP Counter 2. ATM/HDLC/GFP Counter 1. -- INT_EN_CH1-- INT_EN_CH15 Reserved. Channel 1 to Channel 15 Data Interrupt Mask. See above. Reset Default 0x001F 15:5 4 3 2 1 0 0x6A81-- 0x6A8F 15:4 3:0 -- -- INT_EN_CH0 000000 00000 1 1 1 1 1 0x001F Agere Systems Inc. 701 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Descriptions (continued) Table 747. Interrupts for Packet Counters (COR/COW) Address 0x6AC0 Bit -- 15:4 3 2 1 0 0x6AC1-- 0x6ACF 15:4 3:0 -- INT_ST_CH1-- INT_ST_CH15 Name -- -- INT_ST_CH0 Function Channel 0 Data Interrupt. Stores bits that describe which conditions of corrupted data exist in channel 0. Reserved. PPP Bad Header. CRC Bad Packet. ATM/HDLC/GFP Counter 2. ATM/HDLC/GFP Counter 1. Reserved. Channel 1 to Channel 15 Data Interrupt. See above. Reset Default 0x0000 0x000 0 0 0 0 0x0000 Table 748. Transmit (Tx) Good Packet Counter (PMRST Update) (RO) Address 0x6B00-- 0x6B01 Bit 31:0 31:28 27:16 15:0 31:0 Name PM_GPC_TX_0 Reserved MSB of register LSB of register PM_GPC_TX_1-- PM_GPC_TX_15 Function Reset Default Transmit Good Packet Counter Channel 0. Keeps a 0x0000000 count of good packets transmitted in the TX direction. In ATM mode, idle cells are not included in the count. The counter value is updated upon PMRST, and the real-time counter value is reset to zero. Transmit Good Packet Counter Channel 1--15. See 0x0000000 above. (0x6B02-- 0x6B03) -- (0x6B1E-- 0x6B1F) 702 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map Table 749. DE Register Map Note: Shading denotes reserved bits. Addr 0x6000 0x6001 Symbol -- -- Type RO R/W 15 14 13 12 11 10 Misc DE_VERSION[7:0] DE_C ORW N TXMASK RXMASK [15:0] DE_SCRATCH[15:0] Interrupts 0x6010 DE48_CNT_ COR/ INT COW 0x6011 0x6012 0x6013 GFP_MS_ INT GFP ATM_FS_ INT COR/ COW COR/ COW COR/ COW DE_CNT_INT[15:0] GFP_MS_INT[15:0] GFP_INT[15:0] ATM_FS_INT[0:15] ATM_COOL_INT[15:0] 9 8 7 6 5 4 3 2 1 0 0x6002 0x6003 0x6004 0x6005 0x6006 0x6007 -- -- -- -- -- -- -- R/W R/W R/W -- R/W 0x6014 ATM_COOL COR/ _INT COW 0x6015 -- -- Agere Systems Inc. 703 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6080 -- 0x60AF 0x60B0 -- 0x60BE 0x60BF 0x60C0 -- 0x60EF 0x60F0 -- 0x60FF Symbol CDA_M0_CHy Type 15 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CDA_M0_CH0[3:0] -- CDA_M0_CH47[3:0] 0 CDA Map and Control Register -- -- CDA_MAP_CNTL CDA_M1_CHy R/W R/W CDA_MAP_CNTL[1] CDA_MAP_CNTL CDA_M1_CH0[3:0] -- CDA_M1_CH47[3:0] -- -- ATM Framer Registers Idle Cell Match Mask (R/W) 0x6100 0x6101 to 0x611E 0x611F -- -- -- -- -- R/W R/W R/W R/W R/W ATM_IDM_0[31:16] ATM_IDM_0[15:0] to ATM_IDM_15[31:16] ATM_IDM_15[15:0] 704 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6120 -- 0x612F 0x6130 0x6131 0x6132 0x6133 0x6134 0x6180 0x6181 to 0x619E 0x619F 0x6200 0x6201 to 0x621E 0x621F 0x6280 0x6281 to 0x629E 0x629F Agere Systems Inc. Symbol ATM_LCD[0--15] Type R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCD Registers ATM_LCD[0--15][5:0] ATM_LCDCLK ATM_IN_LCD_MASK ATM_OUT_LCD_MASK ATM_IN_LCD ATM_OUT_LCD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R/W R/W R/W COR/COW COR/COW Idle Cell Register (R/W) R/W R/W R/W R/W R/W ATM_LCDCLK[15:0] ATM_IN_LCD_MASK[15:0] ATM_OUT_LCD_MASK[15:0] ATM_IN_LCD[15:0] ATM_OUT_LCD[15:0] ATM_IDC_0[31:16] ATM_IDC_0[15:0] to ATM_IDC_15[31:16] ATM_IDC_15[15:0] Unassigned Cell Match Mask (R/W) ATM_USM_0[31:16] ATM_USM_0[15:0] to ATM_USM_15[31:16] ATM_USM_15[15:0] Unassigned Cell Register (R/W) ATM_USG_0[31:16] ATM_USG_0[15:0] to ATM_USG_15[31:16] ATM_USG_15[15:0] 705 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6300 -- 0x630F 0x6340 0x6341 0x6342 0x6343 0x6344 0x6345 0x6346 0x6347 0x6348 0x6349 Symbol -- Type RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATM Framer State (RO) ATM Control Registers (R/W) -- -- -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W -- ATM_COOL_INTM[0:15] ATM_FS_INTM[0:15] ATM_ COOL ATM_X43[11:8] (Alpha) ATM_X43[5:0] (Alpha) 706 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6380 -- 0x638F 0x6400 0x6401 -- 0x643F 0x6440 -- 0x644F 0x6450 -- 0x647F 0x6480 -- 0x648F 0x6490 -- 0x64BF 0x64C0 -- 0x64CF 0x64D0 -- 0x64FF Symbol -- Type R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID (R/W) RX_PCTL_0[15:0] -- RX_PCTL_15[15:0] GFP Receive Registers (R/W) -- -- RO -- GFP_ST_0[7:0] -- R/W GFP_AMM0_1[15:0] -- GFP_AMM15_1[15:0] -- -- -- R/W GFP_AMM0_2[15:0] -- GFP_AMM15_2[15:0] -- -- -- R/W GFP_AMM0_3[15:0] -- GFP_AMM15_3[15:0] -- -- Agere Systems Inc. 707 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6500 -- 0x650F 0x65A0 -- 0x653F 0x6540 -- 0x654F 0x6550 -- 0x657F 0x6580 -- 0x658F 0x6590 -- 0x65BF Symbol -- Type R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GFP_BMM0_1[15:0] -- GFP_BMM15_1[15:0] -- -- -- R/W GFP_BMM0_2[15:0] -- GFP_BMM15_2[15:0] -- -- -- R/W GFP_BMM0_3[15:0] -- GFP_BMM15_3[15:0] -- -- 708 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x65C0 -- 0x65CF 0x65D0 -- 0x65FF 0x6600 -- 0x660F 0x66A0 -- 0x663F 0x6640 Symbol -- Type R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GFP_IRQEN_CH0[7:0] -- GFP_IRQEN_CH15[7:0] -- -- -- COW GFP_IRQ_CH0[7:0] -- GFP_IRQ_CH15[7:0] -- -- -- R/W GFP_ MOD E GFP_DELTA[3:0] 0x6641 -- 0x667F -- -- Agere Systems Inc. 709 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6680 -- 0x668F 0x6690 -- 0x66AF 0x66B0 -- 0x66BB 0x66BC -- 0x66BF 0x66C0 -- 0x66CF 0x66D0 -- 0x66FF Symbol -- Type R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPP Detach Registers (R/W) PPP_PROTOCOL_CONTROL0[15:0] -- PPP_PROTOCOL_CONTROL15[15:0] -- -- -- R/W PPP_RX_HDR00[15:0] -- PPP_RX_HDR11[15:0] -- -- -- R/W PPP_RX_CHK_CH0[15:0] -- PPP_RX_CHK_CH15[15:0] -- -- 710 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6700 0x6701 to 0x671E 0x671F 0x6720 -- 0x677F 0x6780 0x6781 -- 0x678F Symbol -- -- -- -- -- -- Type R/W R/W -- R/W R/W -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATM Transmit Registers (R/W, RO) NULL_CELL_CH0[31:16] NULL_CELL_CH0[15:0] to NULL_CELL_CH15[31:16] NULL_CELL_CH15[15:0] -- -- R/W -- ATM_HEADE R_ERR[9:8] ATM_HEADER_ERR[7:0] Agere Systems Inc. 711 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6790 0x6791 -- 0x679F 0x67A0 0x67A1 0x67A2 0x67A3 Symbol -- -- Type R/W -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRC Transmit Registers (R/W) CRC_ERR[11:0] GFP Transmit Registers (R/W, RO) -- -- -- -- R/W R/W R/W R/W GFPFI_MSG_1[15:0] GFPFI_MSG_2[15:0] GFPFI_MSG_3[15:0] GFPFI_MSG_TYPE[7:4] GFPF I_MS G_TY PE[0] GFPFI_MOD E[1:0] 0x67A4 0x67A5 -- -- R/W R/W GFPF I_MO DE[1 5] GFPFI_INT[15:0] 0x67A6 -- RO GFPF I_INT R[0] -- -- -- -- -- -- -- -- -- -- -- -- 0x67A7 0x67A8 -- 0x67AF -- -- R/W -- 712 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x67B0 0x67B1 0x67B2 -- 0x67BF 0x67C0 -- 0x67CF 0x67C0 --0x67FF 0x6800 0x6801 to 0x681E 0x681F 0x6820 --0x687F Symbol -- -- -- Type R/W R/W -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDLC Transmit Registers (R/W) DRY_CHARACTER[7:0] HDLC_FIFO_TH[7:4] (LOW) HDLC_FIFO_TH[3:0] (HIGH) Gap Inserter Registers (R/W) -- R/W TX_PCTL_0[15:0] -- TX_PCTL_15[15:0] -- -- ATM/HDLC Counter 1 (PMRST Update) (RO) -- -- -- -- -- -- RO RO -- RO RO -- to PM_FC1_0[27:16] PM_FC1_0[15:0] PM_FC1_15[27:16] PM_FC1_15[15:0] Agere Systems Inc. 713 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6880 0x6881 to 0x689E 0x689F 0x68A0 to 0x68AF 0x6900 0x6901 to 0x691E 0x691F 0x6920 --0x697F Symbol -- -- -- -- -- -- Type RO RO -- RO RO -- to PM_FC2_15[27:16] PM_FC2_15[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATM/HDLC Counter 2 (PMRST Update) (RO) PM_FC2_0[27:16] PM_FC2_0[15:0] CRC Checker Bad Packet Counter (PMRST Update) (RO) -- -- -- -- -- -- RO RO -- RO RO -- to PM_BPC_15[27:16] PM_BPC_15[15:0] PM_BPC_0[27:16] PM_BPC_0[15:0] 714 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Engine Block Registers (continued) DE Register Map (continued) Table 749. DE Register Map (continued) Note: Shading denotes reserved bits. Addr 0x6980 0x6981 to 0x699E 0x699F 0x69A0 --0x69AF 0x6A00 --0x6A7F 0x6A80-- 0x6A8F 0x6A90 --0x6ABF 0x6AC0-- 0x6ACF 0x6AD0 --0x6AFF 0x6B00 0x6B01 to 0x6B1E 0x6B1F 0x6B20 --0x6FFF Symbol -- -- -- -- -- -- -- Type RO RO -- RO RO -- -- Counter Block Control/Status (R/W, RO) -- R/W INT_EN_CH0[3:0] -- INT_EN_CH15[3:0] 15 14 13 12 11 10 9 8 7 6 5 4 PPP Detach Bad Header Counter (PMRST Update) (RO) PM_BHC_0[27:16] PM_BHC_0[15:0] to PM_BHC_15[27:16] PM_BHC_15[15:0] 3 2 1 0 -- -- -- COR/ COW -- Transmit Good Packet Counter (PMRST Update) (RO) PM_GPC_TX_0[27:16] PM_GPC_TX_0[15:0] to PM_GPC_TX_15[27:16] PM_GPC_TX_15[15:0] INT_ST_CH0[3:0] -- INT_ST_CH15[3:0] -- -- -- -- -- -- -- RO RO -- RO RO -- Agere Systems Inc. 715 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block This section describes the UTOPIA block (known as the UT48 core) of the MARS2G5 P-Pro device. The UTOPIA block is responsible for transporting ingress and egress traffic through the UTOPIA interface. It supports all the features of MARS2G5 P-ProLT UTOPIA interface with some additional enhancements while maintaining backward compatibility. The PHY interface of the UTOPIA block has the same pins as MARS2G5 P-ProLT as well as some additional pins to allow support of more channels. UTOPIA Interface Features Conformance to ATM forum UTOPIA level 2 and level 3 specifications. Support for PLATO packet-over-SONET UTOPIA extensions. Support for 52/53-byte ATM cells in 8-bit mode, 52/54-byte cells in 16-bit mode, 52/56-byte cells in 32-bit mode. Support for 8-bit and 16-bit transfers in U2 mode; 8-bit, 16-bit, and 32-bit transfers in U3 mode. Support for 16 data channels, each with (64X32) 256 bytes of FIFO storage, implemented as four ingress/egress slices with four subchannels each. Quad physical interfaces independently configurable as either 8-bit or 16-bit data paths. Support for up to two 32-bit data paths. (Use of a 32-bit interface will use two 16-bit interfaces.) Operation at 52 MHz for U2 or 104 MHz for U3 (85 MHz for U3 C/D interface, see Table 751). Multi-PHY support on all physical interfaces with some limitations and configuration options. Point-to-point non-MPHY operation supported at higher clock speeds. Legacy support for a MARS2G5 P-ProLT 5-bit MPHY addressing mode. The UT48 core provides buffering and UTOPIA interface functionality. This enhanced UTOPIA interface passes U2, U2+, U3, and U3+ protocols. In the receive direction, data is buffered from the line side, and sent out of the device via a UTOPIA/POS-PHY interface. In the transmit direction, data is received by the device via a UTOPIA/ POS-PHY interface, and is buffered before being sent to the line side. Data that is sent or received can be either packet or ATM traffic, and is configurable on a per-channel basis. The UTOPIA slave interface is designed to accommodate back-to-back ATM cell and packet data transfers in point-to-point or multi-PHY modes. The UTOPIA block consists of four independent physical interfaces with up to 16 logical channels. If the UT is configured as four interfaces, for example, each interface can handle up to STS-12/STM-4 traffic. If the UT is configured as one interface, that interface can handle up to STS-48/STM-16 traffic. Using MPHY 32-bit mode, the single 32-bit interface can supply data to either a single STS-48c channel or four STS-12c channels. All four physical interfaces (A, B, C, and D) can be configured independently to carry different traffic types at different rates. There are two basic data paths: receive side, defined as data going from the line side to the UTOPIA side, and transmit side, defined as data going from the UTOPIA side to the line side as shown in Figure 93. 716 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UTOPIA Interface Features (continued) INGRESS SLICE A INGRESS SLICE B DE INGRESS SLICE C INGRESS SLICE D RX CROSS BAR UPRX UPRX UPRX UPRX A B RX C D EGRESS SLICE A EGRESS MUX EGRESS SLICE B EGRESS SLICE C EGRESS SLICE D TX CROSS BAR UPTX UPTX UPTX UPTX A B TX C D DE MICRO I/F LINE (DATA ENGINE) SIDE UTOPIA SIDE 5-8370(F)r.2 Figure 93. UT48: Generic Structure of UTOPIA Block In the ingress direction, data arrives from the line (data engine (DE)) side, and is sent to one of 16 channels (A0 through D3). The most significant 2 bits of the channel ID are ignored, and the remaining 4 bits are associated with channels in the slice. The channel ID corresponding to a slice and a channel name is shown in Table 750. Table 750. Slices, Channels, and Channel IDs Slice A Ch. A0 A1 A2 A3 Ch. ID 000000 000001 000010 000011 Slice B Ch. B0 B1 B2 B3 Ch. ID 000100 000101 000110 000111 Slice C Ch. C0 C1 C2 C3 Ch. ID 001000 001001 001010 001011 Slice D Ch. D0 D1 D2 D3 Ch. ID 001100 001101 001110 001111 Each slice buffers data independently, and, when sufficient data has been stored into its FIFO, sends the data out of the slice via its UTOPIA-like interface. In the egress direction, data arrives from the various UTOPIA interfaces, and is stored in a channel's FIFO. Each FIFO serves both as a buffer and as a means to cross data from the egress UTOPIA side timing to the DE side timing. After sufficient data has been stored into the FIFO, it is sent out of the UT48 core when requested to do so by the DE. Data that is transported through the UT48 can be either ATM traffic or packet traffic. Each channel can be configured to carry only one type. That is, one channel could carry ATM traffic while others are carrying packet traffic. However, any one channel cannot carry both ATM and packet traffic simultaneously, unless ATM cells are viewed as 52/53 byte packets, and are transported using the packet mode for that UTOPIA channel. Note: If any one channel of a slice is configured to carry packet data, the interface connecting to the slice must be provisioned in packet mode even if the rest of the channels are carrying ATM cell traffic. Agere Systems Inc. 717 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UTOPIA Modes Each interface mode is capable of supporting various types of traffic with different bandwidth capabilities as summarized in Table 751. Table 752 highlights the interfaces that can be used to support the traffic types and data rates. Each interface type can be configured as point-to-point or multi-PHY. UTOPIA contains four slices in ingress/ egress direction with each slice comprising of four logical channels. A slice can only connect to one of the four interfaces while an interface can connect to more than one slices. Each channel in a slice can be configured differently to support the various traffic types, e.g., channel A0 passes ATM cells using STS-12c, channel B1 passes packets, etc. In point-to-point mode, only channel 0 of an interface's native slice is used (i.e., for interface A, channel A0). 32-Bit Mode Configuration (Necessary Configuration for Proper Operation) Example Provisioning a 32-Bit Interface on A (Both Interfaces A and B Need to be Configured) An active interface is one in which the enable and address inputs from a master device are actively decoded by MARS2G5 P-Pro and whose PA pins (PPA and/or SPA) may be used by the master to determine FIFO status. An inactive interface is one in which the enable and address inputs from a master device are ignored but whose PA pins may still be used to determine FIFO status in direct status or multiplexed status modes. If the multiplexed status polling scheme is to be utilized for the inactive interface, which has provisioned active channels in its native slice, the PollEnb bit needs to be turned on within the respective MODE register. When an active interface borrows data pins from an adjacent interface, it does not imply that the adjacent interface must also be active. It should be provisioned idle. Certain fields of the interface configuration register are always bound only to the associated physical interface (data width, OE mode, and PA response). Therefore, to provision a 32-bit interface on A, use the following rules as guidelines: 1. Provision interface A for 32-bit operation as specified in this data sheet. 2. Interface A data width should be set to 11, signifying 32-bit and active. 3. Interface B data width should be set to 00, signifying idle. 4. The OE mode and PA response bits for interface B should be the same as those for interface A. 5. For transmit only, when interface A is operating in MPHY mode and direct or multiplex status is required from inactive interfaces B, C, or D, then set the polling enable bit for each of those interfaces. 6. The remaining fields for interface B are don't care. If guideline 4 is not followed, then the composite data bus will have different behaviors between the A half and the B half with respect to 3-stating (OE mode difference) and latency (PA response difference). 718 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UTOPIA Modes (continued) Table 751. UTOPIA Traffic Types UTOPIA Mode U2/U2+, 8-bit MPHY Size Maximum Bandwidth Configuration Speed Non-MPHY 8 bits 52 MHz 155.52 Mbits/s (point-to-point) Up to 4-Channel MPHY (native slice) Up to 8-Channel MPHY Up to 16-Channel MPHY Non-MPHY 16 bits 622 Mbits/s (point-to-point) Up to 4-Channel MPHY (native slice) Up to 8-Channel MPHY Up to 16-Channel MPHY Non-MPHY 8 bits 104 MHz 622 Mbits/s (point-to-point) Up to 4-Channel MPHY 104 MHz 85 MHz Up to 8-Channel MPHY 104 MHz 85 MHz Up to 16-Channel MPHY 104 MHz 85 MHz Non-MPHY 16 bits 104 MHz 1.2 Gbits/s (point-to-point) Up to 4-Channel MPHY 104 MHz 85 MHz Up to 8-Channel MPHY 104 MHz 85 MHz Up to 16-Channel MPHY 104 MHz 85 MHz Non-MPHY 32 bits 104 MHz 2.5 Gbits/s (point-to-point) Up to 4-Channel MPHY 104 MHz 85 MHz Up to 8-Channel MPHY 104 MHz 85 MHz Up to 16-Channel MPHY 104 MHz 85 MHz Available Interfaces ATM cells only (U2)/ 4: A, B, C, D ATM cells/packets (U2+) 2: A, C 4: A, B, C, D Traffic Type U2/U2+, 16-bit 2: A, C ATM cells only (U3)/ 4: A, B, C, D ATM cells/packets (U3+) 2: A, B 2: C, D 1: A 1: C 1: A 1: C 4: A, B, C, D 2: A, B 2: C, D 1: A 1: C 1: A 1: C ATM cells only (U3)/ 2: A/B, C/D ATM cells/packets (U3+) 1: A/B 1: C/D 1: A/B 1: C/D 1: A/B 1: C/D U3/U3+, 8-bit U3/U3+, 16-bit U3/U3+, 32-bit Agere Systems Inc. 719 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UTOPIA Modes (continued) Table 752. Interface Configurations Supported Traffic ATM Traffic Rate to STS-12/STM-4 Interface Supported U2 or U2+ (8-bit or 16-bit modes) U3 or U3+ (8-bit, 16-bit, or32-bit modes) ATM Traffic Packet Traffic >STS-12/STM-4 to STS-12/STM-4 Notes -- In 32-bit mode, controls are used from channel A or C and data is used from channel A & B or C & D. U3 or U3+ In 32-bit mode, controls are used from channel A (16-bit or32-bit modes) or C and data is used from channel A & B or C & D. U2+ (16-bit mode) U3+ (8-bit, 16-bit or 32 bit modes) -- In 32-bit mode, controls are used from channel A or C and data is used from channel A & B or C & D. In 32-bit mode, controls are used from channel A or C and data is used from channel A & B or C & D. Packet Traffic >STS-12/STM-4 U3+ (16-bit or 32-bit modes) 720 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Receive Path (Ingress) The UTOPIA PHY Rx interface is designed to accommodate ATM cells as well as packet traffic. The interfaces supported include: UTOPIA level 2 (U2), enhanced UTOPIA level 2 (U2+), UTOPIA level 3 (U3), and enhanced UTOPIA level 3 (U3+). Enhanced refers to the extensions that have been added to support packet transfers. These extensions are the following: end of packet indication (RxEOP), byte on which packet ends in last word (RxSZ), and if the packet is to be aborted early (RxERR). An abort occurs, for example, if the check sum at the end of a packet is bad, or the end of a packet is reached prematurely. If the receive FIFO overflows because the master cannot process packet data fast enough, an RxERR will also be generated. An additional signal (relative to MARS2G5 P-ProLT) is the selected packet available (RxSPA), which gives a direct status indication on the selected FIFO. RxSPA signals are defined for active interfaces only and they indicate the status of the selected channel that currently has valid data on the RxDATA bus. Note: The start of packets must be word-aligned and the final word of a packet must be padded with dummy data (if needed), since this is required by the definition of the UTOPIA interface. The UTOPIA interface can be placed in a number of modes, 8-bit, 16-bit, or 32-bit mode. These modes are dependent on the type of traffic that is being carried in the ingress slice, as well as the rate of the traffic. If all four channels in a slice are in ATM mode, then the interface for that slice can be configured in ATM mode; however, if any of the four channels in a slice are in packet mode, then the interface for that slice should be configured in packet mode. During packet mode operation (supported from (TADM042G5 (TADMV1B))), it is possible to cause a minimum gap period to occur between packets on the ingress interface. In other words, it is possible to prevent back-to-back transfer on an interface. This behavior is affected as an interface parameter, which is a 3-bit field (11:9) in the RXMODE[A--D] (Table 770) provisioning registers. The contents of the field are the minimum number of cycles between packet transfers. Note that when a channel is provisioned in ATM mode, the gap feature of the interface is ignored. If ATM cells are being transported and the interface is placed in packet mode, there is no capability to abort ATM cells in case of a deviation from the expected EOP or size indication. This follows since EOP and size indications are not processed by the channel transferring ATM cells. This mainly affects the Tx direction. If it is an abnormal short ATM cell, the SOP of the next ATM cell will be ignored and the cell is attached to the short ATM cell. If it is an abnormal long ATM cell, the portion in excess of the normal ATM cell size will be discarded. While one ingress slice may be carrying ATM traffic, the others may be carrying packet traffic. However, not all interfaces can coexist at the same time. For example, if ingress interface A is configured as a 32-bit mode interface, then the ingress interface B cannot be used. Because each UTOPIA PHY interface has only 16 bits of output data, if ingress interface A is placed in 32-bit mode, ingress interface A will have to send the least significant 16 bits of data out via ingress interface B. The same principle applies to interfaces C and D. Agere Systems Inc. 721 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Receive Path (Ingress) (continued) Channel FIFO The (64x32) 256-byte UTOPIA Rx FIFO in each channel buffers data sent from the DE block to the UTOPIA interface. The FIFO accommodates four ATM cells or 256 bytes of packet data and manages the asynchronous nature of the UTOPIA interface. Overflow will only occur if the master device connected to the UTOPIA interface is having congestion problems. When overflow occurs, a head of FIFO discard is performed. In order to avoid the situation where part of one packet may be appended to another (if for example, an end of packet is discarded along with the data at the head of the FIFO), data is discarded until the start of the next packet is observed. Upon overflow, the RxERR and RxEOP signals are asserted to indicate to the master the corruption of the current packet. An alarm is also sent to the microprocessor. Underflow in the receive direction can occur when there is no data, or if only part of a packet has arrived and has been transmitted, and is normal behavior. Data is read from the FIFO when there is sufficient data in the FIFO. Sufficient data is defined to be a minimum amount of data in the FIFO (a programmable threshold, low watermark), or at least one end of packet stored in the FIFO. Provisioning of high watermark and low watermark thresholds is performed in terms of 32-bit words, not bytes. Receive Polled Packet Available (RxPPA). Signal behavior depends on whether packet or ATM mode is selected as described below. Assertion of RxPPA. In packet mode, RxPPA is asserted when the FIFO has more data than threshold low or there is an end of packet (EOP) inside the FIFO. In ATM mode, RxPPA is asserted when the FIFO contains at least one complete ATM cell. Deassertion of RxPPA. In packet mode, RxPPA is deasserted when the FIFO has less data than threshold minimum and there isn't any EOP inside the FIFO. In ATM mode, RxPPA is deasserted when the FIFO contains less than a complete ATM cell. 722 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Receive Path (Ingress) (continued) Figure 94 illustrates the receive side interface handshaking when operating in point-to-point mode with the RXPPA response provisioned to be a single cycle. In two-cycle mode, the RXSOP, RXDATA, and RXPPA signals are delayed for an additional cycle. In the figure, the master device initiates the transfer after observing an asserted packet available for the channel. The MARS2G5 P-Pro samples RXENB low on the first cycle and then asserts RXSOP/C and RXDATA on the second cycle. RXDATA is sampled on the rising edge of the next cycle by the master device. In this example, the master stops the transfer in the middle of the packet. Data with value c is valid on the cycle that RXENB goes inactive, and when RXENB returns, data is again valid on the first cycle after the slave observes an active RXENB (data value d). The packet transfer is complete when the slave asserts the RXEOP signal. If an error occurs in the packet, then the RXERR signal is asserted simultaneously with the RXEOP. RXERR is ignored if it is not asserted when RXEOP is active. 1 RXCLK 2 3 4 5 6 7 8 9 10 11 12 RXPPA RXENB RXSOP/C RXDATA[15:0] a b c d e RXEOP RXERR 5-8716(F) Figure 94. Receive-Side Interface Handshaking in Point-to-Point Mode (RXPPA as Single Cycle) Agere Systems Inc. 723 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Transmit Path (Egress) In the transmit direction, data arrives from the various UTOPIA interfaces and is stored in (64x32) 256-byte FIFOs of different channels. After sufficient data has been buffered into a FIFO, it is made available to be sent to the DE. Like the UTOPIA Rx interface, the UTOPIA Tx interface is designed with enhancements to accommodate packet traffic as well as ATM cells. Supported interfaces include the following: UTOPIA level 2 (U2) in 8-bit or 16-bit mode, enhanced UTOPIA level 2 (U2+) in 8-bit or 16-bit mode, UTOPIA level 3 (U3) in 8-bit, 16-bit or 32-bit mode, and enhanced UTOPIA level 3 (U3+) in 8-bit, 16-bit, or 32-bit mode. An additional signal (relative to MARS2G5 PProLT) is the selected packet available (TXSPA), which gives a direct status indication on the selected FIFO. TXSPA signals are defined for active interfaces only and they indicate the status of the selected channel that currently has valid data on the TxDATA bus. The UTOPIA Tx side can indicate to the ATM side to suspend the transfer, by deasserting TXPPA, when necessary. When the amount of data in the FIFO exceeds its programmable high watermark, it deasserts TXPPA. At this point, the ATM side knows that the UTOPIA Tx block can only accept a limited number of words, after which it will overflow. In this case, the ATM device must not exceed writing this limited number of words before suspending the transfer. Transfer is resumed once again when the FIFO falls below the high watermark. When transferring ATM cells, TXPPA is deasserted with SOP/SOC of the current cell unless UT is prepared to accept an entire new cell after the current transfer. This behavior complies with both, UTOPIA level 2 and level 3 standards. level 2 requires that TXPPA be deasserted at least four cycles before the end of the current cell if it does not have enough room to accept another complete cell. Level 3 requires deassertion of TXPPA with current cell's SOP if there is no space for another complete cell. Only level 3 specification is implemented in UT that automatically makes its behavior compliant with level 2 since SOP is at least four cycles before the end of the cell. Deassertion of TXPPA does not immediately suspend the transfer of the current cell because the entire cell must be transmitted without interruption. Transmit Polled Cell/Packet Available (TXPPA) Assertion of TXPPA. In packet mode, TXPPA is asserted when the FIFO has less data than threshold HIGH. In ATM mode, TXPPA is asserted when the FIFO has room for a complete ATM cell. Deassertion of TXPPA. In packet mode, TXPPA is deasserted when the FIFO has more data than threshold MAX. In ATM mode, TXPPA is deasserted with the current cell's SOP if the FIFO does not have enough room for another complete ATM cell on the following transmission. Low Watermark. The low watermark in the Tx direction is relevant for defining when data is sent from the UTOPIA block to the data engine. A particular egress slice will send data upon a request from the data engine if (1) there is greater than or equal to low threshold amount of data in the TxFIFO or (2) there is an end of packet (EOP) currently residing in the FIFO (which may possibly be below low watermark). Once data transmission to the data engine begins, it continues until it reaches the EOP, or until it reaches the end of the FIFO, where it is flagged as an underflow. The UTOPIA side notifies the data engine that it has run dry. The data engine can either insert a dry escape character into the data stream (dry mode, user-provisionable value, 0x7D20 default) or it can insert an abort character into the data stream (0x7D7E). 724 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Transmit Path (Egress) (continued) Tx FIFO The UTOPIA Tx FIFO is used to create an elastic store that can buffer bursts of data received via the UTOPIA Tx, faster than can be transmitted out of the path. After the FIFO exceeds a programmable watermark (threshold MAX), it indicates to the UTOPIA Tx master to stop sending data. The master can choose to ignore this request causing the risk of an overflow. The FIFO block buffers sixty four 32-bit words (256 bytes) of cell/packet data. The FIFO accommodates four ATM cells or 256 bytes of packet data to manage the asynchronous nature of the UTOPIA interface. Optionally, in the case of FIFO underflow, a 0x7D207D207D20 . . . will be inserted by the data engine into the middle of the packet if dry mode is provisioned and the default dry escape character is used (0x20). This will be removed at the far end by the device (provided the link is comprised of two devices and both sides of the link support dry mode). Figure 95 illustrates the transmit side interface handshaking when operating in point-to-point mode with the TXPPA response provisioned to be a single cycle. In two-cycle mode, the TXPPA signal is delayed an additional cycle. In the figure, the master device initiates the transfer after observing an asserted packet available for the channel by asserting the TXENB signal. The master places data and start of packet on the bus the same cycle as TXENB, and the MARS2G5 P-Pro samples the TXSOP and TXDATA on the following clock cycle (rising edge). In this example, the master stops transfer in the middle of the packet. Data with value c is valid on the cycle (rising edge) that TXENB goes inactive, and when TXENB returns, data is again valid on the first cycle (data value d). The packet transfer is complete when the master asserts the TXEOP signal. If an error occurs in the packet, then the TXERR signal is asserted simultaneously with the TXEOP. TXERR is ignored if it is not asserted when TXEOP is active. 1 TXCLK 2 3 4 5 6 7 8 9 10 11 12 TXPPA TXENB TXSOP/C TXDATA[15:8] a b c d e f g TXEOP TXERR 5-8717(F) Figure 95. Transmit-Side Interface Handshaking in Point-to-Point Mode (TXPPA as Single Cycle) Agere Systems Inc. 725 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Address Modes and Pin Assignments of MPHY Interfaces Table 753 shows the address bus assignment for each interface depending on data transfer modes and the number of MPHY groups. Since the UTOPIA block has a limited number of pins, pins are overlayed and concatenated to provide 5-bit address buses to each interface (& represents concatenation in Table 753). The three basic addressing pin assignments/overlays (and corresponding address modes) are as follows: 1. A2/A3 Address Mode. In 16-bit data transfer mode, a UTOPIA interface connected to only one slice (polling a maximum of four channels of a particular slice) uses its own 3-bit (for interface A or C) or 2-bit (for interface B or D) address bus. All four interfaces (ports) can be used independently in this mode. 2. A5' Address Mode. In 8-bit data transfer mode, unused transmit data pins of an active interface (port) are overlaid to form a 5-bit address bus for that interface. For example, TXADDRA[2:0] forms the most significant three bits and TXDATAA[7:6] forms the least significant two bits of the 5-bit transmit address bus for interface A. Similarly, the 5-bit receive address bus is formed with RXADDRA[2:0] and TXDATAA[1:0] (for interface A). Transmit data pins in other interfaces are also used in the same manner. All four interfaces can be used independently in this mode. 3. A5 Address Mode. In 32-bit data transfer mode, address pins of interfaces A and B (or C and D) are concatenated to form a 5-bit address bus. For example, TXADDRA[2:0] and TXADDRB[1:0] form the 5-bit transmit address bus for interface A. Only two interfaces, A (concatenated with B) and C (concatenated with D), are available in 32-bit data transfer mode/A5 address mode. If both interfaces are used simultaneously, each can poll a maximum of 8 channels (two slices). If only one interface is used, it can poll all 16 channels. Point-to-Point (non-MPHY) Mode. No address decoding is performed in non-MPHY mode. An active interface is directly connected to channel 0 of its native interface. For example, interface A is connected to channel 0 of slice A. Address mode selection is provided through parameters RxAddrMode[A--D][1:0] and TxAddrMode[A--D][1:0] bits [7:6] of registers 0x7012 (Table 773) and 0x7013 (Table 774). Table 753 shows address mode configurations depending on data transfer modes and the number of MPHY groups (active polling interfaces). Addr_mode = 0 configures an interface in non-MPHY mode. Addr_mode = 1 sets an interface in A2/A3 mode. Addr_mode = 2 configures an interface in A2/A3 mode for 16-bit data transfers and in A5' address mode for 8-bit data transfers. Addr_mode = 3 translates into A5 address mode for interface A&B or C&D. 726 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Address Modes and Pin Assignments of MPHY Interfaces (continued) Table 753. UTOPIA Address Modes Note: & represents concatenation. Tx/Rx I/F 4-Port Mode A2/A3 Tx A B C D Rx A B C D TXADDRA[2:0] 16-Bit Mode 2-Port Mode A5 TXADDRA[2:0] & TXADDRB[1:0] 8-Bit Mode 1-Port Mode A5 TXADDRA[2:0] & TXADDRB[1:0] or TXADDRC[2:0] & TXADDRD[1:0] 32-Bit Mode 1-Port Mode A5 TXADDRA[2:0] & TXADDRB[1:0] or TXADDRC[2:0] & TXADDRD[1:0] 4-Port Mode A5' TXADDRA[2:0] & TXDATAA[7:6] TXADDRB[1:0] & TXDATAB[7:5] TXADDRC[2:0] & TXDATAC[7:6] TXADDRD[1:0] & TXDATAD[7:5] 2-Port Mode A5 TXADDRA[2:0] & TXADDRB[1:0] 2-Port Mode A5 TXADDRA[2:0] & TXADDRB[1:0] 1-Port Mode A5 TXADDRA[2:0] & TXADDRB[1:0] or TXADDRC[2:0] & TXADDRD[1:0] Address Mode (addr mode) TXADDRB[1:0] TXADDRC[2:0] TXADDRC[2:0] & TXADDRD[1:0] TXADDRC[2:0] & TXADDRD[1:0] TXADDRC[2:0] & TXADDRD[1:0] TXADDRD[1:0] RXADDRA[2:0] RXADDRA[2:0] & RXADDRB[1:0] RXADDRB[1:0] RXADDRA[2:0] & RXADDRB[1:0] or RXADDRC[2:0] & RXADDRD[1:0] RXADDRC[2:0] RXADDRC[2:0] & RXADDRD[1:0] RXADDRD[1:0] RXADDRA[2:0] RXADDRA[2:0] RXADDRA[2:0] & & & RXADDRB[1:0] RXADDRB[1:0] RXADDRB[1:0] or or RXADDRB[1:0] RXADDRC[2:0] RXADDRC[2:0] & & & TXDATAB[2:0] RXADDRD[1:0] RXADDRD[1:0] RXADDRC[2:0] RXADDRC[2:0] RXADDRC[2:0] & & & TXDATAC[1:0] RXADDRD[1:0] RXADDRD[1:0] RXADDRD[1:0] & TXDATAD[2:0] RXADDRA[2:0] & TXDATAA[1:0] RXADDRA[2:0] & RXADDRB[1:0] Agere Systems Inc. 727 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Address Modes and Pin Assignments of MPHY Interfaces (continued) It should be noted that the RXADR and TXADR names shown in Table 754 are (virtual) UTOPIA address bits, not physical ball names as shown in the Pin Information tables. This table is intended to give a physical mapping of the permutation of UTOPIA port address bits in the three possible addressing modes (A2/A3, A5, and A5') of the UTOPIA interface. The left side of the table shows the pin-to-address bit mappings; the right side shows the address bitto-pin mappings. The TDAT column is provided as a reference to correlate MARS2G5 P-ProLT (TDAT042G5) pins to MARS2G5 P-Pro (TDAT162G52) pins. Table 754. MARS2G5 P-ProLT/MARS2G5 P-Pro UTOPIA (Virtual) Address Pin Mappings Pin V34 W32 W31 AL32 AL33 AN19 AL19 AP20 AP7 AL8 -- M34 M35 AE35 AE34 AE33 AR26 AM25 AM14 AP13 AN13 -- -- U33 G33 G32 Y34 W34 AM19 AN31 AM31 AP5 AM7 -- L33 L34 AD35 AD34 AD33 AP27 AR27 AM15 AR14 AP14 TDAT -- RXADRA1 RXADRA0 RXADRA3 RXADRA2 -- -- RXADRA4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TXADRA1 TXADRA0 TXADRA3 TXADRA2 -- -- TXADRA4 -- -- -- -- -- -- -- -- -- -- -- -- -- Pin-to-Address Bit Map A2/A3 A5 RXADRA2 RXADRA4 RXADRA1 RXADRA3 RXADRA0 RXADRA2 RXADRB1 RXADRA1 RXADRB0 RXADRA0 RXADRC2 RXADRC4 RXADRC1 RXADRC3 RXADRC0 RXADRC2 RXADRD1 RXADRC1 RXADRD0 RXADRC0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TXADRA2 TXADRA4 TXADRA1 TXADRA3 TXADRA0 TXADRA2 TXADRB1 TXADRA1 TXADRB0 TXADRA0 TXADRC2 TXADRC4 TXADRC1 TXADRC3 TXADRC0 TXADRC2 TXADRD1 TXADRC1 TXADRD0 TXADRC0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A5' RXADRA4 RXADRA3 RXADRA2 RXADRB4 RXADRB3 RXADRC4 RXADRC3 RXADRC2 RXADRD4 RXADRD3 -- RXADRA1 RXADRA0 RXADRB2 RXADRB1 RXADRB0 RXADRC1 RXADRC0 RXADRD2 RXADRD1 RXADRD0 -- -- TXADRA4 TXADRA3 TXADRA2 TXADRB4 TXADRB3 TXADRC4 TXADRC3 TXADRC2 TXADRD4 TXADRD3 -- TXADRA1 TXADRA0 TXADRB2 TXADRB1 TXADRB0 TXADRC1 TXADRC0 TXADRD2 TXADRD1 TXADRD0 Address RXADRA4 RXADRA3 RXADRA2 RXADRA1 RXADRA0 RXADRB4 RXADRB3 RXADRB2 RXADRB1 RXADRB0 RXADRC4 RXADRC3 RXADRC2 RXADRC1 RXADRC0 RXADRD4 RXADRD3 RXADRD2 RXADRD1 RXADRD0 -- TXADRA4 TXADRA3 TXADRA2 TXADRA1 TXADRA0 TXADRB4 TXADRB3 TXADRB2 TXADRB1 TXADRB0 TXADRC4 TXADRC3 TXADRC2 TXADRC1 TXADRC0 TXADRD4 TXADRD3 TXADRD2 TXADRD1 TXADRD0 -- -- -- Address Bit-to-Pin Map TDAT A2/A3 A5 AP20 -- V34 AL32 -- W32 AL33 V34 W31 W32 W32 AL32 W31 W31 AL33 -- -- -- -- -- -- -- -- -- -- AL32 -- -- AL33 -- -- -- AN19 -- -- AL19 -- AN19 AP20 -- AL19 AP7 -- AP20 AL8 -- -- -- -- -- -- -- -- -- -- AP7 -- -- AL8 -- -- -- -- AM31 -- U33 Y34 -- G33 W34 U33 G32 G33 G33 Y34 G32 G32 W34 -- -- -- -- -- -- -- -- -- -- Y34 -- -- W34 -- -- -- AM19 -- -- AN31 -- AM19 AM31 -- AN31 AP5 -- AM31 AM7 -- -- -- -- -- -- -- -- -- -- AP5 -- -- AM7 -- -- -- -- -- -- -- -- -- -- A5' V34 W32 W31 M34 M35 AL32 AL33 AE35 AE34 AE33 AN19 AL19 AP20 AP26 AM25 AP7 AL8 AM14 AP13 AN13 -- U33 G33 G32 L33 L34 Y34 W34 AD35 AD34 AD33 AM19 AN31 AM31 AP27 AR27 AP5 AM7 AM15 AR14 AP14 -- -- -- 728 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UTOPIA Loopbacks MARS2G5 P-Pro can be placed in loopback on a slice-by-slice basis. In near-end loopback (NELB), data from channels in the egress slice is transferred to the corresponding ingress channels instead of the DE. This data is then processed by the ingress slice and is returned to the UTOPIA master. In summary, near-end loopback data must traverse both the egress and ingress FIFOs. INGRESS SLICE A RX INGRESS SLICE B DE INGRESS SLICE C INGRESS SLICE D CROSS BAR UPRX UPRX UPRX UPRX A B RX C D EGRESS SLICE A EGRESS MUX TX EGRESS SLICE B CROSS EGRESS SLICE C EGRESS SLICE D SLICE D: NEAR-END LOOPBACK LINE (DATA ENGINE) SIDE BAR DE UPTX UPTX UPTX UPTX A B TX C D UTOPIA SIDE 5-8371(F)r.3 Figure 96. Near-End Loopback for Slice D Agere Systems Inc. 729 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Basic Modes of Operations The UTOPIA block has 16 logical channels arranged into four slices of four channels each. Four physical interfaces (namely A, B, C, and D) are available in the both transmit and receive directions that communicate with channels/ slices through a crossbar. Each interface uses 16-bit transmit and receive data buses, and some control signals to communicate with the master. Each channel is assigned a unique physical address through the microprocessor interface. The following are some possible configurations of MPHY polling groups. For 16-bit or 8-bit mode, up to four polling groups can be formed. For 32-bit mode, up to two polling groups with a maximum of eight channels each can be formed. All 16 channels can be arranged in a single polling group with either 8-bit, 16-bit, or 32-bit mode. PHY Channel Addresses When an active interface (port) connected to more than one slice selects a channel, every inactive interface whose native slice is connected to the active interface indicates status of the corresponding channel in its native slice. Table 755 below assumes one of four interfaces is active and connected to all four slices (meaning other three interfaces are inactive). In this case, if interface A is the active interface, and channel A0 is polled, PPA_A, PPA_B, PPA_C, and PPA_D will show the status of channel addresses A0, B0, C0, and D0, respectively. Table 755. PHY Channel Address Allocation Related to Status Signal Signal RXPPAA/TXPPAA RXPPAB/TXPPAB RXPPAC/TXPPAC RXPPAD/TXPPAD PHY Channel Address A0 B0 C0 D0 A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 730 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 97 shows the overall structure of the receive direction of the UTOPIA block illustrating connections between slices and physical interfaces. The figure shows all possible connections from four slices to four physical interfaces through configurable cross-bar switch. Each channel and its FIFO handle 32-bit data. A UTOPIA PHY Rx block (also referred to as interface) can connect to multiple slices but a slice cannot connect to more than one interface. UTOPIA BLOCK CROSS CONNECT RXPPAA /RXDATAA[15:0] RECEIVE CHANNEL A0 UTOPIA_ RXENBA/ PHY_RX RXADDRA [2:0] A3 RXPPAB /RXDATAB[15:0] RECEIVE CHANNEL B0 UTOPIA_ PHY_RX RXENBB /RXADDRB [1:0] B3 RXPPAC /RXDATAC[15:0] RECEIVE CHANNEL C0 UTOPIA_ PHY_RX C3 RXENBC /RXADDRC [2:0] RECEIVE CHANNEL D0 RXPPAD /RXDATAD[15:0] UTOPIA_ PHY_RX D3 RXENBD /RXADDRD [1:0] 5-8372(F)r.1U Figure 97. Overall Structure for Receive Direction Agere Systems Inc. 731 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 98 shows the overall structure of the transmit direction of the UTOPIA block. UTOPIA BLOCK CROSS CONNECT TXPPAA TRANSMIT CHANNEL A0 UTOPIA_ PHY_TX TXENBA/TXADDRA[2:0]/ TXDATAA[15:0] A3 TXPPAB TRANSMIT CHANNEL B0 UTOPIA_ PHY_TX TXENBB/TXADDRB[1:0]/ TXDATAB[15:0] B3 TXPPAC TRANSMIT CHANNEL C0 UTOPIA_ PHY_TX TXENBC/TXADDRC[2:0]/ TXDATAC[15:0] C3 TXPPAD TRANSMIT CHANNEL D0 UTOPIA_ PHY_TX D3 TXENBD/TXADDRD[1:0]/ TXDATAD[15:0] 5-8373(F)r.2U Figure 98. Overall Structure for Transmit Direction 732 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 99 shows the receive direction of UTOPIA block, illustrating the four polling groups with four channels each for 16-bit data transfer. Each polling group can be interfaced with different clocks. Note that this mode needs only 2-bit address bus per each interface. UTOPIA BLOCK RXPPAA/ RXDATAA[15:0] RECEIVE CHANNEL A0 UTOPIA_ PHY_RX RXENBA/ RXADDRA[2:0] A3 RECEIVE CHANNEL B0 UTOPIA_ PHY_RX RXENBB/ RXADDRB[1:0] B3 RXPPAC/ RXDATAC[15:0] RXPPAB/ RXDATAB[15:0] RECEIVE CHANNEL C0 UTOPIA_ PHY_RX C3 RXENBC/ RXADDRC[2:0] RECEIVE CHANNEL D0 UTOPIA_ PHY_RX D3 RXPPAD/ RXDATAD[15:0] RXENBD/ RXADDRD[1:0] 5-8374(F)r.3 Figure 99. Four Groups of Multi-PHY Devices of Four Channels for Receive Direction Agere Systems Inc. 733 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 100 shows the transmit direction of the UTOPIA block, which is also divided into the four groups of four channels each for 16-bit data transfer. UTOPIA BLOCK TXPPAA TRANSMIT CHANNEL A0 UTOPIA_ PHY_TX TXENBA/TXADDRA[2:0]/ TXDATAA[15:0] A3 TRANSMIT CHANNEL B0 UTOPIA_ PHY_TX B3 TXENBB/TXADDRB[1:0]/ TXDATAB[15:0] TXPPAB TRANSMIT CHANNEL C0 UTOPIA_ PHY_TX TXPPAC TXENBC/TXADDRC[2:0]/ TXDATAC[15:0] C3 TXPPAD TRANSMIT CHANNEL D0 UTOPIA_ PHY_TX D3 TXENBD/TXADDRD[1:0]/ TXDATAD[15:0] 5-8375(F)r.3 Figure 100. Four Groups of Multi-PHY Devices of Four Channels for Transmit Direction 734 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 101 shows a 32-bit mode Rx configuration, which is divided into two groups of eight channels. Data from and to the UTOPIA PHY Rx block is 32 bits wide. For the first eight channels, the most significant 2 bytes of data from the UTOPIA PHY Rx block are brought out through interface A, and the least significant 2 bytes of data from the UTOPIA PHY Rx block are sent to interface B. Each channel is addressed via a 5-bit address bus, which is concatenated by address bus A and B (or C and D) as shown in Figure 101. By operating this way, all eight channels can be treated as a polled multi-PHY group for 32-bit data transfer. The second eight-channel polling group is operated in the same way using interfaces C and D. UTOPIA BLOCK RXPPAA RECEIVE CHANNEL A0 UTOPIA_ PHY_RX RXENBA RXADDRA[2:0] & RXADDRB[1:0] RXDATAA [31:16] UTOPIA_ PHY_RX A3 RECEIVE CHANNEL B0 B3 RXDATAB [15:0] RECEIVE CHANNEL C0 UTOPIA_ PHY_RX C3 RECEIVE CHANNEL D0 RXPPAC RXENBC RXADDRC[2:0] & RXADDRD[1:0] UTOPIA_ PHY_RX RXDATAC [31:16] D3 CROSS-BAR SWITCH RXDATAD [15:0] 5-8376(F)r.3 Figure 101. Two Groups of Multi-PHY Devices of Eight Channels for Receive Direction Agere Systems Inc. 735 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 102 shows a 32-bit mode Tx configuration. When data coming from the outside of UTOPIA block is targeted to one of the first eight channels, the most significant two bytes of data are brought in through interface A. The least significant 2 bytes of data are brought in through interface B and sent to the UTOPIA PHY Tx block of the interface A. Each channel is addressed via a 5-bit address bus, which is concatenated by address bus A and B (or C and D) as shown in Figure 102. All eight channels are treated as a polling group. The second eight-channel polling group is also operated in the same way using interfaces C and D. UTOPIA BLOCK TXPPAA TXENBA UTOPIA_ PHY_TX TXDATAA [31:16] A3 TRANSMIT CHANNEL B0 UTOPIA_ PHY_TX TXADDRA[2:0] & TXADDRB[1:0] TRANSMIT CHANNEL A0 TXDATAB [15:0] B3 TRANSMIT CHANNEL C0 UTOPIA_ PHY_TX C3 TXDATAD [31:16] TXPPAC TXENBC TXADDRC[2:0] & TXADDRD[1:0] TRANSMIT CHANNEL D0 UTOPIA_ PHY_TX TXDATAD [15:0] D3 5-8377(F)r.4 Figure 102. Two Groups of Multi-PHY Devices of Eight Channels for Transmit Direction 736 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 103 shows the case when all 16 channels are arranged in a polling group. Although any of the physical interfaces can be used, interface A or C are recommended for 16 channel MPHY. In this example, interface A is activated. Each channel is addressed via a 5-bit address bus, which is concatenated by address bus A and B. Activated interface becomes master interfaces, and the RXPA (or TXPA) for the master interface shows the polled data availability (or room availability) of all 16 channels. Other interfaces that are not activated just show the data availability (or room availability) of their own slice channels by asserting RXPA (or TXPA). Address and interface mapping follows the multiplexed status polling of UTOPIA level 2 Standard Specification. According to multiplexed status polling of UTOPIA level 2 standard specification, PHY channel addresses are grouped together and are allocated in a fixed manner to one of the four status signals in each direction (TXPPAA, TXPPAB, TXPPAC, and TXPPAD, and RXPPAA, RXPPAB, RXPPAC, and RXPPAD) as shown in Table 755. The status signals are read simultaneously in one status poll cycle to show the status of their own slice channels. UTOPIA BLOCK RECEIVE CHANNEL A0 UTOPIA_ PHY_RX RXPPAA/ RXDATAA[15:0] RXENBA RXADDRA[2:0] & RXADDRB[1:0] RXPPAB RXPPAC RXPPAD A3 RECEIVE CHANNEL B0 UTOPIA_ PHY_RX B3 UTOPIA_ PHY_RX RECEIVE CHANNEL C0 C3 UTOPIA_ PHY_RX RECEIVE CHANNEL D0 RXCLKA RXCLKB D3 RXCLKC RXCLKD 5-8378(F)r.3 Figure 103. A Multi-PHY Device of 16 Channels for Receive 16-Bit or 8-Bit Modes Agere Systems Inc. 737 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Basic Modes of Operations (continued) Figure 104 shows the case when all 16 channels are arranged in a polling group in 32-bit mode. In this configuration, only interface A (with interface B) or interface C (with interface D) can be used. UTOPIA BLOCK RECEIVE CHANNEL A0 UTOPIA_ PHY_RX RXPPAA RXENBA RXADDRA[2:0] & RXADDRB[1:0] RXDATAA[31:16] & RXDATAB[15:0] A3 RECEIVE CHANNEL B0 RXPPAB RXPPAC RXPPAD B3 UTOPIA_ PHY_RX RECEIVE CHANNEL C0 UTOPIA_ PHY_RX C3 RECEIVE CHANNEL D0 UTOPIA_ PHY_RX RXCLKA RXCLKB D3 RXCLKC RXCLKD 5-8379(F)r.4 Figure 104. A Multi-PHY Device of 16 Channels of Receive 32-Bit Mode 738 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Mixed Modes of Operations Each slice can be operated in a different mode. For example, the first slice can be configured for 8-bit mode, the second slice can be configured for 16-bit mode, and the next two slices can be configured for 32-bit mode. Figure 105 shows this example of mixed mode operation in the receive direction. UTOPIA BLOCK RECEIVE CHANNEL A0 UTOPIA_ PHY_RX RXPPAA/ RXDATAA[7:0] RXENBA RXADDRA[2:0] & TXDATAA[1:0] A3 (U3 8-bit MODE) RXPPAB/ RXDATAB[15:0] RXENBB RXADDRB[1:0] RECEIVE CHANNEL B0 UTOPIA _PHY_RX B3 (U2 16-bit MODE) RECEIVE CHANNEL C0 RXPPAC RXENBC RXADDRC[2:0] & RXADDRD[1:0] RXPPAD C3 RXDATAC[31:16] RXDATAD[15:0] UTOPIA_ PHY_RX UTOPIA _PHY_RX RECEIVE CHANNEL D0 D3 (U3 32-bit MODE) 5-8380(F)r.3 Figure 105. Mixed Modes of Operations for Receive Direction Agere Systems Inc. 739 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) Mixed Modes of Operations (continued) The receive side and the transmit side of an MPHY channel can also be operated in different modes. For example, the receive side of channel A is operated in 16-bit mode while the transmit side of channel A is operated in 32-bit mode. Figure 106 shows this example of mixed modes of operation. UTOPIA BLOCK UTOPIA_ PHY_RX RXPPAA/ RXDATAA[15:0] RXENBA RXADDRA[2:0] RECEIVE CHANNEL A0 A3 (U2 16-bit MODE) TXPPAA TRANSMIT CHANNEL A0 UTOPIA _PHY_TX TXADDRA[2:0] & TXADDRB[1:0] TXDATAA[31:16] A3 (U3 32-bit MODE) TXDATAB[15:0] TXENBA 5-8381(F)r.3 Figure 106. Mixed Modes of Operation of the Receive Side and the Transmit Side 740 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) Reference Configurations Examples of various UTOPIA reference configurations are shown on Figure 107. In quad OC-12c configuration shown on Figure 107(A), four ATM devices are connected to one MARS2G5 P-Pro device, and each interface transports 16-bit data running at 52 MHz. Figure 107(B) depicts a single OC-48c configuration for one ATM device connected to one MARS2G5 P-Pro. Many other configurations are possible. MARS2G5 P-Pro UTOPIA U2 16-bit AT 52 MHz ATM DEVICE U2 U2 16-bit AT 52 MHz U2 U2 16-bit AT 52 MHz U2 U2 16-bit AT 52 MHz ATM DEVICE ATM DEVICE ATM DEVICE U2 (A) QUAD OC-12C CONFIGURATION WITH 4 ATMs MARS2G5 P-Pro UTOPIA U3 32-bit U3* 32-bit AT 104 MHz ATM DEVICE U3 32-bit U3 32-bit U3 32-bit (B) SINGLE OC-48C CONFIGURATION 5-8382(F)r.3TDATU * See Table 751 on page 719 for frequency limitations. Figure 107. Reference Configurations Agere Systems Inc. 741 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UTOPIA Interface Pin Description The UTOPIA external interface pins are listed and described in the following tables. Note: Pins whose names are marked with an asterisk (*) are only used in POS mode. Table 756. UTOPIA Tx Interface Pins that Have Different Meanings in Different Modes Pin Name TXADDRA[2:0] TXADDRB[1:0] TXADDRC[2:0] TXADDRD[1:0] Mode 8-bit (A5') Description TXADDRA[2:0] concatenated with TXDATAA[7:6] forms 5-bit address bus. TXADDRB[1:0] concatenated with TXDATAB[7:5] forms 5-bit address bus. TXADDRC[2:0] concatenated with TXDATAC[7:6] forms 5-bit address bus. TXADDRD[1:0] concatenated with TXDATAD[7:5] forms 5-bit address bus. TXADDR[A--D][1:0] selects a channel among four channels. If more than four channels are polled, then 32-bit mode (A5) configuration is used. TXADDRA[2:0] forms the most significant 3 bits and TXADDRB[1:0] forms the least significant 2 bits of the combined address bus for interface A. TXADDRC[2:0] forms the most significant 3 bits and TXADDRD[1:0] forms the least significant 2 bits of the combined address bus for interface C. TXDATA[A--D][15:8] are valid. TXDATA[A--D][15:0] are valid. TXDATAA[15:0] forms the most significant 16 bits 31:16, and TXDATAB[15:0] forms the least significant 16 bits 15:0 of the combined data bus. This is the same for TXDATAC[15:0] and TXDATAD[15:0]. Not used. 16-bit (A2/A3) 32-bit (A5) TXDATA[A--D] [15:0] 8-bit 16-bit 32-bit TXSZ[A--D] 8-bit Packet Mode 16-bit Packet Mode 32-bit Packet Mode TXSZ[A--D] = 0 indicates that the MS byte of TXDATA[A--D] is the end of packet, and TXSZ[A--D] = 1 indicates that the LS byte of TXDATA[A--D] is the end of packet existing in the current word. Microprocessor configurable. TXSZA is used in conjunction with TXSZB, with TXSZA forming the most significant bit. For the combined results, 00, 01, 10, and 11 indicate that the last byte of data is on the data bus bits 31:24, 23:16, 15:8, or 7:0, respectively. This is the same for TXSZC and TXSZD. Microprocessor configurable. 742 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UTOPIA Interface Pin Description (continued) Table 757. UTOPIA Rx Interface Pins that Have Different Meanings in Different Modes Pin Name RXADDRA[2:0] RXADDRB[1:0] RXADDRC[2:0] RXADDRD[1:0] Mode 8-bit (A5') Description RXADDRA[2:0] concatenated with TXDATAA[1:0] forms 5-bit address bus. RXADDRB[1:0] concatenated with TXDATAB[2:0] forms 5-bit address bus. RXADDRC[2:0] concatenated with TXDATAC[1:0] forms 5-bit address bus. RXADDRD[1:0] concatenated with TXDATAD[2:0] forms 5-bit address bus. RXADDR[A:D][1:0] selects a channel among four channels. If more than four channels are polled then 32-bit mode (A5) configuration is used. RXADDRA[2:0] forms the most significant 3 bits and RXADDRB[1:0] forms the least significant 2 bits of the combined address bus for interface A. RXADDRC[2:0] forms the most significant 3 bits and RXADDRD[1:0] forms the least significant 2 bits of the combined address bus for interface C. RXDATA[A:D][15:8] are valid. RXDATA[A:D][15:0] are valid. RXDATAA[15:0] forms the most significant 16 bits 31:16, and RXDATAB[15:0] forms the least significant 16 bits 15:0 of the combined data bus. This is the same for RXDATAC[15:0] and RXDATAD[15:0]. Not used. 16-bit (A2/A3) 32-bit (A5) RXDATA[A--D] [15:0] 8-bit 16-bit 32-bit RXSZ[A--D] 8-bit Packet Mode 16-bit Packet Mode 32-bit Packet Mode RXSZ[A--D] = 0 indicates that the MS byte of RXDATA[A--D] is the end of packet, and RXSZ[A--D] = 1 indicates that the LS byte of RXDATA[A--D] is the end of packet existing in the current word. Microprocessor configurable. RXSZA is used in conjunction with RXSZB, with RXSZA forming the most significant bit. For the combined results, 00, 01, 10, and 11 indicates that the last byte of data is on the data bus bits 31:24, 23:16, 15:8, or 7:0, respectively. This is the same for RXSZC and RXSZD. Microprocessor configurable. Agere Systems Inc. 743 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) FIFO Ganging FIFO ganging allows a slice's channel 1 FIFO (a1, b1, c1, d1) to be ganged/combined together with the same slice's channel 0 (a0, b0, c0, d0) to result in a 128x4 byte (512-byte) FIFO. Only channels 0 and 1 of the same slice can be combined together (e.g., a0a1, b0b1, c0c1, d0d1). This feature can be enabled by bit 2 of the Rx/TxPrv registers of channels a0, b0, c0, or d0. In slices where FIFO ganging is enabled, slice channel 1 must be idle (disabled) and not used. The FIFO thresholds must be adjusted to take advantage of the extra FIFO memory. The following settings can be used for channel b0/b1 ganging for ATM cells. Table 758. Channel B0/B1 Ganging Settings for ATM Cells Register RXPRVB0 TXPRVB0 RXTHB0 TXTHB0 RXTHMINB0 TXTHMAXB0 Settings 0x8005 0x8005 0x760E 0x5E0E 0x0000 0x0071 Channel 1 of a slice must be disabled when FIFO 0 and 1 are ganged. All channel 1 status signals are inactive and output their default values. Internal FIFO read and write addresses are extended from 7 to 8 bits to accommodate the increase in the storage locations of combined/ganged FIFO. Each slice can be configured in the gang mode. Packet Packing Packet packing provides a packet mode feature (ignored for ATM transfers) that compresses unused bytes between successive packets on the egress path, which are a natural artifact of a 32-bit datapath. The packet mode is enabled by asserting bit 8 of the Tx interface mode provisioning register. In addition, a time-out counter (TXWC[A--D]) should be provisioned to indicate the maximum number of UTOPIA interface clocks that should elapse before transferring the last word of a packet, so the tail of the packet does not become stuck in the datapath. The default value of 0 will cause the immediate transfer of the final word.Small Packet Enable (Transmit Interface) Unless provisioned otherwise, packets less than 4 bytes are discarded by UTOPIA transmit interface. A bit in STM_bypass register (0x700E, bit 15 -- TxSmallPktEn) can be set to prevent transmit interface from discarding packets less than 4 bytes. No such provisioning is necessary for receive interface since it passes on whatever comes from DE. Default Channel Configuration MARS2G5 P-Pro specific channel configuration settings is for the ATM mode of operation with threshold settings appropriate for ATM transfer. 744 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UTOPIA Interface Timing UTOPIA interface timing specifications are given for the transmit direction in Figure 108 and in Table 759, and for the receive direction in Figure 109 and in Table 760 (see page 746). Specifications for the UTOPIA clock interface are given in Table 761 (see page 747). TXCLK[D--A] t43 TXENB[D--A] TXSZ[D--A] TXPRTY[D--A] TXSOP[D--A] TXEOP[D--A] TXERR[D--A] TXDATA[D--A][15:0] t44 INPUTS t45 TXPPA[D--A] TXSPA[D--A] 5-7663(F).ar.2 Figure 108. Transmit UTOPIA Interface Timing Table 759. Transmit UTOPIA Interface Timing Specifications Parameter Setup Time: Inputs to TXCLK[D--A] Hold Time: Inputs from TXCLK[D--A] Propagation Delay, Clock to Output TXPPA[D--A], TXSPA[D--A] from TXCLK[D--A] Symbol t43 Test Conditions TXCLK[D--A] as U3/U3+ U2/U2+ TXCLK[D--A] as U3/U3+ U2/U2+ TXCLK[D--A] U3/U3+, CL = 25 pF U2/U2+, CL = 50 pF where CL = the load capacitance on the outputs Min 2 4 1 1 2 2 Max -- -- -- -- 4.5 13 Unit ns ns ns ns ns ns t44 t45 Agere Systems Inc. 745 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UTOPIA Interface Timing (continued) RXCLK[D--A] t47 t46 RXENB[D--A] OUTPUTS RXPPA[D--A] RXSPA[D--A] RXPRTY[D--A] RXSOP[D--A] RXEOP[D--A] RXERR[D--A] RXDATA[D--A][15:0] t48 5-7664(F).ar.3 Figure 109. Receive UTOPIA Interface Timing Table 760. Receive UTOPIA Interface Timing Specifications Parameter Set Up Time: RXENB[D--A] to RXCLK[D--A] Hold Time: RXENB[D--A] from RXCLK[D--A] Propagation Delay, Clock to Output: RXPPA[D--A], RXSPA[D--A], RXSZ[D--A], RXPRTY[D--A], RXSOP[D--A], RXEOP[D--A], RXERR[D--A], RXDATA[D--A](15:0) from RXCLK[D--A] Symbol t46 Test Conditions RXCLK[D--A] as U3/U3+ U2/U2+ RXCLK[D--A] as U3/U3+ U2/U2+ RXCLK[D--A] CL = 25 pF CL = 50 pF where CL = the load capacitance on the outputs Min 2 4 1 1 2 6.5 Max -- -- -- -- 6.5 13 Unit ns ns ns ns ns ns t47 t48 746 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UTOPIA Interface Timing (continued) Table 761. UTOPIA Interface Clock Specifications Note: See Table 751 on page 719 for frequency limitations. Mode U3+ Signal Name TXCLK[D--A] Parameter Transmit TXCLK Frequency TXCLK Duty Cycle TXCLK Peak-to-Peak Jitter TXCLK Rise/Fall Time TXCLK Skew Receive U3+ RXCLK[D--A] RXCLK Frequency RXCLK Duty Cycle RXCLK Peak-to-Peak Jitter RXCLK Rise/Fall Time RXCLK Skew Transmit U2+ TXCLK[D--A] TXCLK Frequency TXCLK Duty Cycle TXCLK Peak-to-Peak Jitter TXCLK Rise/Fall Time TXCLK Skew Receive U2+ RXCLK[D--A] RXCLK Frequency RXCLK Duty Cycle RXCLK Peak-to-Peak Jitter RXCLK Rise/Fall Time RXCLK Skew 52 MHz, Multi-PHY Signal 0 40 -- -- -- 50 60 5 2 1 MHz % % ns ns 52 MHz, Multi-PHY Signal 0 40 -- -- -- 50 60 5 2 1 MHz % % ns ns 104 MHz, Multi-PHY Signal 0 40 -- -- -- 104 60 2 2 1 MHz % % ns ns 104 MHz, Multi-PHY Signal 0 40 -- -- -- 104 60 2 2 1 MHz % % ns ns Test Conditions Min Max Unit Agere Systems Inc. 747 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Global Registers Table 762. (UTVER) Version Control (RO) Address 0x7000 Bit 15:8 7:0 Name -- UTVER Reserved. Block Version. Indicates version number of the UTOPIA block. Function Reset Default 0x00 0x02 Table 763. (XBARCFGRX) Cross-Bar Configuration Register for Rx (R/W) Note: Active interfaces at a minimum must be connected to their native slices. Address Bit Name RXIFDSEL RXIFCSEL RXIFBSEL RXIFASEL Function Connection from Slices (D, C, B, A) to Interface D. Connection from Slices (D, C, B, A) to Interface C. Connection from Slices (D, C, B, A) to Interface B. Connection from Slices (D, C, B, A) to Interface A. Reset Default 1000 0100 0010 0001 0x7002 15:12 11:8 7:4 3:0 Table 764. (XBARCFGTX) Cross-Bar Configuration Register for Tx (R/W) Note: Active interfaces at a minimum must be connected to their native slices. Address Bit Name TXIFDSEL TXIFCSEL TXIFBSEL TXIFASEL Function Connection from Slices (D, C, B, A) to Interface D. Connection from Slices (D, C, B, A) to Interface C. Connection from Slices (D, C, B, A) to Interface B. Connection from Slices (D, C, B, A) to Interface A. Reset Default 1000 0100 0010 0001 0x7003 15:12 11:8 7:4 3:0 Table 765. (INTSTATUS) Interrupts (RO) Address 0x7004 Bit 15:0 Name INT[D--A](3:0) Function Interrupt for Channel [D--A](3:0). Reset Default 0x0000 Table 766. (INTMASK) Interrupt Masks (R/W) Address 0x7008 Bit Name Function Reset Default 0xFFFF 15:0 INT[D--A](3:0)M If set, masks any interrupts from channel [D--A](3:0). 748 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Global Registers (continued) Table 767. (ARST) ARST Register (R/W) Address 0x700C Bit 15:8 7:4 3:0 Name -- Reserved. Function Reset Default 0xFF 0xF 0xF ARSTTX[D--A] Asynchronous Reset to Tx Slice D--A. Active-high. ARSTRX[D--A] Asynchronous Reset to Rx Slice D--A. Active-high. Table 768. (CORWN) Clear-On-Read or Clear-On-Write Select Register (R/W) Address 0x700F Bit 15:1 0 Name -- CORWN Reserved. Assert this bit for clear-on-read. Default is clear-on-write. Function Reset Default 0x0000 Agere Systems Inc. 749 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers Meanings for the fields of the provisioning registers are given below. Table 769. UTOPIA Provisioning Field Description Field Name Polling Enable Mode RXCLK Mode SPA Enable Mode Output Enable Mode Rx Min Pkt Gap/ Dummy Cycles (Packet mode only) Value Polling enabled (MPHY). Polling disabled (non-MPHY). Sink mode (receive clocks provided by UTOPIA master). Selected packet available (SPA) enable on. Enable off. Bypassed 3-state buffers for U3 operations. Operate in 3-state output mode as described in UTOPIA level 2. No gap (dummy cycles) between packets on the receive interface to ATM master. Auto halt mode: Insert dummy cycles after EOP until current channel is deselected. Provisioned number of dummy cycles (gaps) are inserted between packets. Data valid style: RXPPA indicates data valid. Follows the UTOPIA level 1 and level 2 standards. In packet mode, RXPPA always indicates data valid. Advanced notice style: Only used in ATM mode. RXPPA is deasserted coincident with RXSOC to indicate to the master that the corresponding port of the PHY has no subsequent cell available. This gives advanced notice to master device. Follows level 3 straw ballot. Encoding 1 0 0 1 0 1 0 000 111 001--110 1 Rx PPA Style 0 750 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 769. UTOPIA Provisioning Field Description (continued) Field Name Address Mode Value No address bit is assigned. Idle interface or point-to-point (non-MPHY) mode. a2/a3 mode: Use only their own address buses (3 bits for IF A and C, 2 bits for IF B and D). a5' mode: For 8-bit data width mode, borrow TXDATA pins to form 5-bit for all IFs. a5 mode: Borrow from neighboring IF to form 5-bit address bus. In this mode, TX/RXSZ 0 means MS byte, 1 means LS byte. In this mode, TX/RXSZ 1 means MS byte, 0 means LS byte. PPA Response PPA response is one clock later after ATM put address. Delays between RXDATA and RXENB is also defined as one cycle. PPA response is two clocks later after ATM put address. Delays between RXDATA and RXENB is also defined as two cycles. Odd. Even. IF Type Data Width ATM. Packet. Disabled (idle). 8 bit. 16 bit. 32 bit. Encoding 00 01 10 11 0 1 0 1 1 0 1 0 00 01 10 11 Size Mode Parity Agere Systems Inc. 751 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) The following table lists the registers used to provision Rx/Tx UTOPIA interfaces A--D. Refer to Table 771 on page 753 through Table 774 on page 757 for a description of these registers. Table 770. Rx/Tx UTOPIA Interface A--D Provisioning Registers Address 0x7010 (See Table 771.) 0x7011 (See Table 772.) 0x7012 (See Table 773.) 0x7013 (See Table 774.) 0x7014 (See Table 771.) 0x7015 (See Table 772.) 0x7016 (See Table 773.) 0x7017 (See Table 774.) 0x7018 (See Table 771.) 0x7019 (See Table 772.) 0x701A (See Table 773.) 0x701B (See Table 774.) 0x701C (See Table 771.) 0x701D (See Table 772.) 0x701E (See Table 773.) 0x701F (See Table 774.) Mnemonic PARERRA_PM PARERRA RxModeA TxModeA PARERRB_PM PARERRB RxModeB TxModeB PARERRC_PM PARERRC RxModeC TxModeC PARERRD_PM PARERRD RxModeD TxModeD D C B Interface A Default 0x0000 0x0000 0x000C 0x000C 0x0000 0x0000 0x000C 0x000C 0x0000 0x0000 0x000C 0x000C 0x0000 0x0000 0x000C 0x000C 752 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 771. (PARERRA_PM) Interface A Error Count in PMRST Mode (RO) Address 0x7010 Bit Name Function Reset Default 0x0000 15:0 Parity Error Count Tx A Counts the number of parity errors that occur for Tx port A. Only on the rising edge of PMRST signal, the value of this register is updated. Table 772. (PARERRA) Interface A Error Count (RO/COR) Note: A clock must be provided to the UTOPIA transmit clock pins for each port that requires register access and the UTOPIA FIFOs must be reset. Address 0x7011 Bit Name Function Reset Default 0x0000 15:0 Parity Error Count Tx A Counts the number of parity errors that occur for Tx port A. The value of this register is updated in real time. Table 773. (RXMODEA) Rx Interface A Provisioning Registers (R/W) Address 0x7012 Bit 15 Name PollEnbRxA or (MPHYModeRxA) Function Polling Enable. This bit configures an interface in MPHY or nonMPHY (point-to-point) mode. When this bit is set, the interface decodes address pins as described in Table 9. When this bit is cleared to zero, the interface is in non-MPHY mode and connected to channel 0 of its native slice. RXADDR pins are not decoded. If multiplexed status polling is required, then this bit must be configured to a 1 for all interfaces that are generating PPA responses. For example, to obtain four PPA (PPAA, PPAB, PPAC, and PPAD) responses on a single polling cycle then all four interfaces require bit 15 to be set to 1. Reserved. RXSPA (Table 9) Enable. This bit enables the nonstandard RXSPA pin. When set to a one, RXSPA is enabled and drives a value whenever RXDATA, RXSOP, and RXEOP, etc. drive their values (U3 behavior, 3-state bypassed). When this bit is 0, RXSPA is 3-stated during its operation similar to other output pins in U2 mode. Reset Default 0 14 13 -- SPAEnRxA 0 0 Agere Systems Inc. 753 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 773. (RXMODEA) Rx Interface A Provisioning Registers (R/W) (continued) Address 0x7012 Bit 12 Name OutputEnRxA Function Reset Default 0 11:9 8 Output Enable Mode (3-State Buffer Override). When set to 1, the 3-state enable circuits for RxData, RxSOP, etc. are overridden so that they are continuously driven regardless of RxEnb. When cleared to 0, the 3-state enable circuits dynamically 3-state or drive these outputs according to RxEnb. This pin was added for U3 compliance since in U3 only point-to-point connections between a PHY and the ATM layer are allowed. The output enable mode field for 32-bit interfaces should be set to the same value for both A and B. If an interface is not used, then keep the default value in this register. Only when an interface is used in conjunction with another interface, i.e., A/B or C/D 32-bit modes, must the OE bit and the PA response bit be set the same on both interfaces. 000 UT _MINGAP_ Minimum number of gap (dummy cycles) between packet transfers. PCKT000 = No gap (default) MODE[2:0]/ 001 = 1 cycle gap DummyCy010 = 2 cycles gap cleRxA[2:0] 011 = 3 cycles gap 100 = 4 cycles gap 101 = 5 cycles gap 110 = 6 cycles gap 111 = Auto halt mode; insert dummy cycles after EOP until current channel is deselected. In this mode, channel must be reselected in between successive packets (i.e., RxEnbA must be toggled). 0 RxPPAStyleA UTOPIA level 2 and level 1 standard require RXCLV to be asserted for the duration of the transfer. The availability of the next cell is not (Advanc ed known until the current cell is transferred completely. This mode, the data valid mode, is activated by setting RxPPAStyle[A--D] bit Notice to 1. In packet transfer mode, data valid style is automatically used. Mode) UTOPIA level 3 requires an initiated transfer to proceed until the end of the cell without interruption. In compliance with level 3, RXCLV can be set in advanced notice mode (by setting RxPPAStyleA bit to 0) where RXCLV indicates next cell's availability with the SOP of current cell being transferred. 754 modified: August 20, 1999 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 773. (RXMODEA) Rx Interface A Provisioning Registers (R/W) (continued) Address 0x7012 Bit 7:6 Name RxAddrModeA Address Mode Selection. In MPHY configurations, each PHY is to have five dedicated Rx address pins according to U2 and U3. Since there are only 10 pins available for Rx addressing, it is not possible for all four interfaces to have the full five RXADDR (Table 9) pins at one time. To address this issue, the MARS2G5 P-Pro has three different ways to assign address pins to interfaces: 1. A2/A3 mode (local address mode)--In this mode, only the address pins that are local to this interface are used by it. Since the 10 available address pins cannot be equally divided among the four interfaces, the distribution is for interfaces A and C to have 3 pins each and interfaces B and D to have 2 pins each. It is true that the channels connected to interfaces A and C are limited to addresses 0x00--0x07 and that the channels connected to interfaces B and D are limited to addresses 0x00-- 0x03. This should not be a limitation; however, because when all four interfaces are active, each interface can only address four channels maximum. 2. A5' mode (TXDATA [Table 9] borrowing address mode)--If the data width of this interface is 8 bits, then only half of the TXDATA inputs of the corresponding Tx interface are actually used. In this mode, some of the unused TXDATA inputs are borrowed so that this Rx interface can have a full complement of five Rx address pins (2 pins borrowed for interfaces A and C and 3 pins borrowed for interfaces B and D). 3. A5 mode (adjacent interface borrowing address mode)--If the data width is 16 bits or 32 bits, then there are no unused TXDATA inputs to use as address pins. The only alternative to achieve a full complement of five address pins is to borrow the local address pins of the adjacent interface. This mode is limited to interfaces A and C, which may borrow the two local address pins of interfaces B and D, respectively. In 16-bit mode, interfaces B and D must be nonpolling because their local pins are no longer available. In 32-bit mode, interfaces B and D must be inactive because their RXDATA pins are being borrowed. 00 = No address pins are connected to this interface (default). 01 = Local address mode. 10 = TXDATA borrowing address mode. 11 = Adjacent interface borrowing address mode. Function Reset Default 00 (nonMPHY) Agere Systems Inc. 755 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 773. (RXMODEA) Rx Interface A Provisioning Registers (R/W) (continued) Address 0x7012 Bit 5 Reset Default 0 RxSizeModeA This bit controls the polarity of the RXSZ pin (Table 9). When set to 1, RXSZ high indicates the MS byte and RXSZ low indicates the LS byte. When cleared to 0, RXSZ high indicates the LS byte and RXSZ low indicates the MS byte. In 32-bit mode, the RXSZ pin of the adjacent interface is borrowed to indicate one of four bytes. In this case, the size mode of both interfaces must be the same. When both mode bits are set to 1, RXSZ[A:B] = 11 indicates the MS byte and RXSZ[A:B] = 00 indicates the LS byte. When both mode bits are cleared to 0, RXSZ[A:B] = 11 indicates the LS byte and RXSZ[A:B] = 00 indicates the MS byte. The same applies for interface C and D. RxPPARespA This bit controls the latency of the Rx interface's outputs with respect to the changes on inputs (RXEnb and RxADDR). When set to 1, the interface will respond to polling and selection by RxAddr and RxEnb after two cycles (referred to as two cycle mode). When cleared to 0, the default setting, the Interface will respond after just one cycle (referred to as single cycle mode). For U1/U2 applications, therefore, single-cycle mode should be used and for U3 applications, twocycle mode should be used. If multiplexed status polling is required, then this bit must be configured to either a 1 (two cycle PA response) or 0 (single cycle PA response) for all interfaces that are generating PPA responses in multiplexed status mode. For example, to obtain four 2-cycle PPA (PPAA, PPAB, PPAC, and PPAD) responses on a single polling cycle, all four interface configuration registers must have bit 4 set to 1. Rx Parity Type. This bit controls if odd or even parity is generated for the data transmitted across the UTOPIA PHY Rx interface (RXPRTY pin (Table 9) polarity). When set to 1, RXPRTY will be odd and when cleared to 0, RXPRTY will be even. This bit determines whether this interface is in ATM mode or in packet mode. When set to 1, ATM mode is selected and when cleared to 0, packet mode is selected. In ATM mode, the RXERR, RXEOP, and RXSZ outputs will be 3-stated (or will drive 0s when in OE mode). In packet mode, the RXERR, RXEOP, and RXSZ pins will be driven along with the RXDATA, RXSOP, and RXPRTY pins. 0 Name Function 4 3 ParRxA 1 2 IFTypeRxA 1 1:0 If multiplexed status polling is required, this bit must be configured to either a 1 (ATM mode) or 0 (packet mode) for all interfaces that are generating PPA responses in multiplexed status mode. DataWidthRxA Receive Interface Data Width. These bits control the data width of this interface. Since only interfaces A and C can be 32-bit interfaces, 32-bit mode may not be selected for interfaces B and D. 00 = Disable interface. 01 = 8-bit mode. 10 = 16-bit mode. 11 = 32-bit mode. 00 756 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 774. (TXMODEA) Tx Interface A Provisioning Registers (R/W) Address Bit 0x7013 15 Name PollEnbTxA If set, polling mode is enabled. If multiplexed status polling is required, then this bit must be configured to a 1 for all interfaces that are generating PPA responses. For example, to obtain four PPA (PPAA, PPAB, PPAC, and PPAD) responses on a single polling cycle then all four interfaces require bit 15 to be set to 1. 14 13 -- SPAEnTxA Reserved. This bit configures the nonstandard TXSPA pin to behave in either 3state mode (U2) or in 3-state bypass mode (U3). When set to a one, TXSPA is always driven as other output pins in U3 mode (i.e., 3-state is bypassed). When cleared to 0, TXSPA is driven similar to other output pins in U2 behavior (3-state enable). 0 0 Function Reset Default 0 12 OutputEnTxA When this bit is set to 1, 3-state buffers are bypassed (UTOPIA level 3). When this bit is cleared to 0, outputs operate in 3-state mode behavior as described in UTOPIA level 2 (outputs are switched dynamically between 3-state and driven states). This bit overrides SPAEnModeRxA. -- TxWaitEnbA Reserved. Enables packet packing (packet gap compression feature) on transmit interface. Packet packing provides a packet mode feature (ignored for ATM transfers) that compresses unused bytes between successive packets on the egress path, which are a natural artifact of a 32-bit datapath. The packet mode is enabled by asserting bit 8 of the Tx interface mode provisioning register. In addition, a time-out counter (TXWC[A--D]) should be provisioned to indicate the maximum number of UTOPIA interface clocks that should elapse before transferring the last word of a packet so that the tail of the packet does not become stuck in the datapath. The default value of 0 will cause the immediate transfer of the final word. 0 11:9 8 000 0 (disabled) 7:6 TxAddrModeA Similar modes as receive side (RxAddrModeA) except in TXDATA borrowing address mode (TxAddrMode = 10), TXDATA[7:6] are borrowed instead TXDATA[1:0]. 5 TxSizeModeA In default (TxSizeMode = 0), TXSZA 0 means MS byte and 1 means LS byte. Otherwise, TXSZA 1 means MS byte and 0 means LS byte. In 32-bit mode for interface A, the TXSZA and TXSZB together indicate one of four bytes. Size mode of both interfaces must be the same. When both size mode bits are set to 1, TXSZ[A:B] = 11 indicates the MS byte and TXSZ[A:B] = 00 indicates the LS byte. When both are cleared to 0, TXSZ[A:B] = 11 indicates the LS byte and TXSZ[A:B] = equal to 00 indicates the MS byte. Same applies for interface C and D. 00 (nonMPHY) 0 Agere Systems Inc. 757 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 774. (TXMODEA) Tx Interface A Provisioning Registers (R/W) (continued) Address 0x7013 Bit 4 Name TxPPARespA Function In default value of this register bit, PPA response related to polling address is 1 clock later (for U2 mode operations); otherwise, 2 clocks later (for U3 mode). If multiplexed status polling is required, then this bit must be configured to a either a 1 (two cycle PA response) or 0 (single cycle PA response) for all interfaces that are generating PPA responses in multiplexed status mode. For example, to obtain four 2-cycle PPA (PPAA, PPAB, PPAC, and PPAD) responses on a single polling cycle, all four interface configuration registers must have bit 4 set to 1. 3 2 ParTxA IFTypeTxA Defines if odd or even parity is generated for the data transmitted across the UTOPIA PHY Tx Interface. This bit determines whether this transmit interface is in ATM mode or in packet mode. When set to 1, ATM mode is selected and when cleared to 0, packet mode is selected. In ATM mode, the TXERR, TXEOP, and TXSZ inputs pins are ignored. In packet mode, these inputs (along with TXDATA, TXPRTY, and TXSOP) are used for packet handling. If multiplexed status polling is required, then this bit must be configured to a either a 1 (ATM mode) or 0 (packet mode) for all interfaces that are generating PPA responses in multiplexed status mode. 1:0 DataWidthTxA Transmit Interface Data Width. These bits control the data width of this interface. Since only interfaces A and C can be 32-bit interfaces, 32-bit mode may not be selected for interfaces B and D. 00 = Idle interface. 01 = 8-bit mode. 10 = 16-bit mode. 11 = 32-bit mode. Table 775. (TxWC[A--D]) Channel A--D Transmit Wait Register (R/W) Address Bit Name -- TxWC[A--D] Reserved. Interface A Tx Wait Cycles for Packet Packing. This time-out counter is provisioned to indicate the maximum number of UTOPIA interface clocks cycles that should elapse before transferring the last word of a packet so that the tail of the packet does not become stuck in the datapath. Packet packing feature enabled by bit 8 (TxWaitEnbA) of TXMODE[A--D] interface registers. Function Reset Default 0x00 0x000 00 1 1 Reset Default 0 0x7020 15:10 0x7021 9:0 0x7022 0x7023 758 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) The following table lists the registers used to provision UTOPIA channels (0--3) of interfaces [A--D]. Refer to Table 777 on page 760 through Table 784 on page 763 for a description of these registers. To see which registers refer to which channel, see Table 785. Table 776. UTOPIA Channel [A--D](0--3) Provisioning Registers Address 0x7030, 0x7038, 0x7040, 0x7048, 0x7050, 0x7058, 0x7060, 0x7068, 0x7070, 0x7078, 0x7080, 0x7088, 0x7090, 0x7098, 0x70A0, 0x70A8 0x7031, 0x7039, 0x7041, 0x7049, 0x7051, 0x7059, 0x7061, 0x7069, 0x7071, 0x7079, 0x7081, 0x7089, 0x7091, 0x7099, 0x70A1, 0x70A9 0x7032, 0x703A, 0x7042, 0x704A, 0x7052, 0x705A, 0x7062, 0x706A, 0x7072, 0x707A, 0x7082, 0x708A, 0x7092, 0x709A, 0x70A2, 0x70AA 0x7033, 0x703B, 0x7043, 0x704B, 0x7053, 0x705B, 0x7063, 0x706B, 0x7073, 0x707B, 0x7083, 0x708B, 0x7093, 0x709B, 0x70A3, 0x70AB 0x7034, 0x703C, 0x7044, 0x704C, 0x7054, 0x705C, 0x7064, 0x706C, 0x7074, 0x707C, 0x7084, 0x708C, 0x7094, 0x709C, 0x70A4, 0x70AC 0x7035, 0x703D, 0x7045, 0x704D, 0x7055, 0x705D, 0x7065, 0x706D, 0x7075, 0x707D, 0x7085, 0x708D, 0x7095, 0x709D, 0x70A5, 0x70AD 0x7036, 0x703E, 0x7046, 0x704E, 0x7056, 0x705E, 0x7066, 0x706E, 0x7076, 0x707E, 0x7086, 0x708E, 0x7096, 0x709E, 0x70A6, 0x70AE 0x7037, 0x703F, 0x7047, 0x704F, 0x7057, 0x705F, 0x7067, 0x706F, 0x7077, 0x707F, 0x7087, 0x708F, 0x7097, 0x709F, 0x70A7, 0x70AF Symbol INT[A--D](0--3) Default 0x0000 INT[A--D](0--3)m 0xFFFF RxPrv[A--D](0--3) 0x1F01 TxPrv[A--D](0--3) 0x1F01 RxTh[A--D](0--3) 0x360E TxTh[A--D](0--3) 0x1E0E RxThMin[A--D](0--3) 0x0000 TxThMax[A--D](0--3) 0x0031 Agere Systems Inc. 759 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 777. (INTA0) Channel A0--Overflow/Underflow (COR/COW) Address 0x7030 Bit 15:5 4 3 2 1 0 Name -- FifoOverflowTx Reserved. Tx FIFO overflow alarm. Function Reset Default 0x000 0 0 0 0 0 FifoAlmostFullRx FIFO almost full alarm for a head of FIFO discard. FifoUnderflowTx FIFO underflow occurred in the Tx FIFO. FifoOverflowRx Rx FIFO overflow alarm for a tail of FIFO discard. Ingress threshold high should be lowered to prevent this error. ParityErrorTx If set, indicates that a parity error was detected on the Tx channel. Table 778. (INTA0m) Channel A0--Overflow/Underflow Mask (R/W) Address 0x7031 Bit 15:5 4 3 2 1 0 Name -- FifoAlmostFullRxMask FifoOverflowTxMask FifoUnderflowTxMask FifoOverflowRxMask ParityErrorTxMask Reserved. If set, masks this interrupt from FifoAlmostFullRxx. If set, masks this interrupt from FifoOverflowTx. If set, masks this interrupt from FifoUnderflowTx. If set, masks this interrupt from FifoOverflowRx. If set, masks this interrupt from ParityErrorTx. Function Reset Default 0xFFE 1 1 1 1 1 760 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 779. (RxProvA0) Channel A0--Provisioning Registers (R/W) Address 0x7032 Bit 15 14:13 12:8 7:3 2 Name Function Reset Default 0 00 0x1F 0x00 0 Channel Enable Channel is disabled by default. Rx -- Rx Addr -- GangFifoRxA Reserved. Assigned (Configurable) Polling Address For This Channel. Reserved. FIFO Ganging. Allows a slice's channel 1 FIFO (a1, b1, c1, d1) to be ganged/combined together with the same slice's channel 0 (a0, b0, c0, d0) to result in a 128X4 byte (512-byte) FIFO. Only channels 0 and 1 of the same slice can be combined together (e.g., a0a1, b0b1, c0c1, d0d1). GangFifoRx[1:0] bits are provided in Rx/ TxPrv registers of channels a0, b0, c0, or d0 only. In slices where FIFO ganging is enabled, slice channel 1 must be idle (disabled) and not used. The FIFO thresholds must be adjusted to take advantage of the extra FIFO memory. Channel 1 of a slice must be disabled when FIFO 0 and 1 are ganged. All channel 1 status signals are inactive and output their default values. Internal FIFO read and write addresses are extended from 7 to 8 bits to accommodate the increase in the storage locations of combined/ganged FIFO. Each slice can be configured in the gang mode. 1 ATM SizeRx If traffic type is ATM cells, this bit indicates if UDF fields are transmitted across the UTOPIA PHY Rx interface. UDF is transmitted by default. If UDF is transmitted, then ATM cell size is 53 bytes (ATM Long Mode); otherwise, it is 52 bytes (ATM Short Mode). Configures channel to carry either ATM cells (default) or packets. 0 0 TrafficTypeRx 1 Table 780. (TxProvA0) Channel A0--Provisioning Registers (R/W) Address 0x7033 Bit 15 14:13 12:8 7:3 2 1 0 Name Function Reset Default 0 00 0x1F 0x00 0 0 1 Channel Enable Channel is disabled by default. Tx -- TxAddr -- GangFifoTxA ATMSizeTx TrafficTypeTx Reserved. Assigned (configurable) polling address for this channel. Reserved. FIFOs in transmit channels can also be ganged together as described receive channels above (RxProvA0 register). Defines whether this channel receives 53- (default) or 52-byte ATM cells. Valid only when traffic type is ATM cells. Configures channel to carry either ATM cells (default) or packets. Agere Systems Inc. 761 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) FIFO Threshold Provisioning To allow for more flexibility in performance tuning of a system, FIFO thresholds, previously ignored, are now utilized for ATM operation. The net result of this change is that FIFO thresholds must be provisioned for ATM cell applications for proper system operation. (Provisioning of thresholds in earlier versions of the device are simply ignored and cause no change in behavior.) An example set of thresholds for channel A0 would be: Register RXTHA0 (Table 781) set to 0x360E. Register TXTHA0 (Table 782) set to 0x1E0E. Register RXTHMINA0 (Table 783) set to 0x0000. Register TXTHMAXA0 (Table 784) set to 0x0031. Table 781. (RxThA0) Channel A0--Provisioning Registers (R/W) Address 0x7034 Bit 15 14:8 Name -- IngressThresholdHigh Reserved. Defines threshold before which overflow is detected. When input data cross this boundary (from bottom to top of the FIFO), head of FIFO is discarded until SOP for the next cell/packet is observed. Reserved. Defines how many words must be stored in the ingress FIFO before transmission out of the UTOPIA port, if an end of packet is not received. When input data cross this boundary (from bottom to top of the FIFO), RXPPA is asserted to indicate that there is enough data to send out. Function Reset Default 0 0x36 7 6:0 -- IngressThresholdLow 0 0x0E Table 782. (TxThA0) Channel A0--Provisioning Registers (R/W) Address 0x7035 Bit 15 14:8 Name -- EgressThresholdHigh Reserved. When input data cross this boundary (from top to bottom of the FIFO), TXPPA is asserted to indicate that there is enough room to accept data. Reserved. Defines how many words must be stored in the egress FIFO before transmission out of the UTOPIA port to DE, if an end of packet is not received. Function Reset Default 0 0x1E 7 6:0 -- EgressThresholdLow 0 0x0E 762 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Per-Interface Registers (continued) Table 783. (RxThMinA0) Channel A0--Provisioning Registers (R/W) Address 0x7036 Bit 15:5 6:0 Name -- Ingress ThresholdMin Reserved. If an end of packet is not received, when input data cross this boundary (from top to bottom of the FIFO), RXPPA is deasserted to indicate that there is not enough data to send out. Function Reset Default 0 0 Table 784. (TxThMaxA0) Channel A0--Provisioning Registers (R/W) Address 0x7037 Bit 15:5 6:0 Name -- Egress ThresholdMax Reserved. Defines how many words can be stored into the egress FIFO before backpressure is applied to the UTOPIA PHY Tx port to stop acceptance of more traffic. When input data cross this boundary (from bottom to top of the FIFO), TXPPA is deasserted to indicate that there is not enough room to accept more data. Function Reset Default 0x00 0x31 Agere Systems Inc. 763 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Register Map Table 785. UT Register Map Note: Shading denotes reserved bits. Address 0x7000 0x7001 0x7002 0x7003 0x7004 0x7005 0x7006 0x7007 0x7008 0x7009 0x700A 0x700B 0x700C 0x700D 0x700E 0x700F Symbol UTVER SCRATCH XBARCFGRX XBARCFGTX INTSTATUS -- -- -- INTMASK -- -- -- ARST -- -- CORWN Type RO -- R/W R/W RO -- -- -- R/W -- -- -- R/W -- -- R/W Interface A Registers 0x7010 0x7011 0x7012 0x7013 PARERRA_PM PARERRA RXMODEA TXMODEA RO COR R/W R/W PollEnbRxA PollEnbTxA ClkModeRxA SPAEn RxA SPAEn TxA OutputEnRxA OutputEnTxA Interface B Registers 0x7014 0x7015 0x7016 0x7017 PARERRB_PM PARERRB RXMODEB TXMODEB RO COR R/W R/W PollEnbRxB PollEnbTxB ClkModeRxB SPAEn RxB SPAEn TxB OutputEnRxB OutputEnTxB Interface C Registers 0x7018 0x7019 0x701A 0x701B PARERRC_PM PARERRC RXMODEC TXMODEC RO COR R/W R/W PollEnbRxC PollEnbTxC ClkModeRxC SPAEn RxC SPAEn TxC OutputEnRxC OutputEnTxC UT_MINGAP_PCKTMODE[2:0] PARERRCNTTXC_PM PARERRCNTTXC PA StyleRxC WaitEnb TxC RxAddr ModeC TxAddr ModeC RxSizeModeC TxSizeModeC RxPARespC TxPARespC ParRxC ParTxC IF Type RxC IF Type TxC DataWidth RxC DataWidth TxC UT_MINGAP_PCKTMODE[2:0] PARERRCNTTXB_PM PARERRCNTTXB PA StyleRxB WaitEnb TxB RxAddr ModeB TxAddr ModeB RxSizeModeB TxSizeModeB RxPARespB TxPARespB ParRxB ParTxB IF Type RxA IF Type TxB DataWidth RxB DataWidth TxB UT_MINGAP_PCKTMODE[2:0] PARERRCNTTXA_PM PARERRCNTTXA PPA StyleRxA WaitEnb TxA RxAddr ModeA TxAddr ModeA RxSizeModeA TxSizeModeA RxPPARespA TxPPARespA ParRxA ParTxA IF Type RxA IF Type TxA DataWidth RxA DataWidth TxA CORWN ARSTTxD ARSTTxC ARSTTxB ARSTTxA ARSTRxD ARSTRxC ARSTRxB ARSTRxA IntD3M IntD2M IntD1M IntD0M IntC3M IntC2M IntC1M IntC0M IntB3M IntB2M IntB1M IntB0M IntA3M IntA2M IntA1M IntA0M IntD3 RXIFDSEL TXIFDSEL IntD2 IntD1 IntD0 IntC3 RXIFCSEL TXIFCSEL IntC2 IntC1 IntC0 IntB3 RXIFBSEL TXIFBSEL IntB2 IntB1 IntB0 IntA3 RXIFASEL TXIFASEL IntA2 IntA1 IntA0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VERSION[7:0] 764 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interface D Registers 0x701C 0x701D 0x701E 0x701F 0x7020 0x7021 0x7022 0x7023 0x7024 -- 0x702F PARERRD_PM PARERRD RXMODED TXMODED TxWCA TxWCB TxWCC TxWCD -- RO COR R/W R/W R/W R/W R/W R/W -- PollEnbRxD PollEnbTxD ClkModeRxD SPAEn RxD SPAEn TxD OutputEnRxD OutputEnTxD UT_MINGAP_PCKTMODE[2:0] PARERRCNTTXD_PM PARERRCNTTXD PA StyleRxD WaitEnb TxD RxAddr ModeD TxAddr ModeD RxSizeModeA TxSizeModeD RxPARespD TxPARespD ParRxD ParTxD IF Type RxD IF Type TxD DataWidth RxD DataWidth TxD Interface A Tx Wait Cycles for Packet Packing Interface B Tx Wait Cycles for Packet Packing Interface C Tx Wait Cycles for Packet Packing Interface D Tx Wait Cycles for Packet Packing Agere Systems Inc. 765 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel A0 Registers 0x7030 0x7031 INTA0 INTA0m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh Egress ThresholdHigh FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask Gang Fifo Rx Gang Fifo Tx IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel A1 Registers 0x7038 0x7039 INTA1 INTA1m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel A2 Registers 0x7040 0x7041 INTA2 INTA2m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx 0x7032 0x7033 0x7034 0x7035 0x7036 0x7037 RxPrvA0 TxPrvA0 RxThA0 TxThA0 RxThMinA0 TxThMaxA0 R/W R/W R/W R/W R/W R/W 0x703A 0x703B 0x703C 0x703D 0x703E 0x703F RxPrvA1 TxPrvA1 RxThA1 TxThA1 RxThMinA1 TxThMaxA1 R/W R/W R/W R/W R/W R/W 0x7042 0x7043 0x7044 0x7045 0x7046 0x7047 RxPrvA2 TxPrvA2 RxThA2 TxThA2 RxThMinA2 TxThMaxA2 R/W R/W R/W R/W R/W R/W 766 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel A3 Registers 0x7048 0x7049 INTA3 INTA3m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel B0 Registers 0x7050 0x7051 INTB0 INTB0m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask Gang Fifo Rx Gang Fifo Tx IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel B1 Registers 0x7058 0x7059 INTB1 INTB1m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx 0x704A 0x704B 0x704C 0x704D 0x704E 0x704F RxPrvA3 TxPrvA3 RxThA3 TxThA3 RxThMinA3 TxThMaxA3 R/W R/W R/W R/W R/W R/W 0x7052 0x7053 0x7054 0x7055 0x7056 0x7057 RxPrvB0 TxPrvB0 RxThB0 TxThB0 RxThMinB0 TxThMaxB0 R/W R/W R/W R/W R/W R/W 0x705A 0x705B 0x705C 0x705D 0x705E 0x705F RxPrvB1 TxPrvB1 RxThB1 TxThB1 RxThMinB1 TxThMaxB1 R/W R/W R/W R/W R/W R/W Agere Systems Inc. 767 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel B2 Registers 0x7060 0x7061 INTB2 INTB2m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel B3 Registers 0x7068 0x7069 INTB3 INTB3m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel C0 Registers 0x7070 0x7071 INTC0 INTC0m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask Gang Fifo Rx Gang Fifo Tx IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx 0x7062 0x7063 0x7064 0x7065 0x7066 0x7067 RxPrvB2 TxPrvB2 RxThB2 TxThB2 RxThMinB2 TxThMaxB2 R/W R/W R/W R/W R/W R/W 0x706A 0x706B 0x706C 0x706D 0x706E 0x706F RxPrvB3 TxPrvB3 RxThB3 TxThB3 RxThMinB3 TxThMaxB3 R/W R/W R/W R/W R/W R/W 0x7072 0x7073 0x7074 0x7075 0x7076 0x7077 RxPrvC0 TxPrvC0 RxThC0 TxThC0 RxThMinC0 TxThMaxC0 R/W R/W R/W R/W R/W R/W 768 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel C1 Registers 0x7078 0x7079 INTC1 INTC1m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel C2 Registers 0x7080 0x7081 INTC2 INTC2m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel C3 Registers 0x7088 0x7089 INTC3 INTC3m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx 0x707A 0x707B 0x707C 0x707D 0x707E 0x707F RxPrvC1 TxPrvC1 RxThC1 TxThC1 RxThMinC1 TxThMaxC1 R/W R/W R/W R/W R/W R/W 0x7082 0x7083 0x7084 0x7085 0x7086 0x7087 RxPrvC2 TxPrvC2 RxThC2 TxThC2 RxThMinC2 TxThMaxC2 R/W R/W R/W R/W R/W R/W 0x708A 0x708B 0x708C 0x708D 0x708E 0x708F RxPrvC3 TxPrvC3 RxThC3 TxThC3 RxThMinC3 TxThMaxC3 R/W R/W R/W R/W R/W R/W Agere Systems Inc. 769 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel D0 Registers 0x7090 0x7091 INTD0 INTD0m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask Gang Fifo Rx Gang Fifo Tx IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel D1 Registers 0x7098 0x7099 INTD1 INTD1m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax Channel D2 Registers 0x70A0 0x70A1 INTD2 INTD2m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx 0x7092 0x7093 0x7094 0x7095 0x7096 0x7097 RxPrvD0 TxPrvD0 RxThD0 TxThD0 RxThMinD0 TxThMaxD0 R/W R/W R/W R/W R/W R/W 0x709A 0x709B 0x709C 0x709D 0x709E 0x709F RxPrvD1 TxPrvD1 RxThD1 TxThD1 RxThMinD1 TxThMaxD1 R/W R/W R/W R/W R/W R/W 0x70A2 0x70A3 0x70A4 0x70A5 0x70A6 0x70A7 RxPrvD2 TxPrvD2 RxThD2 TxThD2 RxThMinD2 TxThMaxD2 R/W R/W R/W R/W R/W R/W 770 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface UTOPIA (UT) Block (continued) UT Register Map (continued) Table 785. UT Register Map (continued) Note: Shading denotes reserved bits. Address Symbol Type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel D3 Registers 0x70A8 0x70A9 INTD3 INTD3m COR/W R/W FifoAlmostFullRx FifoAlmostFull RxMask Channel Enable Rx Channel Enable Tx RxAddr TxAddr IngressThresholdHigh EgressThresholdHigh IngressThresholdLow EgressThresholdLow Ingress ThresholdMin Egress ThresholdMax FifoOverflowTx FifoOverflowTx Mask FifoUnderflowTx FifoUnderflow TxMask FifoOverflowRx FifoOverflow RxMask ATMSize Rx ATMSize Tx ParityErrorTx ParityErrorTx Mask TrafficType Rx TrafficType Tx 0x70AA 0x70AB 0x70AC 0x70AD 0x70AE 0x70AF 0x70B0 -- 0x73FF RxPrvD3 TxPrvD3 RxThD3 TxThD3 RxThMinD3 TxThMaxD3 -- R/W R/W R/W R/W R/W R/W -- Agere Systems Inc. 771 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 System Interface ATM Interfaces TXCLK[A] TXENB[A] TXPA[A] TXSZ[A] TXDATA[15:0][A] TXPRTY[A] TXSOP[A] TXEOP[A] TXERR[A] RXCLK[A] RXENB[A] RXPA[A] RXSZ[A] RXDATA[15:0][A] RXPRTY[A] RXSOP[A] RXEOP[A] RXERR[A] INTERFACE B INTERFACE C INTERFACE D AGERE MARS2G5 P-Pro DEVICE INTERFACE A TXDATA[15:0] TXPRTY TXSOC RXCLK RXENB RXCLAV RXDATA[15:0] RXPRTY RXSOC DEVICE #2 DEVICE #3 DEVICE #4 5-7412(F)r.4TDAT Figure 110. Quad 16-Bit ATM Level 2 772 ATM LINK LAYER DEVICE TXCLK TXENB TXCLAV Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface System Interface (continued) ATM Interfaces (continued) CLOCKS TXCLK RXCLK TXCLK[A] TXENB[A] TXPA[A] TXSZ[A] TXDATA[7:0][A] TXPRTY[A] TXSOP[A] TXEOP[A] TXERR[A] RXCLK[A] RXENB[A] RXPA[A] RXSZ[A] RXDATA[7:0][A] RXEOP[A] RXERR[A] RXPRTY[A] RXSOP[A] INTERFACE B INTERFACE C INTERFACE D AGERE MARS2G5 P-Pro DEVICE INTERFACE A TXDATA[7:0] TXPRTY TXSOC RXCLK RXENB RXCLAV RXDATA[7:0] RXPRTY RXSOC DEVICE #2 DEVICE #3 DEVICE #4 5-7413(F)r.4TDAT Figure 111. Quad 8-Bit ATM Level 3 Agere Systems Inc. ATM LINK LAYER DEVICE TXCLK TXENB TXCLAV 773 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 System Interface (continued) ATM Interfaces (continued) CLOCKS TXCLK RXCLK AGERE MARS2G5 P-Pro DEVICE RXCLK[A:B] RXENB[A] RXPA[A] RXSZ[A] RXDATA[15:0][A:B] RXPRTY[A] RXSOP[A] RXEOP[A] RXERR[A] RXCLK RXENB RXCLAV RXDATA[31:0] RXPRTY RXSOC ATM DEVICE TXCLK[A:B] TXENB[A] TXPA[A] TXSZ[A:B] TXDATA[15:0][A:B] TXPRTY[A] TXSOP[A] TXEOP[A] TXERR[A] TXCLK TXENB TXCLAV TXDATA[31:0] TXPRTY TXSOC 5-7414(F)r.3TDAT Note: In 32-bit mode, both A and B clocks must be connected. Figure 112. Single 32-Bit ATM Level 3 774 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface System Interface (continued) POS Interfaces TXCLK[A] TXENB[A] TXPA[A] TXSZ[A] TXDATA[15:0][A] TXPRTY[A] TXSOP[A] TXEOP[A] TXERR[A] RXCLK[A] RXENB[A] RXPA[A] RXSZ[A] RXDATA[15:0][A] RXPRTY[A] RXSOP[A] RXEOP[A] RXERR[A] TFCLK TENB TPA TMOD TDAT[15:0] TPRTY TSOP TEOP TERR RFCLK RENB RPA RMOD RDAT[15:0] RPRTY RSOP REOP RERR AGERE MARS2G5 P-Pro DEVICE INTERFACE B INTERFACE C INTERFACE D DEVICE #2 DEVICE #3 DEVICE #4 5-7415(F)r.3TDAT Figure 113. Quad 16-Bit POS Level 2 Agere Systems Inc. POS CUSTOMER LOGIC INTERFACE A 775 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 System Interface (continued) POS Interface (continued) CLOCKS TXCLK RXCLK AGERE MARS2G5 P-Pro DEVICE RXCLK[A] RXENB[A] RXPA[A] RXSZ[A] RXDATA[7:0][A] RXPRTY[A] RXSOP[A] RXPRTY[A] RXSOP[A] RXEOP[A] RXERR[A] INTERFACE B INTERFACE C INTERFACE D RFCLK RENB RFA RMOD RDAT[7:0] RPRTY RSOP REOP RERR DEVICE #2 DEVICE #3 DEVICE #4 5-7416(F)r.4TDAT Figure 114. Quad 8-Bit POS Level 3 776 POS CUSTOMER LOGIC INTERFACE A TXCLK[A] TXENB[A] TXPA[A] TXSZ[A] TXDATA[7:0][A] TXPRTY[A] TXSOP[A] TXEOP[A] TXERR[A] TFCLK TENB TPA TMOD TDAT[7:0] TPRTY TSOP TEOP TERR Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface System Interface (continued) POS Interface (continued) CLOCKS TXCLK RXCLK AGERE MARS2G5 P-Pro DEVICE RXCLK[A:B] RXENB[A] RXPA[A] RXSZ[A] RXDATA[15:0][A:B] RXPRTY[A] RXSOP[A] RXEOP[A] RXERR[A] RFCLK RENB RPA RMOD[1:0] RDAT[31:0] RPRTY RSOP REOP RERR POS DEVICE TXCLK[A:B] TXENB[A] TXPA[A] TXSZ[A:B] TXDATA[15:0][A:B] TXPRTY[A] TXSOP[A] TXEOP[A] TXERR[A] TFCLK TENB TPA TMOD[1:0] TDAT[31:0] TPRTY TSOP TEOP TERR 5-7417(F)r.4TDAT Note: In 32-bit mode, both A and B clocks must be connected. Figure 115. Single 32-Bit POS Level 3 Agere Systems Inc. 777 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Test Scan This device supports the IEEE 1149.1 JTAG interface for memory BIST, boundary scan, and 32-bit ID register instructions. Table 786. JTAG ID Register Codings JTAG ID Bit 31 30 29 28 Device ID 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Manufacturer ID 11 10 9 8 7 6 5 4 3 2 1 0 Device Version 2.1 Device Version 2.2 Device Version 2.3 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Boundary Scan Full boundary scan is supported on this device. Boundary scan is activated from the JTAG port. RAM BIST Embedded memories support BIST. The BIST algorithm is activated from the JTAG port. 778 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be safely soldered or bonded at temperatures up to 300 C. Parameter Storage Temperature VDDD Power Supply Voltage VDDD2 Power Supply Voltage Total Power Dissipation MARS2G5 P-Pro MARS1G2 P-Pro MARS622 P-Pro Symbol Tstg -- -- PDT Min -65 GND - 0.5 GND - 0.5 -- -- -- Max 125 VDDD + 0.5* VDDD2 + 0.5* 6.13 2.91 2.62 Unit C V V W W W * This maximum rating only applies when the device is powered up with VDDD. Depending on the application for both the 792 PBGA and 600 LBGA, a heat sink may be required (suggested heat sink assembly for 600-pin LBGA package (ChipCoolers part number HST357-D with airflow of 400 LFPM) or equivalent. Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 787. ESD Threshold Voltage Device MARS2G5 P-Pro 792-Pin PBGA MARS2G5 P-Pro 600-Pin LBGA Minimum HBM Threshold Low Speed Pins High Speed Pins >2000 V >2000 V >1000 V >1000 V Minimum CDM Threshold LVDS Pins >200 V >200 V All Pins Except LVDS >500 V >500 V Agere Systems Inc. 779 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Operating Conditions Parameter Power Supply Voltage: 3.3 V I/O 1.5 V Core Low-level Input Voltage: LVTTL LVPECL High-level Input Voltage: LVTTL LVPECL Power Dissipation MARS2G5 P-Pro Total: 3.3 V I/O 1.6 V Core (Typical) MARS1G2 P-Pro Total: 3.3 V I/O 1.6 V Core (Typical) MARS622 P-Pro Total: 3.3 V I/O 1.6 V Core (Typical) OC-48 Contraclocking 1x PLL 1.6 V Analog Power Supply Current @ 1.68 V OC-48 Contraclocking 1x PLL 1.6 V Digital Power Supply @ 1.68 V Junction Temperature Range Ambient Operating Temperature Range Symbol VDDD VDDD2 VILLVTTL VILLVPECL Min 3.165 1.42* GND - 0.3 VDDD - 1.810 Typ 3.3 1.6 -- -- -- -- 5.33 3.50 1.83 2.42 1.16 1.26 2.18 1.06 1.12 8.5 1.5 -- -- Max 3.465 1.68 0.8 VDDD - 1.475 5.5 VDDD - 0.880 5.87 3.85 2.02 2.66 1.28 1.39 2.40 1.17 1.23 9.35 1.65 125 85 Unit V V V V V V W W W W W W W W W mA mA C C VIHLVTTL 2.0 VIHLVPECL VDDD - 1.165 PDTTDAT16 -- -- -- -- -- -- -- -- -- IPLL_VDDA IPLL_VDDD TJ TA -- -- -40 -40 * For core voltage less than 1.5 V, the device has the following restrictions: UTOPIA C and UTOPIA D are only functional at 52 MHz or less. The thermal resistance junction to case, JC, of the 600 LBGA package is 0.4 C/W. The thermal resistance junction to ambient (to the nearest 0.5 C/W), JA, of the 600 LBGA package is given in the following table: Air Speed in Linear Feet per Minute (LFPM) JA (C/W) JEDEC Standard Natural Convection 100 200 500 800 9 8 6.5 6 5 The thermal resistance junction to case, JC, of the 792 PBGA package is 1.7 C/W. The thermal resistance junction to ambient (to the nearest 0.5 C/W), JA, of the 792 PBGA package is given in the following table: Air Speed in Linear Feet per Minute (LFPM) JA (C/W) JEDEC Standard Natural Convection 200 500 9.9 6.5 5.8 Depending on the application for both the 792 PBGA and 600 LBGA a heat sink may be required (suggested heat sink assembly for 600-pin LBGA package (ChipCoolers part number HST357-D with airflow of 400 LFPM) or equivalent. 780 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Electrical Characteristics Table 788. LVTTL 3.3 V Logic Interface Characteristics These logic levels are TTL 5 V compliant. Parameter Input Leakage Current Output Voltage: Low MPU_INTN, MPU_DTN, RXDATA[A--D][0--15], RXEOP[A--D], RXERR[A--D], RXPPA[A--D], RXPRTY[A--D], RXSOP[A--D], RXSPA[A--D], RXSZ[A--D], TXPPA[A--D], TXSPA[A--D], TDO GPIO[3--0], RXTOHCLK[A--D], RXTOHD[A--D], RXTOHF[A--D], RXREF, TXTOHCLK, TXTOHF High MPU_DTN, RXDATA[A--D][0--15], RXEOP[A--D], RXERR[A--D], RXPPA[A--D], RXPRTY[A--D], RXSOP[A--D], RXSPA[A--D], RXSZ[A--D], TXPPA[A--D], TXSPA[A--D], TDO GPIO[3--0], RXTOHCLK[A--D], RXTOHD[A--D], RXTOHF[A--D], RXREF, TXTOHCLK, TXTOHF Input Capacitance Load Capacitance Agere Systems Inc. CI CL Symbol IL VOLLVTTL -10 mA Test Conditions -- Min -- GND Max 20 0.4 Unit A V -6 mA VOHLVTTL 10 mA 2.4 VDDD V 6 mA -- -- -- -- 5.2 -- pF pF 781 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Electrical Characteristics (continued) Table 789. LVPECL 3.3 V Logic Interface Characteristics VDDD has a range of 3.165 V < VDDD < 3.465 V, VDDD typical = 3.3 V. Parameter Input Leakage Current Input Common-mode Voltage Range* Output Voltage: Low High Output Voltage Swing Input Capacitance Load Capacitance Input Buffer Gain * With a differential input swing of 100 mV minimum. Symbol IL VCMR VOLLVPECL VOHLVPECL VOSWING CI CL VG Min -- 0.8 VDDD - 1.97 VDDD - 1.025 0.595 -- -- -- Typical -- -- -- Max 20 2.6 VDDD - 1.620 VDDD - 0.72 Unit A V V V V pF pF dB -- -- -- 125 1.25 2.3 0.4 -- 782 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Outline Diagrams 792-Pin PBGA 40.00 38.70 +0.70 -0.05 35.35 MAX A1 BALL PAD CORNER A1 BALL PAD INDICATOR AVAILABLE MARKING AREA 40.00 38.70 +0.70 -0.05 35.35 MAX 17.72 TOP VIEW 4x 45 CHAMFER 1.17 0.05 30 TYP 8x 4.33 COUNTRY OF ORIGIN INDICATOR 0.50 0.10 SEATING PLANE 0.20 SIDE VIEW 0.61 0.06 SOLDER BALL 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 A C E G B D F H K M P T V Y AB AD AF AH AK AM AP AT AV 2.28 0.21 A1 BALL PAD CORNER 1.00 J L N R U W BOTTOM VIEW AA AC AE AG 0.63 +0.07 -0.13 SOLDER BALL DIAMETER PRIOR TO BEING ATTACHED TO THE PACKAGE 1.00 AJ AL AN AR AU AW 1.00 0.50 R, 3 PLACES THE CONTROLLING DIMENSIONS ARE IN MILLIMETERS. THIS DWG. CONFORMS TO JEDEC STDS. REF. DWG.-- 81949 5-9800(F)ar.2 Agere Systems Inc. 783 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Outline Diagrams (continued) 600-Pin LBGA 45.0 44.00 0.15 A1 BALL IDENTIFIER ZONE 45.00 44.00 0.15 B A 0.60 0.15 Z See Detail C C Z LOWEST BALL REFERENCE PLANE (PARALLEL TO GLOBAL PLANE) SOLDER BALL 34 SPACES @ 1.27 = 43.18 SOLDER BALL DIAMETER PRIOR TO BEING ATTACHED TO THE PACKAGE 0.15 Z AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 8 10 12 14 16 18 20 22 24 26 28 30 32 34 0.75 0.15 34 SPACES @ 1.27 = 43.18 A1 BALL CORNER Table 790. Substrate Thickness A 1.16 0.10 1.14 0.10 1.11 0.10 784 B 1.66 0.20 1.64 0.20 1.61 0.20 C 2.26 0.30 2.24 0.30 2.21 0.30 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Ordering Information Device Code Version Package* Derivatives TDAT162G52-BA23 TDAT162G52-3BAL M-TDAT162G52-3BAL2 TDAT161G2-BA23 TDAT12622-BA23 V2.3 V2.2 V2.0 792-pin PBGA 792-pin PBGA 792-pin PBGA Low-Speed Device V2.3 V2.3 792-pin PBGA 792-pin PBGA -40 C to +85 C -40 C to +85 C 700058138 700058137 -40 C to +85 C -40 C to +85 C -40 C to +85 C 700058140 700048364M 700023755M Temperature Comcode (Ordering Number) * Contact Agere Systems for other package options. These devices are only for existing customers using earlier versions of the device. All new customers are required to use the current 792-pin package device (please contact Marketing with any questions). Note: All references for the 600 LBGA found in this document are meant as support for existing customers. All new customers are required to use the current 792-pin package device (please contact Marketing with any questions). Agere Systems Inc. 785 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) (Version 2.2 and 2.3 Only) GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only) GFP block upgrade on transmit and receive to calculate the CRC-32 over only the payload information area. MARS2G5 P-Pro (version 2.0/2.1) calculated CRC-32 over everything except the PLI field. Two modes are supported for CRC-32 insertion/checking. 1. Null-extension headers. * 4-byte header. * Calculation starts after PLI field and 4 bytes of TYPE field. 2. Linear-extension headers. * 8-byte header. * Calculation starts after PLI field and 4 bytes of TYPE field and 4 bytes of EXT header field. PLI field value will be modified on transmit by +4 to include CRC-32 bytes. PLI field value will be modified on receive by -4 when CRC-32 is stripped. MARS2G5 P-Pro (version 2.2 and 2.3) does not touch PFI field value because it will corrupt tHEC. MPU Register Descriptions Table 24. MPU_VERR[0--5], Version Control Registers (RO) Address 0x0000 Bit 15:0 Name MPU_VER0 Function Indicates version number for version 2.2. Indicates version number for version 2.3. Reset Default 0x0227 0x0237 TOHP-48 Register Descriptions Table 60. TOHP_MODE_VERR, Mode (R/W) and Block Version (RO) Address 0x0800 Bit 15:13 Name Function Reset Default 011 TOHP_RX_MODE[2:0] Receive Direction Mode. TOHP_RX_MODE[2], bit 15, has two functions: default value for the registers and the number of errored frames required before declaring and OOF condition in the framer. [2] 1 = SDH, 0 = SONET [1] 1= OC-48, 0 = OC-3/12 [0] 1 = OC-12, 0 = OC-3 12:10 TOHP_TX_MODE[2:0] Transmit Direction Mode. TOHP_TX_MODE[2], bit 12, has two functions: default value for the registers and the number of errored frames required before declaring and OOF condition in the framer. [2] 1 = SDH, 0 = SONET [1] 1 = OC-48, 0 = OC-3/12 [0] 1 = OC-12, 0 = OC-3 011 9:0 TOHP_VER[9:0] Block Version Number. Block version register will change each time the device is changed. 0000000 001 786 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface MARS2G5 P-Pro (TDAT162G52) (Version 2.2 and 2.3 Only) (continued) TOHP-48 Register Descriptions (continued) Table 66. TOHP_CNTD[A--D][1--2], 0x081A--0x0821, Continuous N-Times Detect (CNTD) Values (R/W) Address 0x081A, 0x081C, 0x081E, 0x0820 Bit 15:12 Name TOHP_CNTDK2 [A--D][3:0] Function Continuous N-Times Detect for K2[2:0] Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDK2[A] is valid. Continuous N-Times Detect for APS (K1, K2[7:3]) Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDK1K2[A] is valid. Reset Default 0x3 11:8 TOHP_CNTDK1K2 [A--D][3:0] 0x3 7:4 TOHP_CNTDF1[A--D][3:0] Continuous N-Times Detect for F1 Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDF1[A] is valid. TOHP_CNTDJ0Z0 [A--D][3:0] Continuous N-Times Detect for J0Z0 Bytes. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, CNTDJ0Z0[A] is valid. Reserved. APS Babble. 0 = Use either K1 and K2[7:3] or K1 and K2[7:0] 1 = K1 only 0x3 3:0 0x3 0x081B, 0x081D, 0x081F, 0x0821 15:13 12 -- -- 0x0 -- 11:8 TOHP_CNTDS1BABLE [A--D][3:0] Continuous N-Times Detect for S1 Byte Babbling. The valid range for this register is 0x3-- 0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, TOHP_CNTDS1BABLE[A] is valid. Continuous N-Times Detect for S1 Byte. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, TOHP_CNTDS1[A] is valid. 0x5 7:4 TOHP_CNTDS1 [A--D][3:0] 0x3 3:0 TOHP_CNTDK1K2FRAME Continuous N-Times Detect for APS Frame. [A--D][3:0] The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. In STS-48 mode, TOHP_CNTDK1K2FRAME[A] is valid. 0xC Agere Systems Inc. 787 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) (Version 2.2 and 2.3 Only) (continued) TOHP-48 Register Descriptions (continued) Table 75. TOHP_SF_SETR[A--D][1--2], 0x0852--0x0859, Signal Fail Set BER Algorithm Control Registers [1--2] (R/W)* Address 0x0852, 0x0854, 0x0856, 0x0858 0x0853, 0x0855, 0x0857, 0x0859 0x0853, 0x0855, 0x0857, 0x0859 Bit 15:0 Name TOHP_SFNSSET [A--D][17:2] Function Signal Fail Ns Set. Number of frames in a monitoring block for signal fail (SF) of slice[A--D] is equal to TOHP_SFNSSET[A--D][17:0], respectively. Reset Default 0x00000 1:0 TOHP_SFNSSET [A--D][1:0] 15:10 TOHP_SFMSET [A--D][5:0] Signal Fail M Set. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is above this threshold, then signal fail is set. 0x00 9:2 TOHP_SFLSET[A--D][7:0] Signal Fail L Set. Error threshold for determining if a monitoring block is bad. 0x00 * See page 208 for the description of reading and writing parameters of more than 16 bits. 788 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface MARS2G5 P-Pro (TDAT162G52) (Version 2.2 and 2.3 Only) (continued) DE Register Descriptions Table 717. Rx Payload Type and Payload Control Summary Table Payload Control[12:0] Type[15:13] 12 11 000 PPP 001 CRC 010 HDLC 011 ATM 100 GFP 101 CRC GFP 110 Transparent Payload 111 Not defined * No discard--pass all ATM cells with no error correction. Discard--discard cells with multiple-bit header errors. Correct and pass all cells with single-bit header errors. Smart discard--discard cells with multiple-bit header errors, and only correct and pass the first of back-to-back single-bit header errors. 10 0 = discard 1 = no discard 9 8 Bit Sync 1 = no invert 0 = invert Bit Sync 1 = no invert 0 = invert Bit Sync 1 = no invert 0 = invert 7 0 = byte sync 1 = bit sync 6 0 = header stripped 1 = header on 5 4 3 2 1 0 0 = CRC-16 0 = CRC stripped 0 = CRC reversed 0 = no dry mode 1 = CRC-32 1 = CRC on 1 = CRC normal 1 = dry mode 00 = no unscrambling 01 = post-unscrambling 10 = pre-unscrambling 11 = undefined 00 = no unscrambling 01 = post-unscrambling 10 = pre-unscrambling 11 = undefined 00 = no unscrambling 01 = post-unscrambling 10 = pre-unscrambling 11 = undefined 00 = no discard* 01 = discard 10 = smart discard 11 = undefined 0 = byte sync 1 = bit sync 0 = CRC-16 0 = CRC stripped 0 = CRC reversed 0 = no dry mode 1 = CRC-32 1 = CRC on 1 = CRC normal 1 = dry mode 0 = byte sync 1 = bit sync 0 = no dry mode 1 = dry mode 0 = X43 scrambler 0 = scrambler on 0 = byte sync 1 = scrambler off 1 = bit sync Unassigned Cell 0 = discard 1 = passthrough 0 = length stripped 1 = length on 0 = idle cell discard 1 = idle cell passthrough 0 = X43 scrambler 0 = scrambler on 0 = byte sync 1 = X48 scrambler 1 = scrambler off 1 = bit sync See Table below for 0 = X43 scrambler 0 = scrambler on 0 = byte sync description of bits [12:10]. 1 = X48 scrambler 1 = scrambler off 1 = bit sync 0 = no align 1 = frame align Length offset = 0x0 to 0xF 0 = length 0 = CRC-16 0 = CRC stripped Length offset = 0x0 to 0xF stripped 1 = CRC-32 1 = CRC on 1 = length on Table 717. Rx Payload Type and Payload Control Summary Table (continued) Note: This is an expansion of Table 717 for Rx payload type CRC GFP bits [12:10] and applies to only version 2.2 and 2.3 of the device. 12 0 = Indicates non-GFP mode. 1 = Must be set to1 in CRC-GFP mode. 11 0 = PLI field unchanged. 1 = Subtract four from the PLI field if the CRC-32 bytes are stripped. 10 0 = Start CRC calculation after first 32 bits of payload (i.e., assume null extension header. 1 = Start CRC calculation after first 64 bits of payload (i.e., assume linear extension header. Agere Systems Inc 789 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) (Version 2.2 and 2.3 Only) (continued) DE Register Descriptions (continued) Table 741. Tx Payload Type and Payload Control Summary Table Payload Control[12:0] Payload Type[15:13] 000 PPP 001 CRC 010 HDLC 011 ATM 100 GFP 101 CRC GFP 110 Transparent Payload 111 Not Defined Table 741. Tx Payload Type and Payload Control Summary Table (continued) Note: This is an expansion of Table 741 for Rx payload type CRC GFP bits [12:10] and applies to only version 2.2 and 2.3 of the device. 12 0 = Indicates non-GFP mode. 1 = Must be set to 1 in CRC-GFP mode. See Table below for description of bits [12:10]. 12 0 = leading 1 = trailing 11 10 9 8 7 0 = HDLC byte 1 = HDLC bit 6 5 0 = CRC-16 1 = CRC-32 4 3 2 1 0 00 = 1 flag between packet Bit-Sync Inter-Pckg-Fill Bit Sync 01 = 2 flags between packets 0 = 7E 1 = no invert 0 = invert 10 = 3 flags between packets 1 = FF 11 = 4 flags between packets 00 = 1 flag between packet Bit-Sync Inter-Pckg-Fill Bit Sync 01 = 2 flags between packets 0 = 7E 1 = no invert 10 = 3 flags between packets 1 = FF 0 = invert 11 = 4 flags between packets 00 = 1 flag between packet Bit-Sync Inter-Pckg-Fill Bit Sync 01 = 2 flags between packets 0 = 7E 1 = no invert 10 = 3 flags between packets 1 = FF 0 = invert 11 = 4 flags between packets 0 = X43 scrambler 0 = scrambler on 1 = scrambler off 0 = scrambler on 1 = scrambler off 0 = scrambler on 1 = scrambler off 0 = CRC reversed 0 = no dry mode 1 = CRC normal 1 = dry mode 00 = no scrambling 01 = postscrambling 10 = prescrambling 11 = undefined 00 = no scrambling 01 = postscrambling 10 = prescrambling 11 = undefined 00 = no scrambling 01 = postscrambling 10 = prescrambling 11 = undefined 0 = leading 1 = trailing 0 = HDLC byte 1 = HDLC bit 0 = CRC-16 1 = CRC-32 0 = CRC reversed 0 = no dry mode 1 = CRC normal 1 = dry mode 0 = leading 1 = trailing 0 = HDLC byte 1 = HDLC bit 0 = no dry mode 1 = dry mode 0 = X43 scrambler 1 = X48 scrambler 0 = X43 scrambler 1 = X48 scrambler 0 = CRC-16 1 = CRC-32 11 0 = PLI field unchanged. 1 = Add four to the PLI field to include CRC-32 bytes. 10 0 = Start CRC calculation after first 32 bits of payload (i.e., assume null extension header). 1 = Start CRC calculation after first 64 bits of payload (i.e., assume linear extension header). 790 Agere Systems Inc Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface MARS2G5 P-Pro (TDAT162G52) (Version 2.3 Only) DE Register Descriptions Table 690. General Registers (RO) Address 0x6000 Bit 15:8 7:0 Name -- DE_VERSION[7:0] Reserved. Version ID. The version of the block will increment each time a change occurs to the block functionality. Indicates version number for version 2.0. Indicates version number for version 2.2. Indicates version number for version 2.3. Table 725. GFP Interrupt Masks R/W Address 0x65C0 -- 0x65CF Bit -- Name GFP_IRQEN_CH0 -- GFP_IRQEN_CH15 -- -- -- -- -- -- -- -- -- Function GFP Interrupt Mask Channel 0--15. When active (logic 1), the associated event/delta is inhibited from contributing to the interrupt on a per-channel basis. Reserved. B_Message Reception. A_Message Reception. Uncorrectable Special Payload Error. Uncorrectable Bit Error. Reserved. Must be set to 1. Single Bit Error. Scrambler Out of Sync. Framer State Mask Bit. Must be set to 1. Reset Default 0x00FF 0x03 0x07 Function Reset Default 0x00 0x02 15:8 7 6 5 4 3 2 1 0 0x00 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 Agere Systems Inc. 791 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) (Version 2.3 Only) (continued) DE Register Descriptions (continued) Determining the Per-Channel Framer State Bit 4 and bit 0 of registers 0x6600--0x660F (Table 727. GFP Interrupts (COW)) are used to determine the perchannel framer state. The following table indicates the per-channel framer state (see bit 0 of registers 0x6600-- 0x660F (Table 727. GFP Interrupts (COW))). Table 726. Per-Channel Framer State Uncorrectable Bit Error (Bit 4) 0 0 1 1 Framer State (Bit 0) 0 1 0 1 Per-Channel Framer State Out of frame In frame Undefined (Not Possible) Framing was lost since the last read of this register. Perform a COW and then read again to confirm if framing is still lost. Table 727. GFP Interrupts (COW) Address 0x6600 -- 0x660F Bit -- Name GFP_IRQ_CH0 -- GFP_IRQ_CH15 -- -- -- -- -- -- -- -- -- Function GFP Interrupt Channel 0--15. Used to record various occurrences within the GFP framer. The bits will generate an interrupt if defined by the interrupt mask, but the register values here are independent of the interrupt mask values. Reserved. B_Message Reception. A_Message Reception. Uncorrectable Special Payload Error. Uncorrectable Bit Error. Reserved. Single Bit Error. Scrambler Out of Sync. Framer State. This bit is a state bit and must always be masked to prevent constant presentation of an interrupt to the MPU. Bit 0 of registers 0x65C0--0x65CF (Table 725. GFP Interrupt Masks R/W) is the mask bit. The value contained in this bit will persist until a COW is performed, or until a transition (from 0 to 1) occurs on the signal. To determine the per-channel frame state, see Table 726. Per-Channel Framer State. Reset Default 0x0000 15:8 7 6 5 4 3 2 1 0 0x00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 792 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Line Loopback Block Introduction This is a feature offered for testing purposes only, to allow line loopback. The example of the loopback configuration script is available upon on request. Please contact your Agere Representative for details. Table 791. Loopback Mode Address 0x2080 Bit 15:12 11:8 Name -- -- Reserved. Loopback Mode for Streams A--D. 0 = Loopback Mode. Bit 11 = Stream A. Bit 10 = Stream B. Bit 9 = Stream C. Bit 8 = Stream D. 7:4 3:0 0x2090 15:12 11:8 7:4 3:0 0x2091 15 14:12 11 10:8 7 6:4 3 2:0 0x2094 0x2300 15:0 15:12 11:0 0x2301, 0x2302, 0x2303 15:12 11:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W/P MUX Control Selection for Line Loopback Stream A--D. Reserved. Stream A MUX Control. 1111 = Line Loopback Mode. Stream B MUX Control. MUX control settings as per stream A control. Stream C MUX Control. MUX control settings as per stream A control. Stream D MUX Control. MUX control settings as per stream A control. Reserved. Stream A MUX Control. 000 = Line Loopback. Reserved. Stream B MUX Control. MUX control settings as per stream A control. Reserved. Stream C MUX Control. MUX control settings as per stream A control. Reserved. Stream D MUX Control. MUX control settings as per stream A control. Reserved. Reserved. Selection of Line Loopback. 0 = Line Loopback selected. Reserved. Selection of Line Loopback. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 Function Reset Default 0 0 Agere Systems Inc. 793 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Line Loopback Block Introduction This is a feature offered for testing purposes only, to allow line loopback. The example of the loopback configuration script is available upon on request. Please contact your Agere Representative for details. Table 791. Loopback Mode Address 0x2310, 0x2311, 0x2312, 0x2313 0x2330 Bit 15:12 11:0 Name -- -- Reserved. Selection of Line Loopback. Function Reset Default -- 0 15:10 9:5 4:0 -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode. 0 = No override. Control for Line Loopback Mode. 0 = Line Loopback. Reserved. Control for W/P Line Loopback Mode Stream A--D. 0 = Line Loopback. Reserved. Reserved. Audited Line Loopback Time Slot 1--12. Reserved. Stream A, Time Slot 1 Mapping. 000 = Line Loopback Mode input port selection. Others = Unused. 0 0 0 0 0 0 0 0 0 0x2333 15:4 3:0 0x2334 0x2360-- 0x236B 0x2500 15:0 15:9 8:0 15:9 8:6 5:4 3:0 0x2501-- 0x250B 15:9 8:0 -- -- -- -- Reserved. Reserved. Reserved. Stream A, Time Slot 2--12 Mapping. 0 0 -- 0 794 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2520 0x2521 0x2522 0x2523 0x2524 0x2525 0x2526 0x2527 0x2528 0x2529 0x2530 0x2531 0x2532 0x2533 0x2534 0x2535 0x2536 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 Agere Systems Inc. Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream A. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2537 0x2540 0x2541 0x2542 0x2543 0x2544 0x2545 0x2546 0x2547 0x2548 0x2549 0x2550 0x2551 0x2552 0x2553 0x2554 0x2555 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 796 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream A. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2556 0x2557 0x2560 0x2561 0x2561 0x2562 0x2563 0x2564 0x2565 0x2566 0x2567 0x2568 0x2569 0x2570 0x2571 0x2572 0x2573 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 Agere Systems Inc. Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 797 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2574 0x2575 0x2576 0x2577 0x2580 0x2581 0x2582 0x2583 0x2584 0x2585 0x2586 0x2587 0x2588 0x2589 0x2590 0x2591 0x2592 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 798 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream B. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2593 0x2594 0x2595 0x2596 0x2597 0x25A0 0x25A1 0x25A2 0x25A3 0x25A4 0x25A5 0x25A6 0x25A7 0x25A8 0x25A9 0x25B0 0x25B1 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 Agere Systems Inc. Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 799 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x25B2 0x25B3 0x25B4 0x25B5 0x25B6 0x25B7 0x25C0 0x25C1 0x25C2 0x25C3 0x25C4 0x25C5 0x25C6 0x25C7 0x25C8 0x25C9 0x25D0 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 800 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream C. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x25D1 0x25D2 0x25D3 0x25D4 0x25D5 0x25D6 0x25D7 0x25E0 0x25E1 0x25E2 0x25E3 0x25E4 0x25E5 0x25E6 0x25E7 0x25E8 0x25E9 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 Agere Systems Inc. Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 801 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x25F0 0x25F1 0x25F2 0x25F3 0x25F4 0x25F5 0x25F6 0x25F7 0x2600-- 0x2617 0x2620-- 0x2637 0x2640-- 0x2657 0x2660-- 0x2677 0x2680-- 0x2697 0x26A0-- 0x26B7 0x26C0-- 0x26D7 0x26E0-- 0x26F7 0x2700-- 0x2717 0x2720-- 0x2737 Bit 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:9 8:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Line Loopback Mode Stream D. Reserved. Registers 0x2600--0x260B must be set to 0x0000--0x000B Reserved. Reserved. Registers 0x2640--0x264B must be set to 0x0010--0x001B Reserved. Reserved. Registers 0x2680--0x268B must be set to 0x0020--0x002B Reserved. Reserved. Registers 0x26C0--0x26CB must be set to 0x0030--0x003B Reserved. Reserved. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 802 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2740-- 0x2757 0x2760-- 0x2777 0x2780-- 0x2797 0x27A0-- 0x27B7 0x27C0-- 0x27D7 0x27E0-- 0x27F7 0x2800-- 0x2817 0x2820-- 0x2837 0x2840-- 0x2857 0x2860-- 0x2877 0x2880-- 0x2897 0x28A0-- 0x28B7 0x28C0-- 0x28D7 0x28E0-- 0x28F7 0x2900 0x2901 0x2902 0x2903 0x2904 0x2905 0x2906 0x2907 0x2908 0x2909 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 803 Agere Systems Inc. MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2910 0x2911 0x2912 0x2913 0x2914 0x2915 0x2916 0x2917 0x2920 0x2921 0x2922 0x2923 0x2924 0x2925 0x2926 0x2927 0x2928 0x2929 0x2930 0x2931 0x2932 0x2933 0x2934 0x2935 0x2936 0x2937 0x2940 0x2941 0x2942 0x2943 0x2944 0x2945 0x2946 0x2947 804 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2948 0x2949 0x2950 0x2951 0x2952 0x2953 0x2954 0x2955 0x2956 0x2957 0x2960 0x2961 0x2962 0x2963 0x2964 0x2965 0x2966 0x2967 0x2968 0x2969 0x2970 0x2971 0x2972 0x2973 0x2974 0x2975 0x2976 0x2977 0x2980 0x2981 0x2982 0x2983 0x2984 0x2985 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 805 Agere Systems Inc. MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x2986 0x2987 0x2988 0x2999 0x2990 0x2991 0x2992 0x2993 0x2994 0x2995 0x2996 0x2997 0x29A0 0x29A1 0x29A2 0x29A3 0x29A4 0x29A5 0x29A6 0x29A7 0x29A8 0x29A9 0x29B0 0x29B1 0x29B2 0x29B3 0x29B4 0x29B5 0x29B6 0x29B7 0x29C0 0x29C1 0x29C2 0x29C3 806 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Loopback Block (continued) Loopback Register Descriptions (continued) Table 792. Connection Memory Map (WO) Note: Use audit memories to read the connection maps Address 0x29C4 0x29C5 0x29C6 0x29C7 0x29C8 0x29C9 0x29D0 0x29D1 0x29D2 0x29D3 0x29D4 0x29D5 0x29D6 0x29D7 0x29E0 0x29E1 0x29E2 0x29E3 0x29E4 0x29E5 0x29E6 0x29E7 0x29E8 0x29E9 0x29F0 0x29F1 0x29F2 0x29F3 0x29F4 0x29F5 0x29F6 0x29F7 Bit 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Name -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Function Reset Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. 807 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet August 18, 2004 Appendix: Line Loopback Block Script Loopback Block Example Script This script should be used after full chip configuration, for debugging purpose only. writeport(0x2080, 0x0000); writeport(0x2090, 0x1111); writeport(0x2091, 0x0000); writeport(0x2600, 0x0000); writeport(0x2601, 0x0001); writeport(0x2602, 0x0002); writeport(0x2603, 0x0003); writeport(0x2604, 0x0004); writeport(0x2605, 0x0005); writeport(0x2606, 0x0006); writeport(0x2607, 0x0007); writeport(0x2608, 0x0008); writeport(0x2609, 0x0009); writeport(0x260a, 0x000a); writeport(0x260b, 0x000b); writeport(0x2640, 0x0010); writeport(0x2641, 0x0011); writeport(0x2642, 0x0012); writeport(0x2643, 0x0013); writeport(0x2644, 0x0014); writeport(0x2645, 0x0015); writeport(0x2646, 0x0016); writeport(0x2647, 0x0017); writeport(0x2648, 0x0018); writeport(0x2649, 0x0019); writeport(0x264a, 0x001a); writeport(0x264b, 0x001b); writeport(0x2680, 0x0020); writeport(0x2681, 0x0021); writeport(0x2682, 0x0022); writeport(0x2683, 0x0023); writeport(0x2684, 0x0024); writeport(0x2685, 0x0025); 808 Agere Systems Inc. Data Sheet August 18, 2004 MARS2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface Appendix: Line Loopback Block Script (continued) writeport(0x2686, 0x0026); writeport(0x2687, 0x0027); writeport(0x2688, 0x0028); writeport(0x2689, 0x0029); writeport(0x268a, 0x002a); writeport(0x268b, 0x002b); writeport(0x26c0, 0x0030); writeport(0x26c1, 0x0031); writeport(0x26c2, 0x0032); writeport(0x26c3, 0x0033); writeport(0x26c4, 0x0034); writeport(0x26c5, 0x0035); writeport(0x26c6, 0x0036); writeport(0x26c7, 0x0037); writeport(0x26c8, 0x0038); writeport(0x26c9, 0x0039); writeport(0x26ca, 0x003a); writeport(0x26cb, 0x003b); Agere Systems Inc. 809 Telcordia Technologies is a registered trademark of Telcordia Technologies, Inc. ANSI is registered trademark of American National Standards Institute, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. ISO is a registered trademark of The International Organization for Standardization. IEC is a registered trademark of The International Electrotechnical Commission. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc. MARS is a trademark of Agere Systems Inc. Copyright (c) 2004 Agere Systems Inc. All Rights Reserved August, 2004 DS02-197SONT |
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